CN108320775A

CN108320775A - Sram cell and its detection method, the detecting system of sram cell and SRAM device

Info

Publication number: CN108320775A
Application number: CN201710037835.8A
Authority: CN
Inventors: 甘正浩
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-18
Filing date: 2017-01-18
Publication date: 2018-07-24
Anticipated expiration: 2037-01-18
Also published as: CN108320775B

Abstract

A kind of sram cell and its detection method, the detecting system of sram cell and SRAM device, sram cell include：Storage unit, including the first phase inverter and the second phase inverter；Transmission unit, including the first transmission gate transistor and the second transmission gate transistor, the drain electrode of the first transmission gate transistor and the second transmission gate transistor are electrically connected with first node and third node respectively；Wordline is electrically connected with the first transmission gate transistor gate and the second transmission gate transistor gate；Bit line, including the first bit line and the second bit line, the first bit line and the second bit line are electrically connected with the source electrode of the first transmission gate transistor and the second transmission gate transistor respectively；The driving unit being electrically connected with bit line, for loading low level to second node and fourth node simultaneously；The reading unit being electrically connected with bit line pulls up transistor the sum of the output current to pull up transistor with second for reading first.Failure sram cell can be detected by the sram cell.

Description

Sram cell and its detection method, the detecting system of sram cell and SRAM device

Technical field

The present invention relates to the detections of semiconductor applications more particularly to a kind of sram cell and its detection method, sram cell System and SRAM device.

Background technology

In current semiconductor industry, IC products can be divided mainly into three categories type：Logic, memory and simulation Circuit, wherein memory device account for sizable ratio in IC products.As semiconductor technology develops, to memory Part is more widely applied, and needs the memory device and other device regions being formed simultaneously on a single die, with shape At embedded semiconductor storing equipment.Such as central processing unit will be embedded in the memory device, then it is required that described deposit Memory device carries out compatible with embedded central processing unit platform, and keeps the specification of original memory device and corresponding electricity Performance.

Usually, it needs to carry out the memory device with embedded standard logical devices compatible.It is partly led for embedded For body device, it is generally divided into logic area and memory block, logic area generally includes logical device, and memory block includes then memory Part.With the development of memory technology, there is various types of semiconductor memories, such as Static RAM (Static Random Access Memory, SRAM), dynamic RAM (Dynamic Random Access Memory, DRAM), Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read-Only Memory, EPROM), electric erasable Programmable read only memory (Electrically Erasable Programmable Read-Only, EEPROM) and flash memory (Flash).Since Static RAM has many advantages, such as low-power consumption and very fast operating rate so that Static RAM and Its forming method receives more and more attention.

Therefore it is urgent to provide a kind of new SRAM cell structures and its test method, mono- to detect failure SRAM in time Member.

Invention content

Problems solved by the invention be to provide a kind of sram cell and its detection method, the detecting system of sram cell and SRAM device, convenient for detecting failure sram cell.

To solve the above problems, the present invention provides a kind of sram cell, including：Storage unit, the storage unit include First phase inverter and the second phase inverter；Wherein, first phase inverter pulls up transistor and the first pull-down transistor including first, The source electrode of described first drain electrode and first pull-down transistor to pull up transistor is electrically connected, and described first pulls up transistor Drain electrode and first pull-down transistor source electrode tie point be first node, the described first grid to pull up transistor and The grid of first pull-down transistor is electrically connected, and the described first grid to pull up transistor and first pull-down transistor Grid tie point be second node；Second phase inverter pulls up transistor and the second pull-down transistor including second, institute The source electrode for stating drain electrode and second pull-down transistor that second pulls up transistor is electrically connected, and described second pulls up transistor The tie point of the source electrode of drain electrode and second pull-down transistor is third node, the described second grid to pull up transistor and institute State the grid electrical connection of the second pull-down transistor, and the described second grid to pull up transistor and second pull-down transistor The tie point of grid is fourth node；Wherein, the second node is electrically connected with the third node, the first node and institute State fourth node electrical connection；Transmission unit, including the first transmission gate transistor and the second transmission gate transistor, first transmission The drain electrode of door transistor is electrically connected with the first node, the drain electrode of the second transmission gate transistor and third node electricity Connection；Wordline is electrically connected with the grid of the grid of the first transmission gate transistor and the second transmission gate transistor；Position Line, including the first bit line and the second bit line, first bit line is electrically connected with the source electrode of the first transmission gate transistor, described Second bit line is electrically connected with the source electrode of the second transmission gate transistor；The driving unit being electrically connected with the bit line, the drive Moving cell is used to load low electricity to the second node and the fourth node simultaneously by the bit line and the transmission unit It is flat；The reading unit being electrically connected with the bit line, the reading unit are used to read by the bit line and the transmission unit Described first the first output current to pull up transistor and described second the sum of the second output current for pulling up transistor.

Correspondingly, the present invention also provides a kind of detection methods of sram cell, including：Sram cell above-mentioned is provided；It carries The threshold voltage reference value for for pulling up transistor；Relational expression between the threshold voltage to pull up transistor and output current is provided； Open the first transmission gate transistor and the second transmission gate transistor；The driving unit passes through first bit line and first Transmission gate transistor loads low level to the fourth node, makes described second to pull up transistor unlatching, second time crystal pulling Body pipe is closed, and described second, which pulls up transistor, exports the second output current；The driving unit also passes through the second simultaneously Line and the second transmission gate transistor load low level to the second node, make described first to pull up transistor unlatching, described the One pull-down transistor is closed, and described first, which pulls up transistor, exports the first output current；The reading unit passes through described first Transmission gate transistor, the first bit line, the second transmission gate transistor and the second bit line read first output current and second defeated Go out the sum of electric current；By the sum of first output current and second output current divided by two, output electric current measure value is obtained；According to The relational expression and the output electric current measure value obtain described first and pull up transistor the threshold to pull up transistor with described second Threshold voltage detected value；Compare the threshold voltage detected value and threshold voltage reference value, when the threshold voltage detected value and threshold Between threshold voltage reference value the absolute value of difference be more than preset difference value when, judgement described first pull up transistor with described second on Pull transistor fails.

Correspondingly, the present invention also provides a kind of detecting systems of sram cell, including：Sram cell above-mentioned；With it is described The connected computing unit of sram cell, for by the sum of the first output current of the sram cell and second output current divided by Two, output electric current measure value is obtained, and according to the relational expression between the threshold voltage and output current to pull up transistor, obtain institute First is stated to pull up transistor the threshold voltage detected value to pull up transistor with described second；The judgement being connected with the computing unit Unit, for providing the threshold voltage reference value to pull up transistor, and the threshold voltage detected value and threshold voltage ginseng Value is examined, when the absolute value of difference between the threshold voltage detected value and threshold voltage reference value is more than preset difference value, judgement Described first pulls up transistor pulls up transistor failure with described second.

Correspondingly, the present invention also provides a kind of SRAM devices, including：Multiple memory modules arranged in arrays, it is described to deposit It includes storage unit and transmission unit to store up module；The storage unit includes the first phase inverter and the second phase inverter；Described first Phase inverter pulls up transistor and the first pull-down transistor including first, under the described first drain electrode to pull up transistor and described first The source electrode of pull transistor is electrically connected, and the company of the source electrode of the described first drain electrode and first pull-down transistor to pull up transistor Contact is first node, the grid electrical connection of the described first grid to pull up transistor and first pull-down transistor, and institute The tie point for stating the grid of grid and first pull-down transistor that first pulls up transistor is second node；Described second is anti- Phase device pulls up transistor and the second pull-down transistor including second, the described second drain electrode to pull up transistor and second drop-down The source electrode of transistor is electrically connected, and the connection of the source electrode of the described second drain electrode and second pull-down transistor to pull up transistor It is third node to put, the grid electrical connection of the described second grid to pull up transistor and second pull-down transistor, and described The tie point of the grid of second grid to pull up transistor and second pull-down transistor is fourth node；The second node It is electrically connected with the third node, the first node is electrically connected with the fourth node；The transmission unit includes the first biography A transistor and the second transmission gate transistor, the drain electrode of the first transmission gate transistor is sent to be electrically connected with the first node, The drain electrode of the second transmission gate transistor is electrically connected with the third node；More wordline, each wordline and the matrix In with a line the first transmission gate transistor and the second transmission gate transistor grid correspond to electrical connection；More bit lines, packet Include the first bit line and the second bit line that more are arranged alternately, each first bit line and described first of same row in the matrix The source electrode of transmission gate transistor corresponds to electrical connection, second transmission gate of each second bit line and same row in the matrix The source electrode of transistor corresponds to electrical connection；The driving unit being electrically connected with the more bit lines, the driving unit is for passing through institute Rheme line and the transmission unit load low level to the second node and the fourth node simultaneously；With the more bit lines The reading unit of electrical connection, the reading unit are used to read crystal pulling on described first by the bit line and the transmission unit First output current of body pipe and described second the sum of the second output current for pulling up transistor.

Compared with prior art, technical scheme of the present invention has the following advantages：

Sram cell of the present invention includes the driving unit being electrically connected with bit line, and the driving unit is used for by described Bit line and the transmission unit load low level to the second node and the fourth node simultaneously, therefore work as sram cell work When making, the second pull-down transistor in the first pull-down transistor and the second phase inverter in the first phase inverter can be made to close It is disconnected, accordingly make first in the first phase inverter to pull up transistor to pull up transistor with second in the second phase inverter and open, institute It pulls up transistor with described first and exports the first output current, i.e., the electric current of the described first node is the first output current, described Second, which pulls up transistor, exports the second output current, i.e., the electric current of the described third node is the second output current；The SRAM is mono- Member further includes the reading unit being electrically connected with the bit line, and the reading unit is used to pass through the bit line and the transmission unit Read the first output current that described first pulls up transistor and the sum of the second output current that described second pulls up transistor； By the sum of the first output current for reading the reading unit and second output current divided by two, output current inspection is obtained Measured value, so as to obtain threshold voltage detected value by the output electric current measure value；Wherein, due to first phase inverter It is symmetrical structure with the second phase inverter, therefore can be considered that first output current and the second output current are equal, correspondingly, institute It is the threshold voltage detected value to state the first voltage threshold of pull up transistor corresponding to the first output current, second output The second voltage threshold of pull up transistor corresponding to electric current is the threshold voltage detected value；It is examined by comparing the threshold voltage Measured value and threshold voltage reference value, when the absolute value of difference between the threshold voltage detected value and threshold voltage reference value is more than When preset difference value, it can determine that described first pulls up transistor and pull up transistor failure with described second；Therefore, institute through the invention Failure sram cell can be detected in time by stating sram cell, so as to make corresponding corrective measure in time, to improve SRAM Device performance.

Description of the drawings

Fig. 1 is a kind of cumulative distribution function figure of SRAM read-writes minimum；

Fig. 2 is the circuit diagram of one embodiment of sram cell of the present invention；

Fig. 3 be sram cell of the present invention one embodiment of detection method in the first voltage threshold of pull up transistor and first defeated Go out the graph of relation of electric current；

Fig. 4 is that the detection system of sram cell of the present invention unifies the functional block diagram of embodiment；

Fig. 5 is the circuit diagram of one embodiment of SRAM device of the present invention.

Specific implementation mode

By background technology it is found that it is urgent to provide a kind of new SRAM cell structures and its test method, to detect in time Fail sram cell.Its reason is analyzed to be：

Currently, Negative Bias Temperature Instability (Negative Bias Temperature Instability, NBTI) at The main reason for declining for SRAM performances, under the influence of NBTI, PMOS accordingly will appear the problem of threshold voltage (Vt) increases. In conjunction with reference to figure 1, a kind of cumulative distribution function figure (CDF plot) of SRAM read-writes minimum, abscissa table are shown Show that operating voltage value, ordinate indicate the ratio under a certain operating voltage value.

Curve 201 and curve 301 indicate that the first SRAM device, curve 202 and curve 302 indicate the second SRAM device, institute It is normal SRAM device to state the first SRAM device, and the voltage threshold of pull up transistor of second SRAM device is more than described first The voltage threshold of pull up transistor of SRAM device, by curve 202 and curve 302 to characterize influences of the NBTI to SRAM device.

Specifically, curve 201 indicates the tired of the read functions minimum (Vccmin_Read) of the first SRAM device Cloth functional arrangement is integrated, curve 202 indicates the cumulative distribution function figure of the read functions minimum of the second SRAM device, bent Line 301 indicates the cumulative distribution function figure of the write-in functions minimum (Vccmin_Write) of the second SRAM device, bent Line 302 indicates the cumulative distribution function figure of the write-in functions minimum (Vccmin_Write) of the first SRAM device.

As shown in Figure 1, when the threshold voltage increase to pull up transistor, the read functions minimum of SRAM device is caused to work Voltage increases, write-in functions minimum reduces, that is to say, that NBIT causes the read functions minimum of SRAM device to work Voltage and write-in functions minimum shift, and decline so as to cause the performance of SRAM device.

Therefore, it is urgent to provide a kind of new SRAM cell structures and its test method, to detect threshold voltage hair in time The corresponding sram cell that pulls up transistor of raw offset, so as to make corresponding corrective measure according to actual conditions, in time Optimize SRAM device, reduces the extent of damage.

In order to solve the technical problem, the present invention provides a kind of sram cell, and the sram cell includes and bit line electricity The driving unit of connection, the driving unit be used for through the bit line and the transmission unit simultaneously to the second node and The fourth node loads low level, therefore when sram cell works, can make first time crystal pulling in the first phase inverter Pipe and the second phase inverter in the second pull-down transistor be turned off, accordingly make first in the first phase inverter pull up transistor and Second in second phase inverter, which pulls up transistor, opens, thus described first pull up transistor output the first output current, i.e., The electric current of the first node is the first output current, and described second pulls up transistor the second output current of output, i.e., described the The electric current of three nodes is the second output current；The sram cell further includes the reading unit being electrically connected with the bit line, described Reading unit be used for by the bit line and the transmission unit read the first output current that described first pulls up transistor with And described second the sum of the second output current that pulls up transistor；Pass through the first output current for reading the reading unit With the sum of the second output current divided by two, output electric current measure value is obtained, so as to be obtained by the output electric current measure value Obtain threshold voltage detected value；Wherein, since first phase inverter and the second phase inverter are symmetrical structure, it can be considered described First output current and the second output current are equal, correspondingly, first corresponding to first output current pulls up transistor Threshold voltage is the threshold voltage detected value, and the second voltage threshold of pull up transistor corresponding to second output current is The threshold voltage detected value；By comparing the threshold voltage detected value and threshold voltage reference value, when the threshold voltage When the absolute value of difference is more than preset difference value between detected value and threshold voltage reference value, it can determine that described first pulls up transistor It pulls up transistor failure with described second；Therefore, through the invention the sram cell can detect in time failure SRAM it is mono- Member, so as to make corresponding corrective measure in time, to improve SRAM device performance.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

With reference to figure 2, the circuit diagram of one embodiment of sram cell of the present invention is shown.

The sram cell includes：

Storage unit (does not indicate), and the storage unit includes that the first phase inverter (not indicating) and the second phase inverter (are not marked Show)；Wherein, first phase inverter pulls up transistor PUL and the first pull-down transistor PDL including first, first pull-up The drain electrode of transistor PUL and the source electrode of the first pull-down transistor PDL are electrically connected, and described first pulls up transistor PUL's The tie point of the source electrode of drain electrode and the first pull-down transistor PDL is first node A, and described first pulls up transistor PUL's The grid of grid and the first pull-down transistor PDL are electrically connected, and the described first grid and described for pulling up transistor PUL The tie point of the grid of one pull-down transistor PDL is second node C；Second phase inverter pulls up transistor PUR including second With the second pull-down transistor PDR, described second pull up transistor PUR drain electrode and the source electrode of the second pull-down transistor PDR Electrical connection, and the described second tie point for pulling up transistor the drain electrode of PUR and the source electrode of the second pull-down transistor PDR is the Three node B, described second pull up transistor PUR grid and the second pull-down transistor PDR grid electrical connection, and it is described Second tie point for pulling up transistor the grid of PUR and the grid of the second pull-down transistor PDR is fourth node D；Wherein, The second node C is electrically connected with the third node B, and the first node A is electrically connected with the fourth node D；

Transmission unit (does not indicate), including the first transmission gate transistor PGL and the second transmission gate transistor PGR, and described The drain electrode of one transmission gate transistor PGL is electrically connected with the first node A, the drain electrode of the second transmission gate transistor PGR with The third node B electrical connections；

Wordline WL, with the grid of the first transmission gate transistor PGL and the grid of the second transmission gate transistor PGR Pole is electrically connected；

Bit line (does not indicate), including the first bit line BL and the second bit line BLb, the first bit line BL is transmitted with described first The source electrode electrical connection of door transistor PGL, the second bit line BLb are electrically connected with the source electrode of the second transmission gate transistor PGR；

The driving unit 300 being electrically connected with the bit line, the driving unit 300 is for passing through the bit line and the biography Unit is sent to load low level to the second node C and fourth node D simultaneously；

The reading unit 200 being electrically connected with the bit line, the reading unit 200 is for passing through the bit line and the biography Unit is sent to read the described first the first output current I for pulling up transistor PUL_LAnd described second pull up transistor the of PUR Two output current I_RThe sum of.

Below with reference to attached drawing, the sram cell is specifically described.

In the present embodiment, the storage unit and transmission unit may make up a memory module, matrix arrangement it is multiple heavy Multiple memory module can be used for constituting SRAM device.

The storage unit is for storing data.It is described to deposit by taking the sram cell is 6T structures as an example in the present embodiment Storage unit includes the first phase inverter (not indicating) and the second phase inverter (not indicating), and first phase inverter and the second phase inverter For symmetrical structure.

First phase inverter pulls up transistor PUL and the first pull-down transistor PDL including first, crystal pulling on described first The drain electrode of body pipe PUL and the source electrode of the first pull-down transistor PDL are electrically connected, and the described first leakage for pulling up transistor PUL The tie point of the source electrode of pole and the first pull-down transistor PDL is first node A；Described first grid for pulling up transistor PUL The grid of pole and the first pull-down transistor PDL are electrically connected, and the described first grid and described first for pulling up transistor PUL The tie point of the grid of pull-down transistor PDL is second node C.

Second phase inverter pulls up transistor PUR and the second pull-down transistor PDR including second, crystal pulling on described second The drain electrode of body pipe PUR and the source electrode of the second pull-down transistor PDR are electrically connected, and the described second leakage for pulling up transistor PUR The tie point of the source electrode of pole and the second pull-down transistor PDR is third node B；Described second grid for pulling up transistor PUR The grid of pole and the second pull-down transistor PDR are electrically connected, and the described second grid and described second for pulling up transistor PUR The tie point of the grid of pull-down transistor PDR is fourth node D.

In the present embodiment, the sram cell further includes operating voltage power supply V_ddAnd common voltage power supply V_ss；Described One pull up transistor PUL and second pull up transistor PUR source electrode with the operating voltage power supply V_ddElectrical connection, described first The drain electrode of pull-down transistor PDL and the second pull-down transistor PDR with the common voltage power supply V_ssElectrical connection.The work electricity Voltage source V_ddVoltage value be more than the common voltage power supply V_ssVoltage value, the common voltage power supply V_ssIt can also be and connect Ground terminal (GND).

With continued reference to Fig. 2, the sram cell further includes：Transmission unit (does not indicate), and the transmission unit includes first Transmission gate transistor PGL and the second transmission gate transistor PGR, the drain electrode and described first of the first transmission gate transistor PGL Node A electrical connections, the drain electrode of the second transmission gate transistor PGR are electrically connected with the third node B；Wordline WL, the word Line WL is electrically connected with the grid of the grid of the first transmission gate transistor PGL and the second transmission gate transistor PGR；Position Line (does not indicate), and the bit line includes the first bit line BL and the second bit line BLb, the first bit line BL and first transmission gate The source electrode of transistor PGL is electrically connected, and the second bit line BLb is electrically connected with the source electrode of the second transmission gate transistor PGR.

Correspondingly, described first PUR that pull up transistor of PUL and described second that pull up transistor are symmetrical structure, described the One pull-down transistor PDL and the second pull-down transistor PDR is symmetrical structure, the first transmission gate transistor PGL and institute It is symmetrical structure to state the second transmission gate transistor PGR.

In the present embodiment, described first PUR that pull up transistor of PUL and second that pull up transistor are PMOS, under described first Pull transistor PDL, the second pull-down transistor PDR, the first transmission gate transistor PGL and the second transmission gate transistor PGR are NMOS.

In the present embodiment, the sram cell pulls up transistor for realizing first PUL or second that pulls up transistor of failure The detection of PUR.

It should be noted that due to described first pull up transistor PUL and described second pull up transistor PUR be symmetrical junction Structure, thus can be considered described first pull up transistor PUL with described second pull up transistor PUR structure it is identical with performance.Together Reason, can be considered that the first pull-down transistor PDL is identical with performance with the structure of the second pull-down transistor PDR, described the One transmission gate transistor PGL is identical with performance with the structure of the second transmission gate transistor PGR.

When being detected using the sram cell, the wordline WL makes first transmission gate for loading high potential Transistor PGL and the second transmission gate transistor PGR are opened, to make the first bit line BL pass through the first transmission gate crystal Pipe PGL is electrically connected with the first node A and fourth node D realizations, and the second bit line BLb is made to pass through second transmission gate Transistor PGR is electrically connected with the third node B and second node C realizations.

With continued reference to Fig. 2, the sram cell further includes：The driving unit 300 being electrically connected with the bit line (not indicating), The driving unit 300 is used for by the bit line and the transmission unit (not indicating) while to the second node C and institute State fourth node D load low levels.

By Such analysis it is found that when the first transmission gate transistor PGL and the second transmission gate transistor PGR are opened, The first bit line BL is electrically connected by the first transmission gate transistor PGL and first node A and fourth node D realizations It connects, the second bit line BLb realizes electricity by the second transmission gate transistor PGR and third node B and second node C Connection, therefore the driving unit 300 can load low level to the first bit line BL and the second bit line BLb simultaneously, to By the first bit line BL and the first transmission gate transistor PGL low level is loaded to the fourth node D, by described Second bit line BLb and the second transmission gate transistor PGR loads low level to the second node C.

It should be noted that since the second node C is electrically connected with the third node B, the first node A and institute Fourth node D electrical connections are stated, therefore the driving unit 300 is additionally operable to simultaneously to the first node A and the third node B Load low potential.

With continued reference to Fig. 2, the sram cell further includes：The reading unit 200 being electrically connected with the bit line (not indicating), The reading unit 200 is used to read described first by the bit line and the transmission unit (not indicating) and pull up transistor The first output current I of PUL_LAnd described second pull up transistor PUR the second output current I_RThe sum of.

When the grid to NMOS loads high potential, NMOS is opened, and when the grid to PMOS loads low potential, PMOS is opened It opens.In the present embodiment, the driving unit 300 to the second node C and fourth node D for loading low electricity simultaneously It is flat, therefore the driving unit 300 can be such that described first PUR that pull up transistor of PUL and second that pull up transistor open, and The first pull-down transistor PDL and the second pull-down transistor PDR is set to be turned off；Correspondingly, the electric current of the first node A is Described first the first output current I for pulling up transistor PUL_L, the electric current of the third node B is described second to pull up transistor The second output current I of PUR_R。

In addition, when the first transmission gate transistor PGL and the second transmission gate transistor PGR are opened, then it can make institute It states the first bit line BL to be electrically connected with the first node A by the first transmission gate transistor PGL, the second bit line BLb It is electrically connected with third node B realizations by the second transmission gate transistor PGR；And the reading unit 200 with it is described Bit line (not indicating) is electrically connected, therefore the reading unit 200 can pass through the first bit line BL and first transmission gate Transistor PGL reads the first output current I at the first node A_L, can also be by the second bit line BLb and described Second transmission gate transistor PGR reads the second output current I at the third node B_R.Correspondingly, the reading unit 200 For reading the first output current I_LWith the second output current I_RThe sum of.

It should be noted that the sram cell is applied not only to be detected, it is additionally operable to carry out normal operation.Therefore in order to The normal operation to sram cell is avoided to generate harmful effect, the sram cell further includes：It is single for being electrically connected the driving Member 300 and the first enabling unit (not indicating) of bit line (not indicating), for being electrically connected the reading unit 200 and bit line Two enabling units (not indicating) and the selecting unit being electrically connected simultaneously with first enabling unit and the second enabling unit 100。

Wherein, the storage unit in the sram cell and transmission unit may make up a memory module, matrix arrangement Multiple memory modules that repeat can be used for constituting SRAM device, i.e. SRAM device includes storage unit and the transmission of multiple repetitive structures Unit, therefore first enabling unit and selecting unit 100 are used to select memory module to be detected from the matrix, with Influence of the memory module for a long time by the driving unit 300 is avoided, the reading unit 200 can also be avoided while being obtained Take the first output current I corresponding to multiple memory modules_LWith the second output current I_RThe sum of；Second enabling unit and choosing Unit 100 is selected for reading the first output current I corresponding to memory module to be detected from the matrix_LWith the second output electricity Flow I_RThe sum of.

In the present embodiment, the selecting unit 100 is used to control the same of first enabling unit and the second enabling unit Shi Kaiqi is simultaneously turned off；First enabling unit for control the driving unit 300 simultaneously to the second node C and The fourth node D loads low level；To read described first defeated for controlling the reading unit 200 for second enabling unit Go out electric current I_LAnd the second output current I_RThe sum of.

SRAM device includes the repetitive structure memory module of multiple matrix arrangements, and the selecting unit 100 is led to for addressing The row address and column address of memory module to be detected in a matrix can be determined by crossing the selecting unit 100, so that it is determined that be checked Survey specific address of the memory module in the matrix.

In the present embodiment, first enabling unit includes the first transistor T1, and second enabling unit includes second Transistor T2, and the first transistor T1 is identical with the transistor types of second transistor T2.Therefore, the selecting unit 100 for opening or simultaneously turning off while controlling the first transistor T1 and second transistor T2.

Therefore, the memory module in the first transistor T1 and second transistor T2 and matrix corresponds, i.e., described The quantity of the first transistor T1 is equal with the quantity of the memory module, the quantity of the second transistor T2 and the storage mould The quantity of block is equal.

It should be noted that in the present embodiment, the selecting unit 100 is applied not only to determine memory module to be detected in institute The specific address in matrix is stated, is additionally operable to open the crystalline substances of the first transistor T1 of memory module corresponding to the specific address and second Body pipe T2 turns off the first transistor T1 and second transistor T2 corresponding to remaining memory module, to make the driving unit 300 and reading unit 200 act on memory module to be detected.

In the present embodiment, the first transistor T1 and second transistor T2 are PMOS.In other embodiments, described The first transistor and second transistor are NMOS.Wherein, when the selecting unit 100 is used to provide high potential, then described The first transistor T1 and second transistor T2 is NMOS, when the selecting unit 100 is for when providing low potential, then described the One transistor T1 and second transistor T2 is PMOS.

Specifically, the first transistor T1 includes first grid, the first source electrode and the first drain electrode, the second transistor T2 includes second grid, the second source electrode and the second drain electrode；The first grid and second grid are electric with the selecting unit 100 Connection；First source electrode is electrically connected with the driving unit 300；First drain electrode and the first bit line BL and second Line BLb electrical connections；Second source electrode is electrically connected with the first bit line BL and the second bit line BLb；Second drain electrode and institute State the electrical connection of reading unit 200.

Therefore, it when the selecting unit 100 determines specific address of the memory module to be detected in the matrix, and opens After the first transistor T1 and second transistor T2 of corresponding memory module, the driving unit 300 passes through the first crystal Pipe T1, the first bit line BL and the first transmission gate transistor PGL load low level to the fourth node D, to open described second Pull up transistor PUR；The driving unit 300 is also brilliant by the first transistor T1, the second bit line BLb and the second transmission gate Body pipe PGR loads low level to the second node C, is pulled up transistor PUL with opening described first, makes described the to reach One pull up transistor PUL export the first output current I_L, make described second pull up transistor PUR export the second output current I_R's Purpose, and the first output current I is read by the reading unit 200_LWith the second output current I_RThe sum of.

With continued reference to Fig. 2, correspondingly, the present invention also provides a kind of detection methods of sram cell, including：Aforementioned reality is provided Apply the sram cell described in example；The threshold voltage reference value to pull up transistor is provided；There is provided the threshold voltage that pulls up transistor with Relational expression between output current；Open the first transmission gate transistor PGL and the second transmission gate transistor PGR；The drive Moving cell 300 loads low level by the first bit line BL and the first transmission gate transistor PGL to the fourth node D, makes Described second pull up transistor PUR open, the second pull-down transistor PDR close, described second pull up transistor PUR output Second output current I_R；The driving unit 300 also passes through the second bit line BLb and the second transmission gate transistor PGR simultaneously Low level is loaded to the second node C, making described first to pull up transistor, PUL is opened, the first pull-down transistor PDL is closed Close, described first pull up transistor PUL export the first output current I_L；The reading unit 200 passes through first transmission gate Transistor PGL, the first bit line BL, the second transmission gate transistor PGR and the second bit line BLb read the first output current I_LWith Second output current I_RThe sum of；By the first output current I_LWith the second output current I_RThe sum of divided by two, obtain output current Detected value；According to the relational expression and the output electric current measure value, obtains described first and pull up transistor PUL and described second Pull up transistor the threshold voltage detected value of PUR；Compare the threshold voltage detected value and threshold voltage reference value, when the threshold When the absolute value of difference is more than preset difference value between threshold voltage detected value and threshold voltage reference value, crystal pulling in judgement described first Body pipe PUL and described second pull up transistor PUR failure.

Detection method provided in an embodiment of the present invention is described in detail below with reference to attached drawing.

Storage unit and transmission unit in the sram cell may make up a memory module, the weight of multiple matrix arrangements Multiple memory module can be used for constituting SRAM device, i.e. SRAM device includes the storage unit and transmission unit of multiple repetitive structures, The detection method is for detecting memory module to be detected in the SRAM device.

Specifically, accordingly retouching in the embodiment of aforementioned sram cell of the present invention is can refer to the description of the sram cell It states, details are not described herein.

In the present embodiment, the detection method pulls up transistor PUL's for detecting described in the sram cell first First output current I_LAnd described second pull up transistor PUR the second output current I_RThe sum of, to defeated by described first Go out electric current I_LWith the second output current I_RThe sum of divided by two, pulled up transistor with obtaining described first PUL and second that pulls up transistor The output electric current measure value of PUR, and according to the relational expression and the output electric current measure value, obtain crystal pulling on described first Pipe PUL and described second pulls up transistor the threshold voltage detected value of PUR, so judge described first pull up transistor PUL or Whether described second PUR that pulls up transistor fails.

It should be noted that due to described first pull up transistor PUL and described second pull up transistor PUR be symmetrical junction Structure, thus can be considered described first pull up transistor PUL with described second pull up transistor PUR structure it is identical with performance；Phase Answer, can be considered described first pull up transistor the output current value that PUL and described second pulls up transistor PUR be output electricity Flow detected value.Therefore, when described first PUL and described second that pulls up transistor pulls up transistor any transistor nonfunctional in PUR When, then judge corresponding sram cell failure.

Specifically, the step of detection method includes：The threshold voltage reference value to pull up transistor is provided, that is, institute is provided First PUL and second that pulls up transistor is stated to pull up transistor the threshold voltage reference value of PUR；Subsequently obtain crystal pulling on described first Body pipe PUL and described second pull up transistor PUR threshold voltage detected value after, by the threshold voltage detected value and the threshold Threshold voltage reference value is compared.Wherein, the threshold voltage reference value to pull up transistor can according to actual process demand and It is fixed.

In the present embodiment, described first pull up transistor PUL and second pull up transistor PUR source electrode and operating voltage Power supply V_ddElectrical connection, the drain electrode of the first pull-down transistor PDL and the second pull-down transistor PDR with common voltage power supply V_ssElectrical connection.The operating voltage power supply V_ddVoltage value be more than the common voltage power supply V_ssVoltage value, the common electrical Voltage source V_ssIt can also be ground terminal (GND).

In the present embodiment, make described first pull up transistor PUL export the first output current I_L, make crystal pulling on described second Body pipe PUR exports the second output current I_RThe step of include：High potential is applied to the wordline WL, keeps first transmission gate brilliant Body pipe PGL and the second transmission gate transistor PGR are opened, to make the first bit line BL pass through the first transmission gate transistor PGL is electrically connected with the first node A and fourth node D realizations, so that the second bit line BLb is passed through second transmission gate brilliant Body pipe PGR is electrically connected with the third node B and second node C realizations；The driving unit 300 (is not marked by the bit line Show) and the transmission unit (not indicating) while loading low level to the second node C and the fourth node D.

Specifically, the driving unit 300 by the first bit line BL and the first transmission gate transistor PGL to institute State fourth node D load low level, while by the second bit line BLb and the second transmission gate transistor PGR to described Second node C loads low level.

Wherein, the company for pulling up transistor the grid of PUL and the grid of the first pull-down transistor PDL due to described first Contact is second node C, the described second company for pulling up transistor the grid of PUR and the grid of the second pull-down transistor PDR Contact is fourth node D, and NMOS is opened when the grid to NMOS loads high potential, when the grid to PMOS loads low potential When PMOS open.Therefore, the driving unit 300 makes described first PUR that pull up transistor of PUL and second that pull up transistor open It opens, while the first pull-down transistor PDL and the second pull-down transistor PDR being made to be turned off.

In the present embodiment, the driving unit 300 is low level to the fourth node D and second node C loads In step, the driving unit 300 makes the first bit line BL and the second bit line BLb ground connection (GND).

The first output current of PUL correspondingly, the output current of first phase inverter pulls up transistor for described first I_L, the output current of second phase inverter is the described second the second output current I for pulling up transistor PUR_R；And due to described Second node C is electrically connected with the third node B, and the first node A is electrically connected with the fourth node D, therefore described The three node B and first node A are also low potential, therefore described first PUL that pulls up transistor is defeated to the first node A Go out electric current, described second pulls up transistor PUR to the third node B output currents, that is to say, that the first node A's Electric current is the described first the first output current I for pulling up transistor PUL_L, the electric current of the third node B is second pull-up The second output current I of transistor PUR_R。

Since the first transmission gate transistor PGL and the second transmission gate transistor PGR is in open state, described the One bit line BL is electrically connected by the first transmission gate transistor PGL with first node A realizations, the second bit line BLb It is electrically connected with third node B realizations by the second transmission gate transistor PGR；And the reading unit 200 with it is described Bit line (not indicating) is electrically connected, therefore the reading unit 200 is read by the first bit line BL at the first node A The first output current I_L, the second output current I at the third node B is also read by the second bit line BLb_R.Tool Body, the electric current that the reading unit 200 is read is the first output current I_LWith the second output current I_RThe sum of.

It should be noted that the sram cell to be detected is additionally operable to carry out normal operation.Therefore in order to avoid right The normal operation of sram cell generates harmful effect, and the sram cell further includes：For being electrically connected 300 He of the driving unit The first enabling unit (not indicating) of bit line (not indicating) is enabled for being electrically connected the second of the reading unit 200 and bit line Unit (not indicating) and the selecting unit 100 being electrically connected simultaneously with first enabling unit and the second enabling unit.

In the present embodiment, first enabling unit includes the first transistor T1, and second enabling unit includes second Transistor T2, and the first transistor T1 is identical with the transistor types of second transistor T2.

To the selecting unit 100, the first enabling unit, the second enabling unit, the first transistor T1 and second transistor The detailed description of T2 can refer to the corresponding description in the embodiment of aforementioned sram cell of the present invention, and details are not described herein.

In the present embodiment, after the selecting unit 100 determines specific address of the memory module to be detected in the matrix, The selecting unit 100 controls the first transistor T1 and second transistor T2 of memory module corresponding to the specific address simultaneously It opens, and closes remaining the first transistor T1 and second transistor T2.

Therefore, the driving unit 300 by the first bit line BL and the first transmission gate transistor PGL to the described 4th Node D is loaded in low level step, between the first transistor T1, the first bit line BL and the first transmission gate transistor PGL The first circuit loop is formed, the driving unit 300 loads low electricity by first circuit loop to the fourth node D It is flat；And source electrode and the operating voltage power supply V for due to described second pulling up transistor PUR_ddElectrical connection, therefore crystal pulling on described second Body pipe PUR is in open state；Further, since the fourth node D is low potential, therefore the second pull-down transistor PDR is in Off state.

Similarly, the driving unit 300 by the second bit line BLb and the second transmission gate transistor PGR to described Two node C are loaded in low level steps, the first transistor T1, the second bit line BLb and the second transmission gate transistor PGR it Between form second circuit circuit, the driving unit 300 loads low electricity by the second circuit circuit to the second node C It is flat；And source electrode and the operating voltage power supply V for due to described first pulling up transistor PUL_ddElectrical connection, therefore crystal pulling on described first Body pipe PUL is in open state；Further, since the second node C is low potential, therefore the first pull-down transistor PDL is in Off state.

Since the second node C is electrically connected with the third node B, the first node A and fourth node D electricity Connection, the first node A and third node B also mutually should be low potential, the described first the first output electricity for pulling up transistor PUL Flow I_LIt flow at the first node A, the described second the second output current I for pulling up transistor PUR_RIt flow to the third node B Place；Therefore, the reading unit 200 passes through the first transmission gate transistor PGL, the first bit line BL, the second transmission gate crystal Pipe PGR and the second bit line BLb read the first output current I_LWith the second output current I_RThe sum of the step of in, described first It pulls up transistor and forms tertiary circuit time between PUL, the first transmission gate transistor PGL, the first bit line BL and second transistor T2 Road, described second pulls up transistor shape between PUR, the second transmission gate transistor PGR, the second bit line BLb and second transistor T2 At the 4th circuit loop, the reading unit 200 passes through described in the tertiary circuit circuit and the 4th circuit loop reading First output current I_LWith the second output current I_RThe sum of.

It should be noted that the reading unit 200 reads the first output current I_LWith the second output current I_R The sum of after, the detection method further includes：By the first output current I_LWith the second output current I_RThe sum of divided by two, obtain Output electric current measure value.

Due to described first pull up transistor PUL and described second pull up transistor PUR be symmetrical structure, can be considered Described first pull up transistor PUL with described second pull up transistor PUR structure it is identical with performance, correspondingly, can be considered institute It is the output electric current measure value to state first output current value that PUL and described second pulls up transistor PUR that pulls up transistor.

It should also be noted that, since the first node A and third node B is to be grounded, crystal pulling on described first The PUR that pull up transistor of body pipe PUL and second are in saturation region (Saturation Region).At this point, the threshold to pull up transistor It is transistor saturation current (I to have relational expression, the relational expression between threshold voltage and output current_dsat) formula.

Pull up transistor the threshold voltage V of PUL with described first_{Th, PUL}For, the described first threshold for pulling up transistor PUL Threshold voltage V_{Th, PUL}With the first output current I_LBetween there is the first relational expression, and according to transistor saturation current (I_dsat) public Formula, first relational expression are：I_L=1/2*K_p*(V_dd-V_B-V_{Th, PUL})^2*(1+λ_p(V_dd-V_A)).Wherein, K_p=μ C_oxW/L, λ_pFor channel-length modulation (channel length modulation), V_BFor the current potential of the third node B, V_AFor institute State the current potential of first node A, V_ddFor constant.And due to the first bit line BL and the second bit line BLb ground connection, V_BAnd V_AIt can It is considered as zero, correspondingly, first relational expression is：I_L=1/2*K_p*(V_dd-V_{Th, PUL})^2*(1+λ_p*V_dd)。

In conjunction with reference to figure 3, pulls up transistor for PUL by described first, show that described first pulls up transistor PUL's Threshold voltage V_{Th, PUL}With the first output current I_LGraph of relation.Wherein, abscissa indicates that described first pulls up transistor The threshold voltage V of PUL_{Th, PUL}, ordinate expression threshold voltage V_{Th, PUL}The first corresponding output current I_L.By relationship song Line chart is it is found that the described first the first output current I for pulling up transistor PUL_LWith described first pull up transistor PUL threshold value electricity Press V_{Th, PUL}It is related.

Similarly, the described second threshold voltage V for pulling up transistor PUR_{Th, PUR}With the second output current I_RBetween have Second relational expression, second relational expression are I_R=1/2*K_p*(V_dd-V_{Th, PUR})^2*(1+λ_p*V_dd)。

That is, the relational expression between the threshold voltage to pull up transistor and output current is：I_PU=1/2*K_p* (V_dd-V_{Th, PU})^2*(1+λ_p*V_dd)。

Further, since the first node A and third node B is low potential, therefore the first transmission gate transistor PGL It is in linear zone (Linear Region) with the second transmission gate transistor PGR.According to linear zone current formula, described in acquisition The output current I of first transmission gate transistor PGL_PGLWith the threshold voltage V of the first transmission gate transistor PGL_{Th, PGL}Between pass It is that formula is：I_PGL=K_p*[(V_GS-V_{Th, PGL})*V_DS-1/2*V_DS^2]=K_p*[(V_dd-V_{Th, PGL})V_A]；Therefore dI/dV_th,PGL=- K_p*V_A。

Since the driving unit 300 makes the first bit line BL be grounded, V_AZero is can be considered, correspondingly, dI/ dV_th,PGL≈ 0, i.e., the described first transmission gate transistor PGL threshold voltages V_{Th, PGL}Variation will not lead to first transmission gate The output current I of transistor PGL_PGLIt changes.Similarly, the second transmission gate transistor PGR threshold voltages V_{Th, PGR}Change The output current I of the second transmission gate transistor PGR will not be led to by changing_PGRIt changes.

So the first transmission gate transistor PGL and the second transmission gate transistor PGR will not be to the reading units 200 electric currents that get generate interference, i.e., the electric current that the reading unit 200 is got only is pulled up transistor by described first PUL and second pulls up transistor the influence of PUR, i.e., the described output electric current measure value is only pulled up transistor PUL by described first Pull up transistor the influence of PUR with second.

Correspondingly, in the present embodiment, described first can be obtained according to the relational expression and the output electric current measure value The PUL and described second that pulls up transistor pulls up transistor the threshold voltage detected value of PUR.

Specifically, the output electric current measure value is substituting in first relational expression, to obtain first pull-up The first threshold voltage detected value V of transistor PUL_{Th, PUL_Test}；The output electric current measure value is substituting to second relationship In formula, to obtain the described second second threshold voltage detected value V for pulling up transistor PUR_{Th, PUR_Test}。

In the present embodiment, since the output electric current measure value is the first output current I_LWith the second output electricity Flow I_RThe sum of half, i.e. output electric current measure value=(the first output current I_L+ the second output current I_R)/2, thus it is described V_{Th, PUL_Test}=V_{Th, PUR_Test}。

After obtaining the threshold voltage detected value, the threshold voltage detected value and threshold voltage reference value work as institute When stating the absolute value of difference between threshold voltage detected value and threshold voltage reference value more than preset difference value, in judgement described first Pull transistor PUL and second pull up transistor PUR failure.

It pulls up transistor for PUL by described first, obtains the first threshold voltage detected value V_{Th, PUL_Test}Afterwards, compare The first threshold voltage detected value V_{Th, PUL_Test}With threshold voltage reference value, when the first threshold voltage detected value V_{Th, PUL_Test}When the absolute value of difference is more than preset difference value between threshold voltage reference value, judgement described first pulls up transistor PUL fails.

Similarly, the second threshold voltage detected value V is obtained_{Th, PUR_Test}Afterwards, the second threshold voltage detected value V_{Th, PUR_Test}With threshold voltage reference value, as the second threshold voltage detected value V_{Th, PUR_Test}With threshold voltage reference value it Between difference absolute value be more than preset difference value when, judgement described second pull up transistor PUR failure.

In the present embodiment, the preset difference value is that 75mV is 125mV.

Correspondingly, the present invention also provides a kind of detecting systems of sram cell.With reference to figure 4, show that SRAM of the present invention is mono- The detection system of member unifies the functional block diagram of embodiment.

The detecting system of the sram cell includes：Sram cell 510 above-mentioned；It is connected with the sram cell 510 Computing unit 520 is used for the first output current I of the sram cell 510_LWith the second output current I_RThe sum of divided by two, obtain Output electric current measure value obtains described the and according to the relational expression between the threshold voltage and output current to pull up transistor One PUL and described second that pulls up transistor pulls up transistor the threshold voltage detected value of PUR；It is connected with the computing unit 520 Judging unit 530, for providing the threshold voltage reference value to pull up transistor, and the threshold voltage detected value and threshold Threshold voltage reference value, when the absolute value of difference between the threshold voltage detected value and threshold voltage reference value is more than preset difference value When, judgement described first pull up transistor PUL and described second pull up transistor PUR failure.

It can refer to accordingly retouching in the embodiment of aforementioned sram cell of the present invention to the detailed description of the sram cell 510 It states, details are not described herein.

In the present embodiment, the computing unit 520 is used for the first output current I_LWith the second output current I_RThe sum of Divided by two, to obtain output electric current measure value.Since described first PUL and described second that pulls up transistor pulls up transistor PUR For symmetrical structure, therefore it can be considered that described first PUL and described second that pulls up transistor pulls up transistor the structure and performance of PUR It is identical, correspondingly, can be considered described first pull up transistor PUL and described second pull up transistor PUR output current value it is equal For the output electric current measure value.

It should be noted that since the first node A and third node B is to be grounded, crystal pulling on described first The PUR that pull up transistor of pipe PUL and second are in saturation region (Saturation Region).At this point, the threshold value to pull up transistor It is transistor saturation current (I to have relational expression, the relational expression between voltage and output current_dsat) formula.

Specifically, the described first threshold voltage V for pulling up transistor PUL_{Th, PUL}With the first output current I_LBetween have There are the first relational expression, first relational expression to be：I_L=1/2*K_p*(V_dd-V_{Th, PUL})^2*(1+λ_p*V_dd)；Similarly, described second Pull up transistor the threshold voltage V of PUR_{Th, PUR}With the second output current I_RBetween have the second relational expression, it is described second close Be formula be I_R=1/2*K_p*(V_dd-V_{Th, PUR})^2*(1+λ_p*V_dd)。

Therefore, the computing unit 520 is additionally operable to the output electric current measure value being substituting in first relational expression, To obtain the described first first threshold voltage detected value V for pulling up transistor PUL_{Th, PUL_Test}；By the output electric current measure value It is substituting in second relational expression, to obtain the described second second threshold voltage detected value for pulling up transistor PUR V_{Th, PUR_Test}。

It, can to obtaining the detailed description of the output electric current measure value and the threshold voltage detected value method to pull up transistor With reference to the detection method of aforementioned sram cell of the present invention embodiment in corresponding description, details are not described herein.

After obtaining the threshold voltage detected value, pass through the 530 threshold voltage detected value of judging unit and threshold value Voltage reference value, when the absolute value of difference between the threshold voltage detected value and threshold voltage reference value is more than preset difference value When, judgement described first pull up transistor PUL and second pull up transistor PUR failure.In the present embodiment, the preset difference value is 75mV is 125mV.

In the present embodiment, pull up transistor the tool whether PUR fail to the PUL and second that pulls up transistor of judgement described first Body describes, and can refer to the corresponding description in the embodiment of the detection method of aforementioned sram cell of the present invention, details are not described herein.

With reference to figure 5, the circuit diagram of one embodiment of SRAM device of the present invention is shown.Correspondingly, the present invention also provides one kind SRAM device.

In conjunction with reference to figure 2, the SRAM device includes：Multiple memory modules 600 arranged in arrays, the memory module Including storage unit and transmission unit；The storage unit includes the first phase inverter and the second phase inverter；First phase inverter It pulls up transistor PUL and the first pull-down transistor PDL including first, the described first drain electrode and described for pulling up transistor PUL The source electrode of one pull-down transistor PDL is electrically connected, and described first pull up transistor PUL drain electrode and first pull-down transistor The tie point of the source electrode of PDL is first node A, described first pull up transistor PUL grid and first pull-down transistor The grid of PDL is electrically connected, and described first pulls up transistor the grid of PUL and the grid of the first pull-down transistor PDL Tie point is second node C；Second phase inverter pulls up transistor PUR and the second pull-down transistor PDR including second, described Second pulls up transistor the drain electrode of PUR and the source electrode of the second pull-down transistor PDR is electrically connected, and crystal pulling on described second The tie point of the drain electrode of pipe PUR and the source electrode of the second pull-down transistor PDR is third node B, crystal pulling on described second The grid of the grid of pipe PUR and the second pull-down transistor PDR are electrically connected, and the described second grid for pulling up transistor PUR Tie point with the grid of the second pull-down transistor PDR is fourth node D；The second node C and third node B Electrical connection, the first node A are electrically connected with the fourth node D；The transmission unit includes the first transmission gate transistor PGL With the second transmission gate transistor PGR, the drain electrode of the first transmission gate transistor PGL is electrically connected with the first node A, described The drain electrode of second transmission gate transistor is electrically connected with the third node B；More wordline WL, each wordline WL and the matrix In with a line the first transmission gate transistor PGL and the second transmission gate transistor PGR grid correspond to electrical connection；More positions Line (does not indicate), including more the first bit line BL being arranged alternately and the second bit line BLb, each first bit line BL and the square The source electrode of the first transmission gate transistor PGL of same row corresponds to electrical connection, each second bit line BLb and the square in battle array The source electrode of the second transmission gate transistor PGR of same row corresponds to electrical connection in battle array；The drive being electrically connected with the more bit lines Moving cell 300, the driving unit 300 be used for through the bit line and the transmission unit simultaneously to the second node C and The fourth node D loads low level；The reading unit 200 being electrically connected with the more bit lines, the reading unit 200 are used for The described first the first output current I for pulling up transistor PUL is read by the bit line and the transmission unit_LAnd described Two the second output current I for pulling up transistor PUR_RThe sum of.

In the present embodiment, the SRAM device include it is arranged in arrays it is multiple repeat memory modules 600, correspondingly, institute It includes storage unit and transmission unit to state multiple memory modules 600 to have identical structure, each memory module 600.

The storage unit is for storing data.It is that 6T SRAM structures are with the memory module 600 in the present embodiment Example, the storage unit include the first phase inverter (not indicating) and the second phase inverter (not indicating), and first phase inverter with Second phase inverter is symmetrical structure.Wherein, first phase inverter pulls up transistor PUL and the first pull-down transistor including first PDL；Second phase inverter pulls up transistor PUR and the second pull-down transistor PDR including second.

In the present embodiment, the transmission unit includes the first transmission gate transistor PGL and the second transmission gate transistor PGR.

Specifically, described first PUR that pull up transistor of PUL and described second that pull up transistor are symmetrical structure, described the One pull-down transistor PDL and the second pull-down transistor PDR is symmetrical structure, the first transmission gate transistor PGL and institute It is symmetrical structure to state the second transmission gate transistor PGR.

It should be noted that the sram cell further includes operating voltage power supply V_ddAnd common voltage power supply V_ss；It is described First pull up transistor PUL and second pull up transistor PUR source electrode with the operating voltage power supply V_ddElectrical connection, described the The drain electrode of one pull-down transistor PDL and the second pull-down transistor PDR with the common voltage power supply V_ssElectrical connection.The work Voltage source V_ddVoltage value be more than the common voltage power supply V_ssVoltage value, the common voltage power supply V_ssIt can also be Ground terminal (GND).

In the embodiment that can refer to aforementioned sram cell of the present invention to the detailed description of the storage unit and transmission unit Corresponding description, details are not described herein.

In the present embodiment, each wordline WL in the matrix with the first transmission gate transistor PGL of a line and The grid of second transmission gate transistor PGR corresponds to electrical connection；Each first bit line BL in the matrix same row it is described The source electrode of first transmission gate transistor PGL corresponds to electrical connection, each second bit line BLb in the matrix same row it is described The source electrode of second transmission gate transistor PGR corresponds to electrical connection.

That is, multiple first transmission gate transistor PGL positioned at same row in the matrix share one first Line BL, the multiple second transmission gate transistor PGR for being located at same row in the matrix share a second bit line BLb, are located at institute It states multiple first transmission gate transistor PGL and the second transmission gate transistor PGR in matrix with a line and shares a wordline WL.

Correspondingly, the driving unit 300 is electrically connected with the more bit lines, the reading unit 200 with described more Bit line is electrically connected.I.e. the multiple memory module 600 shares a driving unit 300 and reading unit 200.

The driving unit 300 is used to save by the bit line and the transmission unit (not indicating) while to described second The point C and fourth node D loads low level, and the reading unit 200 is used to pass through the bit line and the transmission unit (not Mark) read the described first the first output current I for pulling up transistor PUL_LAnd described second pull up transistor the second of PUR Output current I_RThe sum of.

The aforementioned present invention can refer to the detailed description of the wordline WL, bit line, driving unit 300 and reading unit 200 Corresponding description in the embodiment of sram cell, details are not described herein.

It should be noted that the memory module 600 in the SRAM device cannot be only used for being detected, it is additionally operable to carry out Normal operation.In order to avoid generating harmful effect to the normal operation of SRAM device, the SRAM device further includes：For being electrically connected Connect multiple first enabling units (not indicating) of the driving unit 300 and Duo Gen bit lines, the multiple first enabling unit with The multiple memory module 600 is corresponded and is electrically connected with the bit line of corresponding memory module 600；For being electrically connected the reading Multiple second enabling units (not indicating) of unit 200 and multidigit line, the multiple second enabling unit are taken to be deposited with the multiple Storage module 600 is corresponded and is electrically connected with the bit line of corresponding memory module 600；Simultaneously with the multiple first enabling unit With the selecting unit 100 of multiple second enabling units electrical connection.

Correspondingly, the quantity of first enabling unit is equal with the quantity of the memory module 600, described second is enabled The quantity of unit is equal with the quantity of the memory module 600.

In the present embodiment, the SRAM device includes the memory module 600 of multiple repetitive structures of matrix arrangement, the choosing Unit 100 is selected for addressing, can determine memory module 600 to be detected in the matrix by the selecting unit 100 Row address and column address, so that it is determined that specific address of the memory module to be detected 600 in the matrix.

The selecting unit 100 is additionally operable to control first enabling unit corresponding to same memory module 600 simultaneously It opens or simultaneously turns off with while the second enabling unit.Specifically, it is determined that memory module 600 to be detected is in the matrix After specific address, the selecting unit 100 is used to open the first enabling unit and second corresponding to memory module 600 to be detected Enabling unit turns off the first enabling unit and the second enabling unit corresponding to remaining memory module 600.

First enabling unit is for controlling the driving unit 300 simultaneously to corresponding to memory module 600 to be detected The second node C and fourth node D load low level；Second enabling unit is for controlling the reading unit 200 Read the corresponding to memory module 600 to be detected described first the first output current I for pulling up transistor PUL_LAnd on second The second output current I of pull transistor PUR_RThe sum of.

Therefore, by first enabling unit and selecting unit 100, can to avoid the memory module 600 for a long time by To the influence of the driving unit 300, the reading unit 200 can also be avoided and meanwhile obtain multiple memory modules 600 pair The the first output current I answered_LWith the second output current I_RThe sum of；Second enabling unit and selecting unit 100 are waited for for reading Detect the first output current I corresponding to memory module 600_LWith the second output current I_RThe sum of.

In the present embodiment, first enabling unit includes the first transistor T1, and second enabling unit includes second Transistor T2, and the first transistor T1 is identical with the transistor types of second transistor T2.Therefore, the selecting unit 100 open while being additionally operable to control the first transistor T1 and the second transistor T2 corresponding to same memory module 600 Or it simultaneously turns off.

Correspondingly, the memory module 600 1 in the first transistor T1 and second transistor T2 and the matrix is a pair of It answers, i.e., the quantity of the described the first transistor T1 is equal with the quantity of the memory module 600, the quantity of the second transistor T2 It is equal with the quantity of the memory module 600.

Specifically, after the selecting unit 100 determines specific address of the memory module 600 to be detected in the matrix, It is additionally operable to open the first transistor T1 of memory module 600 corresponding to the specific address and second transistor T2, shutdown is remaining The first transistor T1 corresponding to memory module 600 and second transistor T2.

Specifically, the first transistor T1 includes first grid, the first source electrode and the first drain electrode, the second transistor T2 includes second grid, the second source electrode and the second drain electrode；The first grid and second grid are electric with the selecting unit 100 Connection；First source electrode is electrically connected with the driving unit 300；The institute of first drain electrode and corresponding memory module 600 State the first bit line BL and the second bit line BLb electrical connections；First bit line of second source electrode and corresponding memory module 600 BL and the second bit line BLb electrical connections；Second drain electrode is electrically connected with the reading unit 200.

In the present embodiment, when the selecting unit 100 determines memory module 600 to be detected in the matrix specifically Behind location, the first transistor T1 and second transistor T2, the driving unit 300 that open corresponding memory module 600 can pass through The first transistor T1 of memory module 600 to be detected, the first bit line BL and the first transmission gate transistor PGL are to the fourth node D loads low level, is pulled up transistor PUL with opening described first；The driving unit 300 can also pass through the storage to be detected The first transistor T1 of module 600, the second bit line BLb and the second transmission gate transistor PGR load low electricity to the second node C It is flat, it is pulled up transistor PUR with opening described second, makes described first to pull up transistor PUL outputs the first output electricity to reach Flow I_L, make described second pull up transistor PUR export the second output current I_RPurpose, and pass through the reading unit 200 read The first output current I_LWith the second output current I_RThe sum of.

Therefore, the SRAM device through this embodiment, may be implemented to each memory module 600 in the SRAM device Detection.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of sram cell, for being detected, which is characterized in that including：

Storage unit, the storage unit include the first phase inverter and the second phase inverter；Wherein, first phase inverter includes the One pulls up transistor and the first pull-down transistor, the source of the described first drain electrode and first pull-down transistor to pull up transistor Pole is electrically connected, and the tie point of the source electrode of the described first drain electrode and first pull-down transistor to pull up transistor is first segment The grid of point, the described first grid to pull up transistor and first pull-down transistor is electrically connected, and crystal pulling on described first The tie point of the grid of the grid of body pipe and first pull-down transistor is second node；Second phase inverter includes second It pulls up transistor and the second pull-down transistor, the source electrode of the described second drain electrode and second pull-down transistor to pull up transistor Electrical connection, and the tie point of the source electrode of the described second drain electrode and second pull-down transistor to pull up transistor is third section The grid of point, the described second grid to pull up transistor and second pull-down transistor is electrically connected, and crystal pulling on described second The tie point of the grid of the grid of body pipe and second pull-down transistor is fourth node；Wherein, the second node and institute The electrical connection of third node is stated, the first node is electrically connected with the fourth node；

Transmission unit, including the first transmission gate transistor and the second transmission gate transistor, the leakage of the first transmission gate transistor Pole is electrically connected with the first node, and the drain electrode of the second transmission gate transistor is electrically connected with the third node；

Wordline is electrically connected with the grid of the grid of the first transmission gate transistor and the second transmission gate transistor；

Bit line, including the first bit line and the second bit line, the source electrode of first bit line and the first transmission gate transistor are electrically connected It connects, second bit line is electrically connected with the source electrode of the second transmission gate transistor；

The driving unit being electrically connected with the bit line, the driving unit are used to pass through the bit line and the transmission unit simultaneously Low level is loaded to the second node and the fourth node；

The reading unit being electrically connected with the bit line, the reading unit are used to read by the bit line and the transmission unit Described first the first output current to pull up transistor and described second the sum of the second output current for pulling up transistor.

2. sram cell as described in claim 1, which is characterized in that described first pulls up transistor pulls up transistor with second For PMOS, first pull-down transistor, the second pull-down transistor, the first transmission gate transistor and the second transmission gate transistor are NMOS。

3. sram cell as described in claim 1, which is characterized in that the sram cell further include operating voltage power supply and Common voltage power supply；

Described first pull up transistor the source electrode to pull up transistor with second with operating voltage power electric connection, under described first The drain electrode of pull transistor and the second pull-down transistor with common voltage power electric connection.

4. sram cell as described in claim 1, which is characterized in that the sram cell further includes：It is described for being electrically connected First enabling unit of driving unit and bit line, the second enabling unit for being electrically connected the reading unit and bit line and The selecting unit being electrically connected simultaneously with first enabling unit and the second enabling unit；

The selecting unit is for controlling first enabling unit and the second enabling unit while opening or simultaneously turning off；

First enabling unit is loaded to the second node and the fourth node simultaneously for controlling the driving unit Low level；

Second enabling unit reads the described first the first output current to pull up transistor for controlling the reading unit And described second the sum of the second output current that pulls up transistor.

5. sram cell as claimed in claim 4, which is characterized in that first enabling unit includes the first transistor, institute It includes second transistor to state the second enabling unit, and the first transistor is identical with the transistor types of second transistor；

The selecting unit is for controlling the first transistor and second transistor while opening or simultaneously turning off.

6. sram cell as claimed in claim 5, which is characterized in that the first transistor includes first grid, the first source Pole and the first drain electrode, the second transistor include second grid, the second source electrode and the second drain electrode；

The first grid and second grid are electrically connected with the selecting unit；

First source electrode is electrically connected with the driving unit；

First drain electrode is electrically connected with first bit line and the second bit line；

Second source electrode is electrically connected with first bit line and the second bit line；

Second drain electrode is electrically connected with the reading unit.

7. sram cell as claimed in claim 5, which is characterized in that the first transistor and second transistor are NMOS；Alternatively, the first transistor and second transistor are PMOS.

8. a kind of detection method of sram cell, which is characterized in that including：

Sram cell as described in any one of claim 1 to 7 claim is provided；

The threshold voltage reference value to pull up transistor is provided；

Relational expression between the threshold voltage to pull up transistor and output current is provided；

Open the first transmission gate transistor and the second transmission gate transistor；

The driving unit loads low level by first bit line and the first transmission gate transistor to the fourth node, makes Described second pull up transistor unlatching, second pull-down transistor close, described second pull up transistor output second output Electric current；The driving unit is also low to second node load by second bit line and the second transmission gate transistor simultaneously Level makes the described first pull up transistor unlatching, first pull-down transistor close, and described first pulls up transistor output the One output current；

The reading unit passes through the first transmission gate transistor, the first bit line, the second transmission gate transistor and the second bit line Read the sum of first output current and second output current；

By the sum of first output current and second output current divided by two, output electric current measure value is obtained；

According to the relational expression and the output electric current measure value, obtain described first pull up transistor with described second on crystal pulling The threshold voltage detected value of body pipe；

Compare the threshold voltage detected value and threshold voltage reference value, when the threshold voltage detected value and threshold voltage reference When the absolute value of difference is more than preset difference value between value, judgement described first pulls up transistor to pull up transistor mistake with described second Effect.

9. the detection method of sram cell as claimed in claim 8, which is characterized in that the preset difference value 75mV is 125mV.

10. the detection method of sram cell as claimed in claim 8, which is characterized in that the driving unit is simultaneously to described Fourth node and the second node load in low level step, and the driving unit makes first bit line and the second bit line It is grounded simultaneously.

11. the detection method of sram cell as claimed in claim 8, which is characterized in that the step of providing the sram cell In, the sram cell further includes：The first enabling unit, the electrical connection reading for being electrically connected the driving unit and wordline are single First and wordline the second enabling unit and the selection list being electrically connected simultaneously with first enabling unit and the second enabling unit Member；First enabling unit includes the first transistor, and second enabling unit includes second transistor, and described first is brilliant Body pipe is identical with the transistor types of second transistor；

The detection method further includes：The selecting unit controls the first transistor and second transistor is opened simultaneously；

The driving unit loads low level to the fourth node by first bit line and the first transmission gate transistor, leads to It crosses second bit line and the second transmission gate transistor to load in low level step to the second node, the first crystal The first circuit loop is formed between pipe, the first bit line and the first transmission gate transistor, the driving unit passes through first electricity Road circuit loads low level to the fourth node；Between the first transistor, the second bit line and the second transmission gate transistor Second circuit circuit is formed, the driving unit loads low level by the second circuit circuit to the second node；

The reading unit passes through the first transmission gate transistor, the first bit line, the second transmission gate transistor and the second bit line It in the step of reading the sum of first output current and second output current, described first pulls up transistor, the first transmission gate It forms tertiary circuit circuit between transistor, the first bit line and second transistor, described second pulls up transistor, the second transmission gate The 4th circuit loop is formed between transistor, the second bit line and second transistor, the reading unit passes through the tertiary circuit Circuit and the 4th circuit loop read the sum of first output current and second output current.

12. a kind of detecting system of sram cell, which is characterized in that including：

Sram cell as described in any one of claim 1 to 7 claim；

The computing unit being connected with the sram cell, for the first output current of the sram cell and the second output is electric The sum of stream divided by two obtains output electric current measure value, and according to the pass between the threshold voltage and output current to pull up transistor It is formula, obtains described first and pull up transistor the threshold voltage detected value to pull up transistor with described second；

The judging unit being connected with the computing unit for providing the threshold voltage reference value to pull up transistor, and compares institute Threshold voltage detected value and threshold voltage reference value are stated, when difference between the threshold voltage detected value and threshold voltage reference value Absolute value when being more than preset difference value, judgement described first pulls up transistor to pull up transistor failure with described second.

13. the detecting system of sram cell as claimed in claim 12, which is characterized in that the preset difference value 75mV is 125mV。

14. a kind of SRAM device, which is characterized in that including：

Multiple memory modules arranged in arrays, the memory module include storage unit and transmission unit；The storage unit Including the first phase inverter and the second phase inverter；First phase inverter pulls up transistor and the first pull-down transistor including first, The source electrode of described first drain electrode and first pull-down transistor to pull up transistor is electrically connected, and described first pulls up transistor Drain electrode and first pull-down transistor source electrode tie point be first node, the described first grid to pull up transistor and The grid of first pull-down transistor is electrically connected, and the described first grid to pull up transistor and first pull-down transistor Grid tie point be second node；Second phase inverter pulls up transistor and the second pull-down transistor including second, institute The source electrode for stating drain electrode and second pull-down transistor that second pulls up transistor is electrically connected, and described second pulls up transistor The tie point of the source electrode of drain electrode and second pull-down transistor is third node, the described second grid to pull up transistor and institute State the grid electrical connection of the second pull-down transistor, and the described second grid to pull up transistor and second pull-down transistor The tie point of grid is fourth node；The second node is electrically connected with the third node, the first node and described the Four nodes are electrically connected；The transmission unit includes the first transmission gate transistor and the second transmission gate transistor, first transmission The drain electrode of door transistor is electrically connected with the first node, the drain electrode of the second transmission gate transistor and third node electricity Connection；

More wordline, each wordline with it is brilliant with the first transmission gate transistor of a line and the second transmission gate in the matrix The grid of body pipe corresponds to electrical connection；

More bit lines, including more the first bit lines and the second bit line being arranged alternately, each first bit line in the matrix The source electrode of the first transmission gate transistor of same row corresponds to electrical connection, each second bit line and same row in the matrix The second transmission gate transistor source electrode correspond to electrical connection；

The driving unit being electrically connected with the more bit lines, the driving unit are used to pass through the bit line and the transmission unit Simultaneously low level is loaded to the second node and the fourth node；

The reading unit being electrically connected with the more bit lines, the reading unit are used to pass through the bit line and the transmission unit Read the first output current that described first pulls up transistor and the sum of the second output current that described second pulls up transistor.

15. SRAM device as claimed in claim 14, which is characterized in that described first pull up transistor with second on crystal pulling Pipe is PMOS, first pull-down transistor, the second pull-down transistor, the first transmission gate transistor and the second transmission gate transistor For NMOS.

16. SRAM device as claimed in claim 14, which is characterized in that the SRAM device further include operating voltage power supply with And common voltage power supply；

Described first in the SRAM device pull up transistor the source electrode to pull up transistor with second with operating voltage power supply Electrical connection, the drain electrode of first pull-down transistor and the second pull-down transistor with common voltage power electric connection.

17. SRAM device as claimed in claim 14, which is characterized in that the SRAM device further includes：

Multiple first enabling units for being electrically connected the driving unit and Duo Gen bit lines, the multiple first enabling unit with The multiple memory module is corresponded and is electrically connected with the bit line of corresponding memory module；For being electrically connected the reading unit With multiple second enabling units of more bit lines, the multiple second enabling unit and the multiple memory module correspond and It is electrically connected with the bit line of corresponding memory module；It is electrically connected simultaneously with the multiple first enabling unit and multiple second enabling units The selecting unit connect；

The selecting unit is used to control first enabling unit corresponding to same memory module and the second enabling unit is same Shi Kaiqi is simultaneously turned off；

First enabling unit be used for control the driving unit simultaneously to corresponding memory module the second node and The fourth node loads low level；

Second enabling unit is used to control the reading unit and reads crystal pulling on described the first of corresponding memory module First output current of pipe and second the sum of the second output current for pulling up transistor.

18. SRAM device as claimed in claim 17, which is characterized in that first enabling unit includes the first transistor, Second enabling unit includes second transistor, and the first transistor is identical with the transistor types of second transistor；

The selecting unit is used to control the first transistor and second transistor corresponding to same memory module while opening It opens or simultaneously turns off.

19. SRAM device as claimed in claim 18, which is characterized in that the first transistor includes first grid, first Source electrode and the first drain electrode, the second transistor include second grid, the second source electrode and the second drain electrode；

First source electrode is electrically connected with the driving unit；

First drain electrode is electrically connected with first bit line of corresponding memory module and the second bit line；

Second source electrode is electrically connected with first bit line of corresponding memory module and the second bit line；

Second drain electrode is electrically connected with the reading unit.

20. SRAM device as claimed in claim 18, which is characterized in that the first transistor and second transistor are NMOS；Alternatively, the first transistor and second transistor are PMOS.