CN108306620B - Charge-guided amplifier circuit and control method thereof - Google Patents
Charge-guided amplifier circuit and control method thereof Download PDFInfo
- Publication number
- CN108306620B CN108306620B CN201710021056.9A CN201710021056A CN108306620B CN 108306620 B CN108306620 B CN 108306620B CN 201710021056 A CN201710021056 A CN 201710021056A CN 108306620 B CN108306620 B CN 108306620B
- Authority
- CN
- China
- Prior art keywords
- charge
- guided
- voltage
- input signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000003321 amplification Effects 0.000 claims abstract description 32
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 32
- 238000005070 sampling Methods 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims description 35
- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45031—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are compositions of multiple transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45148—At least one reactive element being added at the input of a dif amp
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
本公开提供一种电荷引导式放大电路及其控制方法。电荷引导式放大电路包含一电荷引导式差动放大器及一取样保持电路，该电荷引导式放大电路交替操作于一重置阶段及一放大阶段以放大一差动输入信号，该方法包含：于该重置阶段，根据该差动输入信号得到该差动输入信号的一共模电压；于该重置阶段，将该共模电压提供至该电荷引导式差动放大器及该取样保持电路的其中之一；于该重置阶段，利用该取样保持电路取样该差动输入信号以产生一电压信号；以及于该放大阶段，将该电压信号输入至该电荷引导式差动放大器。
The present disclosure provides a charge-guided amplifier circuit and a control method thereof. The charge-guided amplifier circuit includes a charge-guided differential amplifier and a sampling and holding circuit. The charge-guided amplifier circuit operates alternately in a reset phase and an amplification phase to amplify a differential input signal. The method includes: in the reset phase, obtaining a common-mode voltage of the differential input signal according to the differential input signal; in the reset phase, providing the common-mode voltage to one of the charge-guided differential amplifier and the sampling and holding circuit; in the reset phase, using the sampling and holding circuit to sample the differential input signal to generate a voltage signal; and in the amplification phase, inputting the voltage signal to the charge-guided differential amplifier.
Description
Technical Field
The present disclosure relates to charge-steering amplifiers, and more particularly, to amplification circuits implemented with charge-steering amplifiers.
Background
Fig. 1 is a circuit diagram of a conventional charge-steering differential amplifier. The charge-guided differential amplifier 100, also called dynamic amplifier (dynamic amplifier), is mainly composed of transistors 110 and 120, and further includes switches 130-160 and capacitors 170-190. The connection of the elements is shown in the figure. The charge-guided differential amplifier 100 alternately operates in a reset phase (phi)s) And an amplification stage (phi)h) To amplify the differential inputSignal ViAnd generates an output signal Vo. Switches 130, 140 and 150 are non-conductive during the reset phase and conductive during the amplification phase, and switch 160 is conductive during the reset phase and non-conductive during the amplification phase. The details of the operation of the charge-steering differential amplifier 100 are well known to those skilled in the art and will not be described in detail. It is noted that the gain (gain) of the charge-steering differential amplifier 100 and the gate-source voltages (V) of the transistors 110 and 120gs) Are closely related, so long as differential input signal V is presentiThe common mode voltage will slightly disturb (perturbation) the output signal VoThis has a considerable effect, which causes the performance of the charge-steering differential amplifier to be reduced.
Disclosure of Invention
In view of the deficiencies of the prior art, an object of the present disclosure is to provide a charge-steering amplifier circuit and a control method thereof, so as to improve the performance and stability of the charge-steering amplifier circuit.
The present disclosure discloses a charge-guided amplifier circuit alternately operating in a reset stage and an amplification stage to amplify a differential input signal, comprising: a sample-and-hold circuit, including a capacitor, for sampling the differential input signal to generate a voltage signal; a charge-directed differential amplifier, comprising: a transistor, a first end of the transistor receiving the voltage signal, a second end of the transistor being an output end of the charge-directed differential amplifier; a switch, which is not conducted in the reset stage and is conducted in the amplifying stage; and a capacitor coupled to a third terminal of the transistor through the switch; and a reference voltage generating circuit coupled to the charge-steering differential amplifier, for generating a reference voltage according to the differential input signal and outputting the reference voltage to the capacitor in the reset stage; wherein the reference voltage is related to a common mode voltage of the differential input signal.
The present disclosure further discloses a charge-guided amplifier circuit alternately operating in a reset stage and an amplification stage to amplify a differential input signal, comprising: a charge-directed differential amplifier receiving a voltage signal through an input; a sample-and-hold circuit coupled to the charge-steering differential amplifier and sampling the differential input signal to generate the voltage signal, comprising: a capacitor having a first end and a second end; and a plurality of switches, conducting or not conducting according to the reset stage and the amplifying stage; and a reference voltage generating circuit, coupled to the sample-and-hold circuit, for generating a first reference voltage according to the differential input signal, the first reference voltage being related to a common mode voltage of the differential input signal; wherein, in the reset stage, the first terminal of the capacitor receives the differential input signal and the second terminal of the capacitor is coupled to the first reference voltage, and, in the amplifying stage, the first terminal of the capacitor is coupled to the input terminal and the second terminal of the capacitor is coupled to a second reference voltage.
The present disclosure also discloses a control method of a charge-directed amplifier circuit, the charge-directed amplifier circuit including a charge-directed differential amplifier and a sample-and-hold circuit, the charge-directed amplifier circuit alternately operating in a reset stage and an amplification stage to amplify a differential input signal, the method including: in the reset stage, obtaining a common mode voltage of the differential input signal according to the differential input signal; providing the common mode voltage to one of the charge-steering differential amplifier and the sample-and-hold circuit during the reset phase; in the reset stage, the sampling and holding circuit is used for sampling the differential input signal to generate a voltage signal; and inputting the voltage signal to the charge-steering differential amplifier in the amplifying stage.
The charge-guided amplifying circuit and the control method thereof can effectively eliminate common-mode disturbance so as to improve the efficiency and stability of the charge-guided amplifying circuit. Compared with the prior art, the charge-guided amplification circuit and the control method thereof eliminate the common-mode disturbance in a feedforward mode, and can effectively prevent the common-mode disturbance from entering the charge-guided differential amplifier of the charge-guided amplification circuit.
The features, implementations, and technical effects of the present disclosure will be described in detail below with reference to the accompanying drawings.
Drawings
FIG. 1 is a circuit diagram of a conventional charge-steering differential amplifier;
fig. 2A is a circuit diagram of an embodiment of a charge-steering (charging-steering) amplification circuit of the present disclosure;
FIG. 2B is a circuit diagram of an embodiment of a charge-directed differential amplifier according to the present disclosure;
FIG. 3 is a circuit diagram of an embodiment of a reference voltage generating circuit according to the present disclosure;
FIG. 4 is a circuit diagram illustrating an operating state of the disclosed reference voltage generation circuit;
FIG. 5 is a circuit diagram of another operating state of the disclosed reference voltage generation circuit;
fig. 6A is a circuit diagram of another embodiment of a charge-directed amplification circuit of the present disclosure;
FIG. 6B is a circuit diagram of another embodiment of a charge-directed differential amplifier of the present disclosure;
FIG. 7 is a flowchart of one embodiment of a control method of a charge-steering amplifier circuit according to the present disclosure; and
fig. 8 is a flowchart of another embodiment of a control method of a charge-guided amplification circuit according to the present disclosure.
Description of reference numerals:
100. 100a, 100b, 210, 310 charge-steering differential amplifier
110. 120 transistor
130. 140, 150, 160, 130a, 140a, 150a, 160a, 130b, 140b, 150b, 160b, 222, 224, 226, 228, 233, 234, 235, 236, 237, 238, 321, 322, 323, 324, 325, 326, 327, 328 switches
170. 180, 190, 170a, 180a, 190a, 170b, 180b, 190b, 221, 225, 231, 232, 329a, 329b capacitance
200. 300 charge-guided amplifier circuit
220. 320 sample and hold circuit
230 reference voltage generating circuit
239 buffer unit
S710 to S750, S810 to S840
Detailed Description
The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.
The disclosure of the present disclosure includes a charge-directed amplification circuit and a control method thereof. Since some of the components included in the charge-steering amplifier circuit of the present disclosure may be known components alone, the following description will omit details of the known components without affecting the full disclosure and feasibility of the embodiments of the device. Furthermore, part or all of the flow of the control method of the charge-guided amplification circuit of the present disclosure may be in the form of software and/or firmware in combination with hardware, and may be executed by the charge-guided amplification circuit of the present disclosure or its equivalent device.
Fig. 2A is a circuit diagram of an embodiment of a charge-steering (charging-steering) amplification circuit of the present disclosure. The charge-directed amplifying circuit 200 includes a charge-directed differential amplifier 210, a sample-and-hold circuit 220, and a reference voltage generating circuit 230. The charge-directed differential amplifier 210 may be implemented by the charge-directed differential amplifier 100a of fig. 2B. The charge-steering differential amplifier 100a is mainly composed of transistors 110a and 120a, and further includes switches 130a to 160a and capacitors 170a to 190 a. As shown in fig. 2B, one end of the switch 160a is coupled to the reference voltage generating circuit 230. In detail, at the end of the reset phase, the voltage across the capacitor 190a in fig. 2B is the reference voltage Vref.
The sample-and-hold circuit 220 is used for sampling the differential input signal Vi(from voltage)
And voltage
Form) including electricityContainers 221, 225, and switches 222, 224, 226, 228. During the reset phase, switches 222 and 228 are conductive, and switches 224 and 226 are non-conductive. At the end of the reset phase, the voltages across the capacitors 221 and 225 are equal to the voltages
And voltage
During the amplification phase, switches 222 and 228 are not conductive and switches 224 and 226 are conductive, causing the voltage to be applied
And voltage
The charge-steering differential amplifier 210 may be input from nodes N1 and N2, respectively.
Fig. 3 is a circuit diagram of an embodiment of the reference voltage generating circuit 230. The reference voltage generating circuit 230 includes capacitors 231 and 232, switches 233-238, and a buffer unit 239 (in this example, an operational amplifier is used, but not limited thereto). During the amplification stage, the switches 233, 234 and 238 are turned off, and the switches 235, 236 and 237 are turned on, so as to form the circuit shown in FIG. 4, wherein the buffer unit 239 is in an idle state. At the end of the amplification phase, the voltages across the capacitors 231 and 232 are each Vb1And voltage Vb2The difference of (a). During the reset phase, the switches 233, 234 and 238 are turned on, and the switches 235, 236 and 237 are turned off, resulting in the circuit shown in fig. 5. The voltage at node N3 is the differential input signal ViOf the common-mode voltage VcmPlus a voltage Vb1And voltage Vb2The difference of (a). In other words, the reference voltage Vref (═ V) output by the reference voltage generation circuit 230 in the reset phasecm+Vb2-Vb1) Is a common mode voltage (V)cm) Applying a DC voltage (V)b2-Vb1) I.e. the reference voltage Vref and the differential input signal ViIs correlated with the common mode voltage.
Referring again to FIG. 2B, the above referenceThe voltage Vref causes the capacitor 190a to have a voltage Vref across it after the reset phase is completed. In the next amplification stage, the gate-source voltage of the transistor 110a
That is, Vgs＝(vd+Vcm)-(Vcm+Vb2-Vb1)＝vd-(Vb2-Vb1) Wherein v isdIs the differential voltage of the differential input signal. The transistor 120a is similar and will not be described again. It can be seen that the gate-source voltages V of the transistors 110a and 120a are now at this timegsIs no longer affected by the disturbance of the common mode voltage. In some embodiments, | - (V)b2-Vb1) | preferably, the threshold voltage (V) of the transistors 110a and 120a can be designed to be equal to or higher thanthTo ensure that transistors 110a and 120a are turned on. Although P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are exemplified as the transistors 110a and 120a, N-type implementation is also possible, which is well known in the art and will not be described herein.
In one simulation, the common mode voltage VcmIs a sine wave signal with a frequency equal to 125MHz and an amplitude equal to 100 mV. The simulation results show that, for the charge-guided amplifier circuit without the above mechanism, the signal-to-noise-plus-distortion ratio (SNDR) is reduced from 48.3dB (the common-mode voltage is not disturbed) to 25.2dB (the common-mode voltage is disturbed); in contrast, for the charge-guided amplification circuit of the present disclosure, the SNDR is reduced from 48.3dB to 34.2 dB. Therefore, the performance of the charge-guided amplifier circuit can be greatly improved by the Common Mode Perturbation Cancellation (CMPC) mechanism.
Fig. 6A is a circuit diagram of another embodiment of a charge-directed amplification circuit of the present disclosure. The charge-directed amplifying circuit 300 includes a charge-directed differential amplifier 310, a sample-and-hold circuit 320, and a reference voltage generating circuit 230. The charge-directed differential amplifier 310 may be implemented by the charge-directed differential amplifier 100B of fig. 6B. The charge-steering differential amplifier 100b is mainly composed of transistors 110b and 120b, and further includes switches 130 b-160b and capacitors 170 b-190 b. The sample-and-hold circuit 320 is used for sampling the differential input signal ViIncludes capacitors 329a and 329b and switches 321-328. In the reset phase, the switches 321, 324, 325 and 328 are turned on, and the switches 322, 323, 326 and 327 are turned off, so that the two ends of the capacitors 329a and 329b receive the differential input signal V respectivelyiAnd a reference voltage Vref. At the end of the reset phase, the voltage across capacitor 329a is
The capacitor 329b is similar and will not be described in detail.
In the next amplification stage, the switches 321, 324, 325 and 328 are turned off, and the switches 322, 323, 326 and 327 are turned on, so that one end of the capacitors 329a and 329b is coupled to the voltage Vb3And the other end is coupled to node N1 or N2. The input voltage obtained at the input of the charge-steering differential amplifier 310 is Δ V + Vb3＝vd-(Vb2-Vb1)+Vb3. It can be seen that the input voltage of the charge-steering differential amplifier 310 is not affected by the common-mode voltage disturbance at this time. In some embodiments, | - (V)b2-Vb1)+Vb3| preferably, the threshold voltage V of the transistors 110b and 120b can be designed to be greater than or equal tothTo ensure that transistors 110b and 120b are turned on. For example, V can be designedb1＝Vb2Thus, the voltage V can be simply adjustedb3To adjust the bias voltage of the transistors 110b and 120b, i.e., to adjust the voltage | Vb3Designed to be greater than or equal to the threshold voltage V of the transistors 110b and 120bthAbsolute value of (a).
The performance of the charge-guided amplifier circuit can be greatly improved by the common-mode disturbance elimination mechanism.
In summary, the common mode disturbance cancellation mechanism of the present disclosure takes out the common mode voltage of the differential input signal, and transmits the common mode voltage to the charge-guided differential amplifier or the sample-and-hold circuit of the charge-guided differential amplification circuit in a feed-forward (feed-forward) manner, so as to cancel the common mode disturbance. In a conventional Feedback (Feedback) method (e.g., Common Mode Feedback (CMFB)), a disturbance of a Common Mode voltage is analyzed from an output of the charge-steering differential amplifier, and a bias state of a transistor is adjusted by Feedback according to the disturbance. In detail, the feedback approach is to utilize the output signal of this round (one round includes a reset stage and an immediately adjacent amplification stage) to mitigate the common mode voltage disturbance of the next round, however, the effect of the feedback approach is poor because the disturbed input common mode voltage will affect the gain of this round of the amplification circuit anyway. In contrast, the feed-forward approach of the present disclosure utilizes the input signal of the current round to eliminate the common mode voltage disturbance of the current round, so that the signal processed by the charge-steering differential amplifier can ideally completely eliminate the common mode voltage disturbance, and the stability of the gain of the charge-steering differential amplifier is improved.
The embodiment of fig. 6A of the present disclosure is also applicable to (1) the charge-steering differential amplifier of fig. 6B in which the transistors 110B and 120B are biased by current sources; and (2) the charge-steering differential amplifier with the transistors 110B and 120B of FIG. 6B directly coupled to a reference potential (e.g., the sources of the transistors 110B and 120B are directly coupled to ground). The details of the operations of the above embodiments (1) and (2) are well known to those skilled in the art and are not described herein.
In addition to the charge-steering amplifier circuit, the present disclosure also discloses a control method of the charge-steering amplifier circuit. Fig. 7 is a flowchart of one embodiment of the method, which can be performed by the charge-steering amplifier circuit 200 or its equivalent, comprising the steps of:
step S710: in the reset stage, a common mode voltage of the differential input signal is obtained according to the differential input signal. The common mode voltage is obtained, for example, by the reference voltage generating circuit 230 of fig. 3;
step S720: in a reset phase, the common mode voltage is provided to a charge-steering differential amplifier. In detail, the charge-guided differential amplifier comprises a transistor and a capacitor, the common-mode voltage is provided to one end of the capacitor coupled to the source of the transistor;
step S730: in the reset stage, a direct current voltage is provided to the capacitor of the charge-guided differential amplifier at the same time, so that the same end of the capacitor receives the common-mode voltage and the direct current voltage at the same time;
step S740: in the reset stage, the sampling and holding circuit is used for sampling the differential input signal to generate a voltage signal; and
step S750: in the amplifying stage, the voltage signal is input to the charge-guided differential amplifier.
The details of the operation of the process of fig. 7 and other corresponding control steps will be known to those skilled in the art from the foregoing description of the charge-steering amplifier circuit 200 and will not be described in gift presented to a senior at one's first visit as a mark of esteem.
Fig. 8 is a flowchart of an embodiment of the method, which can be performed by the disclosed charge-steering amplifier circuit 300 or its equivalent, comprising the steps of:
step S810: in the reset stage, a common mode voltage of the differential input signal is obtained according to the differential input signal. The common mode voltage is obtained, for example, by the reference voltage generating circuit 230 of fig. 3;
step S820: in the reset stage, the common mode voltage is provided to a sampling holding circuit;
step S830: in the reset stage, the sampling and holding circuit is used for sampling the differential input signal to generate a voltage signal; and
step S840: in the amplifying stage, the voltage signal is input to the charge-guided differential amplifier.
The details of the operation of the flow chart of fig. 8 and other corresponding control steps will be known to those skilled in the art from the foregoing description of the charge-steering amplifier circuit 300, and therefore will not be described in gift presented to a senior at one's first visit as a mark of esteem.
Because those skilled in the art can appreciate details and variations of implementing method embodiments of the present disclosure from the disclosure of apparatus embodiments of the present disclosure, repeated descriptions are omitted herein for the avoidance of unnecessary detail without affecting the disclosed requirements and the implementability of the method embodiments. It should be noted that the shapes, sizes, proportions, and sequence of steps of the elements and steps shown in the drawings are illustrative only and are not intended to limit the present disclosure, which is understood by those skilled in the art.
Although the embodiments of the present disclosure have been described above, these embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of patent protection sought by the present disclosure.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710021056.9A CN108306620B (en) | 2017-01-11 | 2017-01-11 | Charge-guided amplifier circuit and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710021056.9A CN108306620B (en) | 2017-01-11 | 2017-01-11 | Charge-guided amplifier circuit and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108306620A CN108306620A (en) | 2018-07-20 |
| CN108306620B true CN108306620B (en) | 2021-03-16 |
Family
ID=62872144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710021056.9A Active CN108306620B (en) | 2017-01-11 | 2017-01-11 | Charge-guided amplifier circuit and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108306620B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115706568A (en) * | 2021-08-10 | 2023-02-17 | 瑞昱半导体股份有限公司 | Charge-guided amplifier circuit and control method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989603A (en) * | 1989-05-19 | 1991-02-05 | Ventritex, Inc. | Implantable cardiac defibrillator employing a switched capacitor filter stage having a low charge-injection induced offset voltage |
| US5025172A (en) * | 1989-05-19 | 1991-06-18 | Ventritex, Inc. | Clock generator generating trapezoidal waveform |
| US6097248A (en) * | 1998-04-10 | 2000-08-01 | Yokogawa Electric Corporation | Switched capacitor amplifier with one-clock delay |
| CN101860335A (en) * | 2010-06-03 | 2010-10-13 | 复旦大学 | A Headroom Gain Amplifying Circuit Shared by Dual Input Operational Amplifiers |
| US8922275B2 (en) * | 2011-08-17 | 2014-12-30 | Linear Technology Corporation | Common mode input control for switch capacitor amplifier in pipeline analog-to-digital converter |
| WO2016083251A1 (en) * | 2014-11-24 | 2016-06-02 | Bang & Olufsen A/S | Solid state switch relay |
| CN105959008A (en) * | 2015-03-09 | 2016-09-21 | 爱思开海力士有限公司 | Preamplifier, and comparator and analog-to-digital converting apparatus including the same |
| CN105991094A (en) * | 2015-03-17 | 2016-10-05 | 瑞昱半导体股份有限公司 | Summing amplifier and method thereof |
| CN205657655U (en) * | 2016-04-05 | 2016-10-19 | 西安虹陆洋机电设备有限公司 | Novel charge amplifier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4556824B2 (en) * | 2005-09-27 | 2010-10-06 | 日本電気株式会社 | Differential amplifier, digital / analog converter, and display device |
| JP5044242B2 (en) * | 2007-03-08 | 2012-10-10 | オンセミコンダクター・トレーディング・リミテッド | Amplifier circuit |
| JP4564558B2 (en) * | 2008-09-19 | 2010-10-20 | 株式会社半導体理工学研究センター | Differential operational amplifier circuit and pipeline type A / D converter using the same |
| JP5733277B2 (en) * | 2012-07-13 | 2015-06-10 | 株式会社デンソー | Capacitive sensor detection circuit |
| US9503119B2 (en) * | 2014-05-29 | 2016-11-22 | Texas Instruments Incorporated | Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters |
-
2017
- 2017-01-11 CN CN201710021056.9A patent/CN108306620B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989603A (en) * | 1989-05-19 | 1991-02-05 | Ventritex, Inc. | Implantable cardiac defibrillator employing a switched capacitor filter stage having a low charge-injection induced offset voltage |
| US5025172A (en) * | 1989-05-19 | 1991-06-18 | Ventritex, Inc. | Clock generator generating trapezoidal waveform |
| US6097248A (en) * | 1998-04-10 | 2000-08-01 | Yokogawa Electric Corporation | Switched capacitor amplifier with one-clock delay |
| CN101860335A (en) * | 2010-06-03 | 2010-10-13 | 复旦大学 | A Headroom Gain Amplifying Circuit Shared by Dual Input Operational Amplifiers |
| US8922275B2 (en) * | 2011-08-17 | 2014-12-30 | Linear Technology Corporation | Common mode input control for switch capacitor amplifier in pipeline analog-to-digital converter |
| WO2016083251A1 (en) * | 2014-11-24 | 2016-06-02 | Bang & Olufsen A/S | Solid state switch relay |
| CN105959008A (en) * | 2015-03-09 | 2016-09-21 | 爱思开海力士有限公司 | Preamplifier, and comparator and analog-to-digital converting apparatus including the same |
| CN105991094A (en) * | 2015-03-17 | 2016-10-05 | 瑞昱半导体股份有限公司 | Summing amplifier and method thereof |
| CN205657655U (en) * | 2016-04-05 | 2016-10-19 | 西安虹陆洋机电设备有限公司 | Novel charge amplifier |
Non-Patent Citations (2)
| Title |
|---|
| A low-power high-speed charge-steering comparator for high-speed applications;Ali H. Hassan;《2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)》;20161024;第I-IV节 * |
| 一种用于抑制共模信号的差分放大电路的研究;朱士龙;《现代电子技术》;20150915;110-112 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108306620A (en) | 2018-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI612769B (en) | Charging-steering amplifier circuit and control method thereof | |
| TWI382669B (en) | Comparator for a pipelined analog to digital converter and related signal sampling method | |
| US6577184B2 (en) | Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current | |
| CN103338014B (en) | Operational Amplifier Circuit | |
| TWI451692B (en) | Pseudo differential switched capacitor circuit | |
| US9160323B2 (en) | Differential amplifier and dual mode comparator using the same | |
| CN107896095B (en) | Fully differential operational amplifier | |
| CN104467704A (en) | Audio amplifier, electronic device using same and transient noise suppression method | |
| CN114710124B (en) | Rail-to-rail input-output operational transconductance amplifier based on low ripple charge pump | |
| US7271663B2 (en) | Operational amplifier output stage and method | |
| US7696822B2 (en) | Amplifying circuit and associated linearity improving method | |
| US10425042B2 (en) | Negative capacitance circuits including temperature-compensation biasings | |
| US7408410B2 (en) | Apparatus for biasing a complementary metal-oxide semiconductor differential amplifier | |
| US20230092750A1 (en) | Reception circuit for optical communication | |
| US11664774B2 (en) | Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method | |
| CN108306620B (en) | Charge-guided amplifier circuit and control method thereof | |
| CN108183691B (en) | Folded cascode operational amplifier | |
| JP6784375B2 (en) | Transimpedance amplifier | |
| KR20230143932A (en) | Super source follower | |
| US10146245B2 (en) | I-V converting module | |
| CN114697807B (en) | Audio driver circuit and audio processing equipment | |
| EP1124326A1 (en) | An operational amplifier with high gain and sysmmetrical output-current capabilty | |
| CN108155882B (en) | Operational Amplifier and Its Differential Amplifying Circuit | |
| US20120270512A1 (en) | Transfer Gate Circuit and Power Combining Circuit, Power Amplifying Circuit, Transmission Device, and Communication Device Using the Transfer Gate Circuit | |
| TW202308299A (en) | Charge-steering amplification circuit and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |