CN108306496A - Actively start timing controlled in fault mode - Google Patents

Abstract

The power switch transistor of the switch power converter is maintained to be connected by Zener breakdown voltage during restarting period after the fault state of switch power converter.Source voltage from power switch transistor is used to charge to VCC capacitors, which is that the controller of switch power converter stores supply voltage.

Description

Active start timing control in failure mode

Cross References to Related Applications

This application claims priority and benefit to U.S. Provisional Patent Application No. 62/446,344, filed January 13, 2017, which is hereby incorporated by reference in its entirety.

technical field

This application relates to switching power converter controllers, and more particularly to switching power converter controllers with active start-up timing control.

Background technique

The high efficiency of switching power converters such as flyback converters has led to their virtually universal suitability as battery chargers for mobile devices. Because flyback converters convert AC household voltage, fault conditions such as short circuits can be potentially dangerous. It is thus common for flyback converter controllers to monitor various fault conditions. If the controller detects that a fault condition exists, it stops cycling the power switches and enters a restart period. At the end of the restart period, the controller will resume normal operation again. If the fault condition reoccurs, the controller will again stop cycling the power switches and begin another start-up period. The duration of this startup period is of considerable importance because if the failure is persistent, it will keep recurring after each startup period. If the start-up period is too short in the presence of an output short circuit fault, components of the flyback converter may be stressed or damaged due to the heat and excess current generated by such repeated faults.

The duration of the restart period is thus essential to minimize power loss and avoid stressing switching power converter components after a fault condition. The restart period cannot be too short as described above. But in turn, the restart period should not be too long, otherwise it may exceed user requirements. However, conventional control of the restart period has a number of disadvantages which can be better appreciated with reference to a conventional prior art switching power converter as illustrated in FIG. 1 . The controller U1 controls the cycling of the power switching transistor S2 in series with the primary winding T1 of the flyback converter's transformer (not shown). Depending on the load requirements, the controller U1 will turn on the power switch transistor S2 by a drive signal applied to its gate. Power switch transistor S2 is in series with current sense resistor R2 so that controller U1 can measure the primary winding current by sensing the voltage across the current sense resistor. The input voltage V_in (V_IN) drives the primary winding current when the power switch transistor S2 is cycled on, the input voltage V_in being generated, for example, by rectification of the AC mains voltage.

Controller U1 receives its supply voltage VCC from a VCC capacitor coupled between the source of supply voltage regulator switching transistor S1 and ground. The drain of the supply voltage regulator switching transistor S1 is coupled to the input voltage rail of the supply input voltage through the current limiting resistor R1. When the controller U1 cycles the supply voltage regulator switching transistor S1 on, the input voltage senses the current through the current limiting resistor R1 and the supply voltage regulator switching transistor S1 to charge the VCC capacitor with the supply voltage VCC. If the controller U1 must restart due to a fault condition, the controller U1 manages the duration of the restart period by cycling the supply voltage regulator switching transistor S1 off and on. Because the charge on the VCC capacitor is "recirculated" due to the transfer of the supply voltage VCC to the power controller U1, each turn-off and turn-on cycle can be designated as a VCC recirculation period. Some waveforms of the resulting restart period are shown in FIG. 2 .

In the event of a fault condition, the controller U1 enters an initial or first VCC recirculation period with the supply voltage regulator switching transistor S1 turned off. During the initial part of this VCC recirculation period, controller U1 operates in an active mode such that it draws a relatively large current (Icc_high) from the VCC capacitor. The supply voltage VCC thus falls relatively quickly until it reaches the threshold Vcc_low (Vcc_low). The controller U1 monitors the supply voltage VCC to determine if it has decreased to the Vcc_low threshold voltage, whereupon the controller cycles the supply voltage regulator switching transistor S1 on. The supply voltage VCC then begins to increase until it reaches a maximum value Vcc_st, at which point the controller U1 switches off the supply voltage regulator switching transistor S1. When the supply voltage regulator switching transistor S1 is on, the controller U1 operates in a sleep or sleep mode such that it draws virtually no current from the VCC capacitor.

Controller U1 repeats the VCC recirculation period a total of N times to complete the desired restart period. At the end of the restart period, controller U1 resumes normal operation. Restart timing control is thus achieved by controlling the number of VCC recirculation periods. During these regular recycle periods, the duration of each recycle period is governed by the charging of the VCC capacitor while the supply voltage is increased from Vcc_low to Vcc_st. The VCC charging time is controlled by the resistance of the current limiting resistor R1. This dependence on the current limiting resistor R1 prolongs the charging time of the VCC capacitor such that the duration of the VCC recirculation period is dependent on the input voltage V_IN. For example, when V_IN exceeds its rated voltage, the magnitude of the charging current to charge the VCC capacitor increases, which results in a shorter VCC recirculation period. In turn, this results in a shortened restart period. Conversely, a reduction in input voltage lengthens the duration of the recirculation period and the restart period. Thus, a problem with the prior art dependence on V_IN changes is that the restart timing cannot be accurately predicted.

Therefore, there is a need in the art for improved restart timing control techniques for switching power converters.

Contents of the invention

To address the need in the art for improved restart timing control, a controller is provided that actively controls the restart period after a fault condition by implementing a slow VCC discharge time independent of input voltage to dominate the VCC recirculation period. In this way, reliable active restart timing control is possible regardless of the range of input voltages. A reasonable and accurate restart period is thereby achieved after a fault condition, which prevents the switching power converter from being overstressed. The slow VCC discharge period advantageously prevents undesired dependence on the input voltage with respect to controlling the duration of the restart period. These advantageous features can be better appreciated by considering the following detailed description.

Description of drawings

FIG. 1 is a diagram of a conventional switching power converter configured for start-up timing control according to an embodiment of the present disclosure.

FIG. 2 shows waveforms of a conventional switching power converter with start-up timing control according to an embodiment of the disclosure.

3 is a diagram of a switching power converter configured for active start-up timing control according to an embodiment of the disclosure.

FIG. 4 illustrates waveforms of a switching power converter configured for active start-up timing control according to an embodiment of the disclosure.

Embodiments of the present disclosure and their advantages are best understood by reference to the ensuing detailed description. It should be appreciated that like reference numerals are used to identify like elements shown in one or more figures.

Detailed ways

The following discussion will focus on flyback converters. However, it will be appreciated that the improved restart period disclosed herein may be implemented in other types of switching power converters, such as buck converters, boost converters, or buck-boost converters. An example flyback converter 300 configured for a restart period independent of input voltage is shown in FIG. 3 . As is known in the field of flyback converters, the flyback converter 300 includes a power switch transistor S2 in series with the primary winding of a transformer T1, a control configured to control the on and off states of the power transistor switch S2. device U1. During normal operation, the on and off states of the power switching transistor S2 are controlled by the drive terminal of the controller U1 coupled to the gate of the power switching transistor S2, and the controller U1 can maintain the output to the flyback converter 300 Output regulation of the voltage (for simplicity of presentation, the secondary side of the transformer is not shown in Figure 3). The primary winding has a number Np of coils. The power switching transistor S2 may be a field effect transistor (FET) device (eg, a metal oxide field effect transistor (MOSFET) device), a bipolar junction transistor (BJT) device, or other suitable switching transistor. During normal operation, when power switching transistor S2 is placed in the conducting state, the input voltage V_IN carried on the input voltage rail drives a magnetizing or primary current into the primary winding of transformer T1. Based on the input voltage and the magnetizing inductance of the transformer, the primary current ramps up from zero amperes (Amps) to the peak current value, so the controller U1 turns off the power switching transistor S2 to complete the power cycle.

The controller U1 further includes a timer 314 . The voltage control module 312 may include logic gates or a microcontroller. Timer 314 may include analog or digital circuitry. In other embodiments, the voltage control module 312 and the timer 314 may be implemented using a combination of hardware, software, and/or firmware components.

Upon detection of a fault condition, such as an output short circuit, the controller U1 enters a restart period. The restart period includes a series of recycle periods during which the voltage control module 312 cycles the supply voltage switching transistor S3 on and off to regulate the supply voltage VCC stored on the VCC capacitor 316 . The supply voltage switching transistor S3 is coupled between the source of the power switching transistor S2 and the current limiting resistor R3. The cathode of Zener diode Z1 is connected to the gate of power switching transistor S2, while the anode of Zener diode Z1 is grounded. The gate of the power switch transistor S2 is coupled to the input voltage rail through a resistor R4. In some embodiments, Zener diode Z1 may have a Zener breakdown value of fifteen volts DC. The input voltage will typically be higher than such a value that the gate of power switch transistor S2 will be charged to the Zener breakdown voltage during the restart period. If the supply voltage switching transistor S3 is cycled on, the source of the power switching transistor S2 will be powered below the Zener breakdown voltage because the power switching transistor S2 will be turned on due to charging its gate through the Zener breakdown voltage Threshold voltage of switching transistor S2. Advantageously, the source voltage of the power switching transistor S2 is thus independent of input voltage variations, but is determined by the Zener breakdown voltage and the threshold voltage. Since the source voltage is the voltage that supplies the charging of the VCC capacitor, the charging of the supply voltage VCC generated in each recycle period is independent of the input voltage.

During normal operation, the source of power switching transistor S2 is coupled to ground through switching transistor S4 and resistor R5. In response to the fault condition, switching transistor S4 is cycled off. Switching transistor S4 will then cycle back into conduction at the end of the restart period so that normal operation can continue.

When supply voltage switching transistor S3 is closed, the source voltage at power switching transistor S2 will cause charge to flow through current limiting resistor R3 into the VCC capacitor to charge the supply voltage VCC stored across the VCC capacitor. As will be explained further herein, a slow discharge period will dominate each recycle period. The resistance of the current limiting resistor R3 can therefore be relatively small so that the VCC capacitor is charged relatively quickly to the high threshold voltage Vcc_st. Additionally, controller U1 is configured to enter a sleep mode so as to draw virtually no current when supply voltage switching transistor S3 is closed. Thus the charging period during which the supply voltage switching transistor S3 is closed is quite short, since the small resistance of the current limiting resistor R3 will cause a considerable amount of charge to flow into the VCC capacitor to bring the supply voltage VCC from the low threshold The voltage Vcc_low is charged to the high threshold voltage Vcc_st. The recycle period is thus governed by the slow discharge time as measured by timer 314 . Because the charging time of supply VCC is independent of the input voltage during each recycle period, each recycle period is controlled by timer 314, as will be explained further herein.

The operation of the flyback converter 300 during the restart period can be better understood with consideration of the waveforms shown in FIG. 4 . During normal operation, the voltage control module 312 places the supply voltage switching transistor S3 in an off state. The VCC capacitor 316 is fully charged to the high threshold level Vcc_st and the Icc load current drawn by the controller U1 is equal to the high level Icc_high during normal operation of the controller U1.

After a fault condition is detected, the timer 314 begins timing the slow VCC discharge period at the first recycle period, and the voltage control module 312 turns off the supply voltage switching transistor S3. At the same time, controller U1 enters a low power timing mode, which only supports timing of slow discharge periods by timer 314 . The Icc current drawn by controller U1 during the slow discharge period is thus reduced to Icc_low during the slow VCC discharge period. Advantageously, the timing of the slow VCC discharge period is apparently independent of the input voltage. Upon completion of the slow VCC discharge period as timed by timer 314, controller U1 reverts to normal operation and thus begins drawing a relatively large supply current (Icc_high) during the fast discharge period. This causes the supply voltage VCC to rapidly discharge below the low voltage threshold Vcc_low (which may also be indicated as the minimum threshold voltage), whereby the voltage control module 312 turns on the supply voltage switching transistor S3. The supply voltage is then rapidly charged to the high threshold voltage Vcc_st. The recycle period is repeated N times (N is a complex integer) to complete the restart period. Thus, the number of rapid charges and discharges in each recycle period is insignificant compared to the slow discharge period, so that the restart period is dominated by N slow discharge periods. Because the slow discharge period is independent of the input voltage, the duration of the restart period is reliably controlled despite changes in the input voltage. After the restart period is complete, normal operations may then ensue.

A method of operation for controlling the duration of a restart period will now be discussed. The method includes an act of responding to the fault condition by ceasing normal operation of the power switching transistor and initiating a restart period, wherein the restart period extends for a plurality of recycle periods. The initiation of a recirculation period discussed with respect to FIG. 4 is an example of this action. The method also includes the act of charging the gate of the power switch transistor with the zener breakdown voltage to generate a source voltage at the source terminal of the power switch transistor during each recycle period. Generating a source voltage to power switching transistor S2 is an example of this action. The method also includes acts of discharging the supply voltage stored across the VCC capacitor in each recycle period during the discharge period and charging the VCC capacitor with the source voltage in response to the supply voltage falling below a minimum threshold voltage at the end of the discharge period . A slow discharge period followed by a fast discharge period for each recycle period is an example of a discharge action. Finally, the switching on of supply voltage switching transistor S3 is an example of a charging action.

As those skilled in the art will now appreciate, and depending on the particular application at hand, many modifications, substitutions and variations may be made in the materials, arrangement, configuration and methods of use of, and the apparatus of the present disclosure without departing from the scope thereof . For example, the discussion above is in relation to flyback converters, but it will be appreciated that the restart periods disclosed herein can be implemented in other switching power converters such as buck converters, boost converters, or buck-boost converters. accomplish. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments illustrated and described herein (as these are by way of illustration only of some of them), but rather should be limited by the scope of the claims appended hereto and their The functional equivalents of .

Claims (20)

1. A switching power converter, characterized in that, the switching power converter comprises: power switching transistor; current limiting resistor; a supply voltage switching transistor coupled between the source of the power switching transistor and the first terminal of the current limiting resistor; a VCC capacitor for storing a supply voltage, wherein the VCC capacitor is coupled between the second terminal of the current limiting resistor and ground; a zener diode having a cathode coupled to the gate of the power switching transistor and an anode coupled to ground; a resistor coupled between the input voltage node of the flyback converter and the cathode of the zener diode; and a controller configured to regulate the output voltage of the switching power converter by controlling cycling of the power switching transistor during normal operation, the controller further configured to regulate the output voltage of the switching power converter by ceasing normal operation and by making the supply voltage The switching transistor cycles through the restart period in response to the fault condition. 2. The switching power converter of claim 1, wherein the controller is configured to cycle the supply voltage switching transistor through a plurality of recycle periods within the restart period. 3. The switching power converter of claim 2, wherein the controller includes a timer, and wherein the controller is configured to follow the supply voltage during a period of slow discharge of the supply voltage turning off the voltage switching transistor to begin each recycle period during which the controller receives a first current from the VCC capacitor, and wherein the timer is configured to time the slow discharge period . 4. The switching power converter of claim 3, wherein the controller is further configured to enter a fast discharge period of the supply voltage at each recycle period upon completion of the slow discharge period, Wherein the controller is further configured to receive a second current from the VCC capacitor during the fast discharge period, and wherein the second current is greater than the first current. 5. The switching power converter of claim 4, wherein the controller is further configured to switch the power supply voltage less than a low threshold voltage at the end of the fast discharge period at each recycle A period enters a fast charge period of the supply voltage, and wherein the controller is configured to turn on the supply voltage switching transistor during the fast charge period and to switch off by responding to the supply voltage being greater than a high threshold voltage The supply voltage switches the transistor to end the fast charge period. 6. The switching power converter of claim 5, wherein the controller is further configured to draw substantially no current from the VCC capacitor during each fast charge period. 7. The switching power converter of claim 1, wherein the power switching transistor and the supply voltage switching transistor are both NMOS transistors. 8. The switching power converter of claim 1, wherein the zener breakdown voltage of the zener diode is approximately 15 to 25 volts. 9. The switching power converter of claim 5, wherein the controller further comprises a voltage control module for controlling the voltage of the supply voltage switching transistor during the recirculation period. cycle. 10. A method of controlling the duration of a restart period of a switching power converter, the method comprising: responding to a fault condition by ceasing normal operation of a power switching transistor and initiating the restart period, wherein the restart period extends for a plurality of recycle periods; during the restart period, maintaining the power switch transistor on by driving the gate of the power switch transistor with a zener breakdown voltage from a zener diode; During each recycling period: timing a slow discharge period of a supply voltage stored across a VCC capacitor from which a controller powered by the supply voltage draws a first current; drawing a second current from the VCC capacitor to power the controller during a fast discharge period of the supply voltage at the end of the slow discharge period, wherein the second current is greater than the first current; terminating the fast discharge period and initiating a fast charge period by charging the VCC capacitor using the source voltage of the power switch transistor in response to the supply voltage falling below a low threshold voltage; and The fast discharge period is completed in response to the supply voltage exceeding a high threshold voltage, wherein the high threshold voltage is greater than the low threshold voltage. 11. The method of claim 10, wherein the switching power converter is a flyback converter. 12. The method of claim 10, wherein using the source voltage to charge the VCC capacitor comprises turning on a supply voltage switching transistor to couple the VCC capacitor to the power switching transistor. source. 13. The method of claim 12, wherein coupling the VCC capacitor to the source of the power switch transistor comprises coupling the VCC capacitor to the power switch transistor through a current limiting resistor source. 14. The method of claim 10, wherein driving the gate of the power switch transistor with the Zener breakdown voltage from the Zener diode comprises coupling the cathode of the Zener diode to The input voltage node of the switching power converter. 15. The method of claim 14, wherein coupling the cathode of the Zener diode comprises coupling the cathode of the Zener diode to the input voltage node through a resistor. 16. A method of controlling the duration of a restart period of a switching power converter, the method comprising: responding to a fault condition by ceasing normal operation of a power switching transistor and initiating the restart period, wherein the restart period extends for a plurality of recycle periods; During each recycling period: charging a gate of a power switching transistor with a zener breakdown voltage to generate a source voltage at a source terminal of the power switching transistor; During the discharge period, discharging the supply voltage stored across the VCC capacitor; and The VCC capacitor is charged with the source voltage in response to the supply voltage falling below a minimum threshold voltage at the end of the discharge period. 17. The method of claim 16 , wherein each discharge period comprises a slow discharge period and a fast discharge period during which a first current is drawn from the VCC capacitor and during said fast discharge period A second current is drawn from the VCC capacitor for a period of time, wherein the second current is greater than the first current. 18. The method of claim 17, wherein the second current is equal to an operating current for a controller of the switching power converter during normal operation. 19. The method of claim 16, further comprising resuming the normal operation upon completion of the restart period. 20. The method of claim 16, wherein substantially no current is drawn from the VCC capacitor during each fast charge period.