CN108305877B - A gate-last junctionless NAND flash memory and method of making the same - Google Patents

Abstract

The present invention provides a gate-last non-junction NAND gate flash memory and a manufacturing method thereof. The memory includes: a substrate, an insulating layer, a two-dimensional semiconductor material channel layer, a carbon nanotube grid array, a gate trapping structure, and a protective layer , source contact electrode and drain contact electrode. The gate trapping structure includes a tunnel layer, a charge trapping layer and a blocking layer, wherein the tunnel layer is located on the channel layer, and the blocking layer surrounds the outer sides of the carbon nanotubes in the carbon nanotube grid array , the charge trapping layer includes a first portion surrounding the outer side of the blocking layer and a second portion overlying the tunnel layer and in contact with the first portion. The gate-last non-junction NAND flash memory of the present invention adopts a two-dimensional semiconductor material horizontal channel and a metallic carbon nanotube grid array, and the blocking layer and the charge trapping layer surround the carbon nanotube grid, which can not only simplify the device structure , improve the memory cell density, and can also obtain stronger gate charge trapping performance.

Description

A gate-last junctionless NAND flash memory and method of making the same

technical field

The invention belongs to the technical field of integrated circuits, and relates to a gate-last non-junction NAND flash memory and a manufacturing method thereof.

Background technique

For NAND memory with different architectures, it can be divided into three-dimensional floating gate memory and three-dimensional charge trapping memory according to the material of the storage layer. The former is mainly recommended by Micron in the United States, and the technical preparations were completed at the end of 2015. Since the polysilicon floating gate is used as the storage layer, the memory cell area is larger, and the process is more difficult to realize the stacking of more layers of memory cells. Therefore, it is mainly The area reduction is achieved by placing peripheral circuits under the memory array. For the latter three-dimensional charge trapping memory, it can be further divided into vertical gate type and vertical channel type. The three-dimensional charge trapping flash memory structure based on the vertical gate structure introduced by Taiwan Macronix is more difficult than the vertical channel type in the process, and it has never been announced for mass production. Vertical channel 3D charge trapping memory is the earliest flash memory product to achieve mass production. In August 2013, Samsung Electronics launched the first generation of 24-layer 3D vertical channel charge trapping 3D memory, which was launched in July 2014. The second generation of 32-layer 128Gb products, 48-layer 256Gb products were launched in 2015.

Samsung Electronics' vertical-channel three-dimensional charge-trapping memory cell is also based on a junctionless field-effect transistor structure. The chip has 24 stacked word lines (WLs). Except for the bottommost cell selection transistor, which is in the conventional inversion mode, each word cell transistor is based on a charge trap flash memory junctionless thin-film transistor (JL Charge Trap Flash Thin-film Transistor, JL-CTF TFT). The polysilicon film channel (tubular) is required to be fully depleted when the device is turned off; therefore, the polysilicon film thickness (TCH) should be as thin as possible. In addition, the strong demand to further increase the density of memory cells is also driving the shrinking of the polysilicon thin film channel TCH. Compared with devices operating in inversion mode (IM), this product exhibits superior performance, providing faster write/erase (P/E) speed, larger memory window (>12V), and better endurance (>10 ⁴ times); also has excellent 10-year data retention ability under 150 ℃ test conditions. Even better is the fact that the device has a switch current ratio greater than 10 ⁸ and a very steep subthreshold swing. However, the device channel material adopts polysilicon film, which requires good crystallinity and larger crystal grains. At the same time, the polysilicon film thickness (T _CH ) is required to be as thin as possible. It is difficult to take into account the process and affects the product yield.

Silicon (Si) transistors are not predicted to have gate lengths below 5 nanometers because of severe short-channel effects. As an alternative to silicon, some layered semiconductors are more attractive due to their uniform single-atom layer thickness, lower dielectric constant, larger band gap, and heavier effective carrier mass. Allows a smaller gate to control its current flow. Sujay et al. demonstrated a MoS2 transistor with a gate length of only ₁ nm, which uses single-walled carbon nanotubes as the gate electrode, in which a single carbon nanotube with a diameter of ₁ nm is embedded in a thin layer of MoS2 (0.65 nm thick) in the ZrO ₂ film. These ultrashort devices exhibit excellent switching characteristics, such as subthreshold swing amplitudes of about 65mV/dec, and switching current ratios of about 10 ⁶ . Simulation results show that the effective channel length is about 3.9 nm in the off state and about 1 nm in the on state. (Science DOI: 10.1126/science.aah4698)

Therefore, how to provide a new NAND flash memory and a method for making the same, so as to take advantage of the advantages of two-dimensional semiconductor materials and carbon nanotubes, further improve the performance of the memory, and reduce the difficulty of the process, has become an urgent problem for those skilled in the art. an important technical issue.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a gate-last NAND-gate flash memory and a manufacturing method thereof, which are used to solve the problem that the NAND flash memory in the prior art is large in size and complex in structure , the problem of high technological difficulty.

In order to achieve the above-mentioned purpose and other related purposes, the present invention provides a gate-last non-junction NAND flash memory, comprising:

substrate;

an insulating layer on the substrate;

A channel layer, located on the insulating layer, adopts a two-dimensional semiconductor material;

A carbon nanotube grid array, suspended above the channel layer, includes a plurality of discrete carbon nanotubes, and the carbon nanotubes are used as gate electrodes of transistors in the memory;

A gate trapping structure includes a tunnel layer, a charge trapping layer and a blocking layer; wherein, the tunnel layer is located on the channel layer, the blocking layer surrounds the outer side of the carbon nanotube, and the charge trapping layer includes a surrounding a first portion of the outer side of the barrier layer and a second portion located above the tunnel layer and in contact with the first portion;

a protective layer covering the gate trapping structure;

The source contact electrode and the drain contact electrode are respectively located at both ends of the carbon nanotube grid array, and are respectively connected to the channel layer.

Optionally, it also includes a plurality of gate contact electrodes respectively leading out the carbon nanotubes.

Optionally, the carbon nanotubes are metallic carbon nanotubes.

Optionally, the diameter of the carbon nanotube is 0.75-3 nm, and the length is 100 nm-50 μm.

Optionally, the memory includes a plurality of serial lines, and each serial line includes a memory cell string and a junctionless switching transistor respectively connected to both ends of the memory cell string; the memory cell string includes a plurality of memory cells connected in series. A unit transistor; wherein the carbon nanotube grid array corresponds to the series, and each carbon nanotube in the carbon nanotube grid array is used as the gate electrode of each transistor in the series.

Optionally, the junctionless switching transistors connected to both ends of the memory cell string are a string selection transistor and a ground selection transistor, respectively.

Optionally, in the carbon nanotube grid array, each carbon nanotube is arranged in parallel in one horizontal plane.

Optionally, the two-dimensional semiconductor material is selected from any one of MoS ₂ , WS ₂ , ReS ₂ and SnO.

Optionally, the material of the charge trapping layer includes at least one of nitride and hafnium oxide, and the materials of the blocking layer and the tunnel layer are both high-K dielectrics with a dielectric constant greater than 3.9.

The present invention also provides a method for manufacturing a gate-last NAND-gate flash memory, comprising the following steps:

A substrate is provided, and an insulating layer, a two-dimensional semiconductor material channel layer and a tunnel layer are sequentially formed on the substrate from bottom to top;

forming a sacrificial layer on the tunnel layer;

forming a carbon nanotube grid array on the sacrificial layer; the carbon nanotube grid array includes several discrete carbon nanotubes, and the carbon nanotubes are used as gate electrodes of transistors in the memory;

performing wet etching on the sacrificial layer, so that the carbon nanotube grid array is suspended, and retaining part of the sacrificial layer at both ends of the carbon nanotube in the axial direction as a support layer;

forming a barrier layer surrounding the outer sides of the carbon nanotubes;

forming a charge trapping layer; the charge trapping layer includes a first portion surrounding the outer side of the blocking layer and a second portion overlying the tunnel layer and in contact with the first portion;

forming a protective layer covering the charge trapping layer;

A source contact electrode and a drain contact electrode respectively located at both ends of the carbon nanotube grid array and connected to the channel layer are formed, and a gate contact electrode respectively leading out each carbon nanotube is formed.

Optionally, the carbon nanotube grid array is formed on the sacrificial layer by chemical vapor deposition, wherein the material of the sacrificial layer includes a carbon nanotube growth catalyst material.

Optionally, the carbon nanotube growth catalyst material includes one or more of Ni, Ag, Fe, and Co.

Optionally, the method for forming the source contact electrode and the drain contact electrode includes the steps of: forming a through hole penetrating the protective layer, the charge trapping layer and the tunnel layer, and filling the through hole with a conductive material.

Optionally, the method for forming the gate contact electrode includes the steps of: forming a through hole penetrating the protective layer, the charge trapping layer and the blocking layer, and filling the through hole with a conductive material.

As mentioned above, the gate-last junctionless NAND flash memory and the manufacturing method thereof of the present invention have the following beneficial effects: the gate-back junctionless NAND flash memory of the present invention adopts a metallic carbon nanotube grid The transistor is used as the gate electrode of the memory cell transistor, which significantly reduces the gate size and is conducive to improving the density of the memory cell; the gate-back NAND flash memory of the present invention also adopts the gate charge trapping method, and uses a two-dimensional semiconductor The material channel replaces the traditional silicon-doped channel, making it easier for the carbon nanotube gate to control the channel current; and due to the use of the horizontal channel form, compared with the existing vertical channel type memory, the present invention has The memory structure is simpler. The manufacturing method of the gate-last non-junction NAND flash memory of the present invention adopts the gate-last process, that is, firstly fabricating a two-dimensional semiconductor material channel layer, and then fabricating a carbon nanotube grid array, so as to obtain a barrier surrounding the carbon nanotube grid. layer and charge trapping layer can further improve the gate charge trapping capability.

Description of drawings

FIG. 1 is a schematic diagram showing the structure of the gate-last junctionless NAND flash memory of the present invention.

FIG. 2 is a schematic diagram showing that an insulating layer, a two-dimensional semiconductor material channel layer and a tunnel layer are sequentially formed on the substrate from bottom to top in the method for fabricating the gate-last junctionless NAND flash memory according to the present invention.

FIG. 3 is a schematic diagram of forming a sacrificial layer on the tunnel layer according to the method for fabricating the gate-last junctionless NAND flash memory of the present invention.

FIG. 4 is a schematic diagram of forming a carbon nanotube grid array on the sacrificial layer by the method for fabricating the gate-last junctionless NAND flash memory of the present invention.

FIG. 5 is a schematic diagram illustrating wet etching of the sacrificial layer by the method for fabricating the gate-last junctionless NAND flash memory according to the present invention.

FIG. 6 is a schematic diagram of forming a barrier layer surrounding the outer side surface of the carbon nanotube by the method for fabricating the gate-last junctionless NAND flash memory according to the present invention.

FIG. 7 is a schematic diagram illustrating the formation of a charge trapping layer in a method for fabricating a gate-last junctionless NAND flash memory according to the present invention.

FIG. 8 is a schematic diagram of forming a protective layer covering the gate charge trapping layer by the method for fabricating the gate-last junctionless NAND flash memory according to the present invention.

9 is a schematic diagram illustrating the formation of a source contact electrode and a drain contact electrode in a method for fabricating a gate-last junctionless NAND flash memory according to the present invention.

Component label description

1 Substrate

2 insulating layers

3 channel layers

4 Carbon Nanotubes

5 Tunnel layer

6 Charge trapping layer

7 Barrier

8 protective layers

9 Source Contact Electrode

10 Drain Contact Electrode

11 Charge

12 sacrificial layers

13 Support layers

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1-9. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

Example 1

The present invention provides a gate-last non-junction NAND flash memory, please refer to FIG. 1 , which is a schematic structural diagram of the memory, including:

substrate 1;

an insulating layer 2, located on the substrate 1;

The channel layer 3 is located on the insulating layer 2 and adopts a two-dimensional semiconductor material;

The carbon nanotube grid array, suspended above the channel layer 3, includes a plurality of discrete carbon nanotubes 4, and the carbon nanotubes 4 are used as gate electrodes of transistors in the memory;

The gate trapping structure includes a tunnel layer 5, a charge trapping layer 6 and a blocking layer 7; wherein, the tunnel layer 5 is located on the channel layer 3, and the blocking layer 7 surrounds the outer side of the carbon nanotube 4, The charge trapping layer 6 includes a first portion surrounding the outer side of the blocking layer 7 and a second portion located above the tunnel layer 5 and in contact with the first portion;

a protective layer 8, covering the gate trapping structure;

The source contact electrode 9 and the drain contact electrode 10 are respectively located at both ends of the carbon nanotube grid array, and are respectively connected to the channel layer 3 .

Specifically, the gate-last junctionless NAND flash memory further includes a plurality of gate contact electrodes respectively leading out the carbon nanotubes 4 . As an example, in the application process, a voltage V _ss is applied to the source contact electrode 9 , a positive voltage V _dd is applied to the drain contact electrode 10 , and a voltage V _g1 , V _g2 , . . . , is applied to the gate contact electrode. V _gn , V _g(n+1) . Among them, n is the number, representing the nth carbon nanotube.

As an example, the substrate 1 includes, but is not limited to, a suitable semiconductor substrate such as silicon, germanium, and silicon germanium, and the insulating layer 2 includes, but is not limited to, a suitable insulating material such as silicon oxide. The channel layer 3 is made of a two-dimensional semiconductor material, and its thickness is 1-10 atomic layers. The two-dimensional semiconductor material is selected from any one of MoS ₂ , WS ₂ , ReS ₂ and SnO. In this embodiment, MoS ₂ is preferably used. Since the channel layer 3 is in the form of a horizontal channel, the memory structure is simpler.

As an example, the memory includes a plurality of serials, and each serial includes a memory cell string and a junctionless switching transistor connected to both ends of the memory cell string respectively; the memory cell string includes a plurality of memory cells connected in series A transistor; wherein the carbon nanotube grid array corresponds to the series, and each carbon nanotube in the carbon nanotube grid array is used as the gate electrode of each transistor in the series. In this embodiment, the switching transistors and the memory cell transistors use carbon nanotube gates, and the gate dielectric layers use the gate trapping structure.

As an example, the junctionless switching transistors connected to both ends of the memory cell strings are string selection transistors and ground selection transistors, respectively. The number of the string selection transistors may be one or more, the number of the ground selection transistors may be one or more, and the number of memory cell transistors in the memory cell string may be set as required, such as 24, 32 1, 48, or even more.

In this embodiment, each series corresponds to one channel, that is, each memory cell transistor and switch transistor in one series share one channel layer 3 . For different strings, the channel layers are isolated from each other, which can be achieved by patterning the channel layers when they are formed, and depositing insulating material between adjacent channel layers.

In this embodiment, in the carbon nanotube grid array, the carbon nanotubes 4 are arranged in parallel on a horizontal plane above the channel layer 3 , so that in a series, the transistors are arranged in sequence from left to right. Of course, in other embodiments, the arrangement form of the carbon nanotubes in the carbon nanotube grid array can be adjusted as required, and the protection scope of the present invention should not be unduly limited here.

Specifically, the carbon nanotubes 4 are metallic carbon nanotubes. The diameter of the carbon nanotube 4 is 0.75-3 nm, and the length is 100 nm-50 μm. Due to the small diameter of the carbon nanotubes 4, it is beneficial to reduce the gate width and increase the density of memory cells.

Specifically, since in the gate trapping structure, the blocking layer and the charge trapping layer both surround the carbon nanotube gate, a stronger gate charge trapping capability can be obtained. As an example, the material of the charge trapping layer 6 includes at least one of nitride and hafnium oxide, and the materials of the blocking layer and the tunnel layer are both high-K dielectrics with a dielectric constant greater than 3.9, such as zirconia, Silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, etc.

The back-gate junctionless NAND flash memory of the present invention adopts a metallic carbon nanotube grid array, and uses carbon nanotubes as the gate electrode of the memory cell transistor, which significantly reduces the gate size and is beneficial to improve the memory cell density; the present invention The gate-last junctionless NAND flash memory also adopts the gate charge trapping method, and replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, which makes the control of the channel current by the carbon nanotube gate more efficient. Easy; the blocking layer and the charge trapping layer surround the carbon nanotube gate, making the gate charge trapping ability stronger. And because the horizontal channel form is adopted, the memory structure of the present invention is simpler compared to the existing vertical channel memory.

Embodiment 2

The present invention also provides a method for manufacturing a gate-last NAND-gate flash memory, comprising the following steps:

Referring first to FIG. 2 , a substrate 1 is provided, and an insulating layer 2 , a two-dimensional semiconductor material channel layer 3 and a tunnel layer 5 are sequentially formed on the substrate 1 from bottom to top.

Specifically, the substrate 1 includes, but is not limited to, a suitable semiconductor substrate such as silicon, germanium, and silicon germanium, and the insulating layer 2 includes, but is not limited to, a suitable insulating material such as silicon oxide. For example, the insulating layer can be formed by growing an oxide layer on a silicon substrate.

The channel layer 3 is made of two-dimensional semiconductor material, and its thickness is 1-10 atomic layers. As an example, the two-dimensional semiconductor material is selected from any one of MoS ₂ , WS ₂ , ReS ₂ and SnO. In this embodiment, MoS ₂ is preferably used. The method of forming the channel layer 3 can be chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD) and other deposition methods, or other suitable processes .

The material of the tunnel layer 5 is a high-K dielectric with a dielectric constant greater than 3.9, such as zirconium oxide, silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, and the like. The method for forming the channel layer 3 and the tunnel layer 5 can be a deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or the like, or other suitable processes.

3 and 4 , a sacrificial layer 12 is formed on the tunnel layer 5 , and a carbon nanotube grid array is formed on the sacrificial layer 12 ; the carbon nanotube grid array includes a plurality of discrete carbon nanotubes Tube 4, the carbon nanotube serves as the gate electrode of the transistor in the memory.

Here, the sacrificial layer 12 means that it can be removed by wet etching.

As an example, the carbon nanotube grid array is formed on the sacrificial layer 12 by chemical vapor deposition, wherein the material of the sacrificial layer 12 includes a carbon nanotube growth catalyst material. For example, the carbon nanotube growth catalyst material includes, but is not limited to, one or more of Ni, Ag, Fe, and Co.

In this embodiment, in a protective atmosphere, carbon nanotubes are used to grow the catalyst material, and a carbon source is passed into the reaction chamber to form the carbon nanotube grid array by chemical vapor deposition. The protective atmosphere includes one or more of N ₂ , H ₂ , and Ar, and the carbon source includes, but is not limited to, methane, acetylene and other carbon-containing gases.

Referring to FIG. 5 again, the sacrificial layer is subjected to 12 lines of wet etching, so that the carbon nanotube grid array is suspended, and part of the sacrificial layer at the two axial ends of the carbon nanotubes 4 is reserved as the support layer 13 . In order to show the suspended state of the carbon nanotubes, the support layer 13 is shown in a dotted frame in FIG. 5 .

Referring to FIG. 6 again, a barrier layer 7 surrounding the outer side of the carbon nanotubes 4 is formed.

Specifically, the barrier layer 7 uses a high-K dielectric with a dielectric constant greater than 3.9, such as zirconia, silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, and the like. The method of forming the barrier layer 7 can be chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD) and other deposition methods, or other suitable processes. In the process of forming the barrier layer 7, some high-K dielectrics may also be deposited on the surface of the tunnel layer 5, but since the tunnel layer 5 also uses a high-K dielectric, no adverse effects will be produced.

Referring to FIG. 7 again, a charge trapping layer 6 is formed; the charge trapping layer 6 includes a first portion surrounding the outer side of the blocking layer 7 and a second portion located above the tunnel layer 5 and in contact with the first portion .

Specifically, the material of the charge trapping layer 6 includes at least one of nitride and hafnium oxide, and the method for forming the charge trapping layer 6 may be chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic Deposition methods such as compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable processes.

Then, referring to FIG. 8 , a protective layer 8 covering the charge trapping layer 6 is formed.

Specifically, the protective layer 8 is made of silicon oxide or other insulating materials.

Finally, referring to FIG. 9 , a source contact electrode 9 and a drain contact electrode 10 respectively located at both ends of the carbon nanotube grid array and connected to the channel layer 3 are formed, and a gate contact for leading out each carbon nanotube 4 is formed. electrode.

As an example, the method for forming the source contact electrode 9 and the drain contact electrode 10 includes the steps of: forming through holes penetrating the protective layer 8 , the charge trapping layer 6 and the tunnel layer 5 at corresponding positions, and forming a through hole in the through hole Fill with conductive material. The method for forming the gate contact electrode includes the steps of: forming through holes through the protective layer 8 , the charge trapping layer 6 and the blocking layer 7 at corresponding positions, and filling the through holes with a conductive material.

The manufacturing method of the gate-last non-junction NAND flash memory of the present invention adopts the gate-last process, that is, firstly fabricating a two-dimensional semiconductor material channel layer, and then fabricating a carbon nanotube grid array, so as to obtain a barrier surrounding the carbon nanotube grid. layer and charge trapping layer, making the gate charge trapping ability stronger.

To sum up, the back-gate junctionless NAND flash memory of the present invention adopts a metallic carbon nanotube grid array, and uses carbon nanotubes as the gate electrode of the memory cell transistor, which significantly reduces the gate size and is conducive to improving the storage capacity. Cell density; the gate-back NAND-gate flash memory of the present invention also adopts the gate charge trapping method, and replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, so that the carbon nanotube gate is opposite to the channel. The control of the current is easier; and the memory structure of the present invention is simpler compared with the existing vertical channel type memory due to the use of the horizontal channel form. The manufacturing method of the gate-last non-junction NAND flash memory of the present invention adopts a gate-last process, that is, firstly fabricating a two-dimensional semiconductor material channel layer, and then fabricating a carbon nanotube grid array, so as to obtain a barrier surrounding the carbon nanotube grid. layer and charge trapping layer can further improve the gate charge trapping capability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications or changes to the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (14)

1. a back gate non-junction NAND gate flash memory, is characterized in that, comprises: substrate; an insulating layer on the substrate; A channel layer, located on the insulating layer, adopts a two-dimensional semiconductor material; A carbon nanotube grid array, suspended above the channel layer, includes a plurality of discrete carbon nanotubes, and the carbon nanotubes are used as gate electrodes of transistors in the memory; A gate trapping structure includes a tunnel layer, a charge trapping layer and a blocking layer; wherein, the tunnel layer is located on the channel layer, the blocking layer surrounds the outer side of the carbon nanotube, and the charge trapping layer includes a surrounding a first portion of the outer side of the barrier layer and a second portion located above the tunnel layer and in contact with the first portion; a protective layer covering the gate trapping structure; The source contact electrode and the drain contact electrode are respectively located at both ends of the carbon nanotube grid array, and are respectively connected to the channel layer. 2 . The gate-last junctionless NAND flash memory according to claim 1 , further comprising a plurality of gate contact electrodes respectively leading out the carbon nanotubes. 3 . 3 . The gate-last junctionless NAND flash memory according to claim 1 , wherein the carbon nanotubes are metallic carbon nanotubes. 4 . 4 . The gate-last junctionless NAND flash memory according to claim 1 , wherein the carbon nanotube has a diameter of 0.75-3 nm and a length of 100 nm-50 μm. 5 . 5. The back-gate junctionless NAND flash memory according to claim 1, wherein the memory comprises a plurality of serial lines, and each serial line comprises a memory cell string and is respectively connected to the memory cell Junctionless switching transistors at both ends of the string; the memory cell string includes a plurality of memory cell transistors connected in series; wherein, the carbon nanotube grid array corresponds to the series, and each carbon nanotube grid in the carbon nanotube grid array corresponds to The tubes serve as gate electrodes of the transistors in the series, respectively. 6 . The back-gate junctionless NAND flash memory according to claim 5 , wherein the junctionless switching transistors connected to both ends of the memory cell strings are string selection transistors and ground selection transistors, respectively. 7 . 7 . The gate-last junctionless NAND flash memory according to claim 1 , wherein in the carbon nanotube grid array, each carbon nanotube is arranged in parallel in a horizontal plane. 8 . 8 . The gate-last junctionless NAND flash memory according to claim 1 , wherein the two-dimensional semiconductor material is selected from any one of MoS ₂ , WS ₂ , ReS ₂ and SnO. 9 . 9 . The gate-last junctionless NAND flash memory according to claim 1 , wherein the material of the charge trapping layer comprises at least one of nitride and hafnium oxide, the blocking layer and the tunnel The materials of the layers are all high-K dielectrics with a dielectric constant greater than 3.9. 10. A method for making a back gate junctionless NAND flash memory, comprising the steps of: A substrate is provided, and an insulating layer, a two-dimensional semiconductor material channel layer and a tunnel layer are sequentially formed on the substrate from bottom to top; forming a sacrificial layer on the tunnel layer; forming a carbon nanotube grid array on the sacrificial layer; the carbon nanotube grid array includes several discrete carbon nanotubes, and the carbon nanotubes are used as gate electrodes of transistors in the memory; performing wet etching on the sacrificial layer, so that the carbon nanotube grid array is suspended, and a part of the sacrificial layer located at the axial ends of the carbon nanotubes is reserved as a support layer; forming a barrier layer surrounding the outer sides of the carbon nanotubes; forming a charge trapping layer; the charge trapping layer includes a first portion surrounding the outer side of the blocking layer and a second portion overlying the tunnel layer and in contact with the first portion; forming a protective layer covering the charge trapping layer; A source contact electrode and a drain contact electrode respectively located at both ends of the carbon nanotube grid array and connected to the channel layer are formed, and a gate contact electrode respectively leading out each carbon nanotube is formed. 11 . The method for manufacturing a gate-last junctionless NAND flash memory according to claim 10 , wherein the carbon nanotube grid array is formed on the sacrificial layer by chemical vapor deposition, wherein the The material of the sacrificial layer includes carbon nanotube growth catalyst material. 12 . The method for manufacturing a gate-last junctionless NAND flash memory according to claim 11 , wherein the carbon nanotube growth catalyst material comprises one or more of Ni, Ag, Fe, and Co. 13 . 13. The method for fabricating a gate-last junctionless NAND flash memory according to claim 10, wherein the method for forming the source contact electrode and the drain contact electrode comprises the steps of: forming a pass through the protective layer, charge trapping The through holes of the layer and the tunnel layer are filled with conductive material. 14. The method for fabricating a gate-last junctionless NAND flash memory according to claim 10, wherein the method for forming the gate contact electrode comprises the step of: forming through the protective layer, the charge trapping layer and the blocking layer through holes, and the through holes are filled with conductive material.

Images