CN108305648B - DDR4 standard high-speed receiver circuit - Google Patents
DDR4 standard high-speed receiver circuit Download PDFInfo
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- CN108305648B CN108305648B CN201810405812.2A CN201810405812A CN108305648B CN 108305648 B CN108305648 B CN 108305648B CN 201810405812 A CN201810405812 A CN 201810405812A CN 108305648 B CN108305648 B CN 108305648B
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- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 title claims abstract description 22
- 230000005540 biological transmission Effects 0.000 abstract description 9
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- 230000008859 change Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45026—One or more current sources are added to the amplifying transistors in the differential amplifier
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses an input receiver circuit of DDR4 standard, which comprises a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN1, a seventh transistor MN2, an eighth transistor MN3, a ninth transistor MN4, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein MN4 and MP5 form a duty ratio regulating circuit for improving the output duty ratio. The DDR4 standard high-speed receiver circuit has the advantages of simple structure, high transmission bandwidth, small transmission delay and the like.
Description
Technical Field
The present invention relates to integrated circuit design technology, and more particularly, to a DDR4 standard high speed receiver circuit.
Background
The bandwidth and interface speed of high density dynamic memory (DRAM) buses are important metrics for measuring system performance, and industry is continually pushing the boundaries of system design constraints to achieve higher memory interface data transfer rates. DDR4 SDRAM has been greatly improved in capacity, rate and compatibility over the previous DDR3 SDRAM, and has been widely used in many fields, but the design of DDR4 receiver circuits still has many problems, such as: due to the difference of level standards and the improvement of transmission rate, the traditional DDR3 standard receiver circuit structure is not suitable for the design of a DDR4 standard receiver; the DDR4 standard receiver designed by others has a complex circuit structure, uses a multi-stage differential amplifier to amplify an input signal, needs to be provided with an additional bias voltage generating circuit, has the defects of large layout area, large delay and high power consumption, and has larger influence on the duty ratio of an output signal due to process deviation, temperature change and voltage fluctuation.
Disclosure of Invention
The invention aims to provide a DDR4 standard high-speed receiver circuit which has a simple structure, high transmission bandwidth and small transmission delay.
The technical solution for realizing the purpose of the invention is as follows: an input receiver circuit of DDR4 standard comprises a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN1, a seventh transistor MN2, an eighth transistor MN3, a ninth transistor MN4, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein the grid electrode of the first transistor MP1 is connected with an enabling control IE end, the drain electrode of the first transistor MP3 is connected with the drain electrode of the sixth transistor MN1, and the source electrode of the first transistor MP1 is connected with a power supply voltage VDD; the grid electrode of the second transistor MP2 is connected with the enabling control IE end and the input end of the fourth inverter, the drain electrode of the second transistor MP4 is connected with the drain electrode of the seventh transistor MN2 and the input end of the first inverter, and the source electrode of the second transistor MP2 is connected with the power supply voltage VDD; after the grid electrode and the drain electrode of the third transistor MP3 are short-circuited, the drain electrodes of the first transistor MP1 and the seventh transistor MN2 are connected, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fourth transistor MP4 is connected with the grid electrode of the third transistor MP3, the drain electrode is connected with the drain electrodes of the second transistor MP2 and the seventh transistor MN2 and the input end of the first inverter, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fifth transistor MP5 is connected with the output end of the fourth inverter, the drain electrode of the fifth transistor MP5 is connected with the drain electrode of the ninth transistor MN4, and the source electrode of the fifth transistor MP5 is connected with the power supply voltage VDD; the grid electrode of the sixth transistor MN1 is connected with the INN input, the drain electrode of the sixth transistor MN1 is connected with the drain electrodes of the first transistor MP1 and the third transistor MP3, and the source electrode of the sixth transistor MN1 is connected with the source electrode of the seventh transistor MN2 and the drain electrode of the eighth transistor MN 3; the gate of the seventh transistor MN2 is connected with the INP input, the drain is connected with the drains of the second transistor MP2, the fourth transistor MP4 and the input end of the first inverter, and the source is connected with the source of the sixth transistor MN1 and the drain of the eighth transistor MN 3; the grid electrode of the eighth transistor MN3 is connected with the IE port, the drain electrode of the eighth transistor MN3 is connected with the source electrodes of the sixth transistor MN1 and the seventh transistor MN2, and the source electrodes are grounded; the gate of the ninth transistor MN4 is connected to the first director input, the drain is connected to the drain of the fifth transistor MP5, the source is connected to the second inverter output and the third inverter input, and the first inverter output is connected to the second inverter input.
Compared with the prior art, the invention has the remarkable advantages that: 1) The DDR4 circuit has a simple structure, and reduces the number of elements and the area of a chip; 2) The pair of differential transistors N-tube in the differential amplifier adopts the IO power domain thick gate transistor, the P-tube adopts the inner core low voltage domain thin gate transistor, the IO power domain thick gate differential N-tube ensures that the circuit can normally work in a high voltage domain (IO domain), and the inner core low voltage domain thin gate transistor can improve the transmission bandwidth of the circuit and reduce the transmission delay; 3) According to the invention, the duty ratio improving circuit is added between the signal lines OUT1 and OUT3, so that the stable duty ratio of the whole circuit can be still maintained under the condition that the technological parameters, the ambient temperature and the power supply voltage are changed, and the reading performance of the memory is improved.
Drawings
Fig. 1 is a schematic diagram of the structure of the DDR4 standard high-speed receiver circuit of the present invention.
Detailed Description
The present invention will be further described with reference to the drawings and the specific embodiments.
The invention provides a DDR4 standard high-speed receiver circuit, which comprises four parts, namely a differential amplifier, a buffer, a duty ratio regulating circuit and an output inverter, wherein:
(1) The differential amplifier comprises two groups of mirror current sources consisting of thin gate P-type transistors of four kernel power domains, a basic differential pair (coupling pair) consisting of thick gate N-type transistors MN1 and MN2 of two I/O power domains, and a tail current source consisting of an N-type transistor MN3, which is used for providing bias current for the differential pair and inhibiting the influence of the change of input common mode level on the operation of MN1 and MN2 and the output level.
(2) A buffer: the two-phase inverter is composed of two groups of phase inverters and plays a role in buffering and time delay.
(3) Duty cycle adjustment circuit: consists of MN4 and MP5, and is used for improving the output duty ratio.
(4) And the output inverter is used for amplifying the high-potential signal output by the circuit and ensuring that the output circuit has enough driving.
The specific circuit structure of the DDR4 standard high-speed receiver circuit is shown in fig. 1, and includes a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN1, a seventh transistor MN2, an eighth transistor MN3, a ninth transistor MN4, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein the gate of the first transistor MP1 is connected to an enable control IE end, the drain is connected to the drain of the third transistor MP3, the sixth transistor MN1, and the source is connected to the power supply voltage VDD; the grid electrode of the second transistor MP2 is connected with the enabling control IE end and the input end of the fourth inverter, the drain electrode of the second transistor MP4 is connected with the drain electrode of the seventh transistor MN2 and the input end of the first inverter, and the source electrode of the second transistor MP2 is connected with the power supply voltage VDD; after the grid electrode and the drain electrode of the third transistor MP3 are short-circuited, the drain electrodes of the first transistor MP1 and the seventh transistor MN2 are connected, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fourth transistor MP4 is connected with the grid electrode of the third transistor MP3, the drain electrode is connected with the drain electrodes of the second transistor MP2 and the seventh transistor MN2 and the input end of the first inverter, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fifth transistor MP5 is connected with the output end of the fourth inverter, the drain electrode of the fifth transistor MP5 is connected with the drain electrode of the ninth transistor MN4, and the source electrode of the fifth transistor MP5 is connected with the power supply voltage VDD; the grid electrode of the sixth transistor MN1 is connected with the INN input, the drain electrode of the sixth transistor MN1 is connected with the drain electrodes of the first transistor MP1 and the third transistor MP3, and the source electrode of the sixth transistor MN1 is connected with the source electrode of the seventh transistor MN2 and the drain electrode of the eighth transistor MN 3; the gate of the seventh transistor MN2 is connected with the INP input, the drain is connected with the drains of the second transistor MP2, the fourth transistor MP4 and the input end of the first inverter, and the source is connected with the source of the sixth transistor MN1 and the drain of the eighth transistor MN 3; the grid electrode of the eighth transistor MN3 is connected with the IE port, the drain electrode of the eighth transistor MN3 is connected with the source electrodes of the sixth transistor MN1 and the seventh transistor MN2, and the source electrodes are grounded; the gate of the ninth transistor MN4 is connected to the first director input, the drain is connected to the drain of the fifth transistor MP5, the source is connected to the second inverter output and the third inverter input, and the first inverter output is connected to the second inverter input. According to the invention, the MP4 gate is connected with the OU1 signal line, the source is connected with the output of the second-stage inverter, namely the OUT3 signal line, a duty ratio improving circuit consisting of MN4 and MP5 is added between the signal lines OUT1 and OUT3, and after the signal OUT1 is amplified in a differential mode, the signal is divided into two paths: the first path drives the OUT3 point through the two-stage inverter, the second path directly drives the N pipe which is pulled up, the level of the OUT3 point is pulled up in advance by the time delay of the two-stage inverter, and the function of improving the duty ratio is achieved; meanwhile, the lifting amplitude of the duty ratio is in direct proportion to the time delay of the two-stage inverters, and if the capacity of duty ratio adjustment is required to be increased, the number of stages of the inverters between OUT1 and OUT3 can be increased.
The first transistor MP1, the second transistor MP2, the third transistor MP3, the fourth transistor MP4, and the fifth transistor MP5 are P-type transistors. The first transistor MP1, the second transistor MP2, the third transistor MP3 and the fourth transistor MP4 are thin gate P-type transistors in the power domain of the core, which can improve the transmission bandwidth of the circuit and reduce the transmission delay. The sixth transistor MN1, the seventh transistor MN2, the eighth transistor MN3, and the ninth transistor MN4 are N-type transistors. The sixth transistor MN1 and the seventh transistor MN2 are thick gate N-type transistors in the I/O power domain, so that the circuit can be ensured to normally operate in a high voltage domain (IO domain). The first inverter, the second inverter and the third inverter are CMOS inverters. The fourth inverter is a TTL NOT circuit.
The working principle of the invention is as follows:
inn=vref, providing a reference voltage to INP, ensuring that MN1 is always in an on state;
when ie=0, MP1 and MP2 are turned on, MP5 is turned off, MN3 is turned off, the circuit cannot work normally, no matter INP is connected with any signal, no influence is caused to the output terminal OUT, and OUT is constantly 0;
when ie=1, MP1, MP2 are turned off, MN3 is turned on, and the circuit is in the working state;
when inp=0, MN2 is turned off, MP3 is turned on, MP4 is turned off, MN3 is turned off, signal line OUT 1=0, and output terminal out=0 through two groups of inverters;
when inp=1, MN2 is turned on, MP3 is turned off, MP4 is turned on, MN3 is turned on, signal line OUT 1=1, and output terminal out=1 through two sets of inverters.
Claims (7)
1. The DDR4 standard high-speed receiver circuit is characterized by comprising a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN1, a seventh transistor MN2, an eighth transistor MN3, a ninth transistor MN4, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein the grid electrode of the first transistor MP1 is connected with an enabling control IE end, the drain electrode of the first transistor MP3 and the drain electrode of the sixth transistor MN1 are connected with a power supply voltage VDD; the grid electrode of the second transistor MP2 is connected with the enabling control IE end and the input end of the fourth inverter, the drain electrode of the second transistor MP4 is connected with the drain electrode of the seventh transistor MN2 and the input end of the first inverter, and the source electrode of the second transistor MP2 is connected with the power supply voltage VDD; after the grid electrode and the drain electrode of the third transistor MP3 are short-circuited, the drain electrodes of the first transistor MP1 and the seventh transistor MN2 are connected, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fourth transistor MP4 is connected with the grid electrode of the third transistor MP3, the drain electrode is connected with the drain electrodes of the second transistor MP2 and the seventh transistor MN2 and the input end of the first inverter, and the source electrode is connected with the power supply voltage VDD; the grid electrode of the fifth transistor MP5 is connected with the output end of the fourth inverter, the drain electrode of the fifth transistor MP5 is connected with the drain electrode of the ninth transistor MN4, and the source electrode of the fifth transistor MP5 is connected with the power supply voltage VDD; the grid electrode of the sixth transistor MN1 is connected with the INN input, the drain electrode of the sixth transistor MN1 is connected with the drain electrodes of the first transistor MP1 and the third transistor MP3, and the source electrode of the sixth transistor MN1 is connected with the source electrode of the seventh transistor MN2 and the drain electrode of the eighth transistor MN 3; the gate of the seventh transistor MN2 is connected with the INP input, the drain is connected with the drains of the second transistor MP2, the fourth transistor MP4 and the input end of the first inverter, and the source is connected with the source of the sixth transistor MN1 and the drain of the eighth transistor MN 3; the grid electrode of the eighth transistor MN3 is connected with the IE port, the drain electrode of the eighth transistor MN3 is connected with the source electrodes of the sixth transistor MN1 and the seventh transistor MN2, and the source electrodes are grounded; the gate of the ninth transistor MN4 is connected to the first director input, the drain is connected to the drain of the fifth transistor MP5, the source is connected to the second inverter output and the third inverter input, and the first inverter output is connected to the second inverter input.
2. The DDR4 standard high speed receiver circuit of claim 1, wherein the first transistor MP1, the second transistor MP2, the third transistor MP3, the fourth transistor MP4, and the fifth transistor MP5 are P-type transistors.
3. The DDR4 standard high speed receiver circuit of claim 1, wherein the first transistor MP1, the second transistor MP2, the third transistor MP3, and the fourth transistor MP4 are thin gate P-type transistors of a core power domain.
4. The DDR4 standard high-speed receiver circuit of claim 1, wherein the sixth transistor MN1, seventh transistor MN2, eighth transistor MN3, and ninth transistor MN4 are N-type transistors.
5. The DDR4 standard high speed receiver circuit of claim 1, wherein the sixth transistor MN1 and the seventh transistor MN2 are thick gate N-type transistors of an I/O power domain.
6. The DDR4 standard high speed receiver circuit of claim 1, wherein the first inverter, the second inverter, and the third inverter are CMOS inverters.
7. The DDR4 standard high speed receiver circuit of claim 1, wherein the fourth inverter is a TTL not gate circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810405812.2A CN108305648B (en) | 2018-04-29 | 2018-04-29 | DDR4 standard high-speed receiver circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810405812.2A CN108305648B (en) | 2018-04-29 | 2018-04-29 | DDR4 standard high-speed receiver circuit |
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| CN108305648A CN108305648A (en) | 2018-07-20 |
| CN108305648B true CN108305648B (en) | 2023-12-19 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160683A (en) * | 2016-06-24 | 2016-11-23 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN106209035A (en) * | 2016-07-13 | 2016-12-07 | 电子科技大学 | A kind of two stage comparator |
| CN106653072A (en) * | 2017-02-03 | 2017-05-10 | 苏州大学 | Pseudo device auxiliary sensitive amplifier circuit |
| CN208126877U (en) * | 2018-04-29 | 2018-11-20 | 南京胜跃新材料科技有限公司 | The high-speed receiver circuit of DDR4 standard |
-
2018
- 2018-04-29 CN CN201810405812.2A patent/CN108305648B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160683A (en) * | 2016-06-24 | 2016-11-23 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN106209035A (en) * | 2016-07-13 | 2016-12-07 | 电子科技大学 | A kind of two stage comparator |
| CN106653072A (en) * | 2017-02-03 | 2017-05-10 | 苏州大学 | Pseudo device auxiliary sensitive amplifier circuit |
| CN208126877U (en) * | 2018-04-29 | 2018-11-20 | 南京胜跃新材料科技有限公司 | The high-speed receiver circuit of DDR4 standard |
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| CN108305648A (en) | 2018-07-20 |
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