CN108288649B - A superjunction power MOSFET with two types of carrier conduction - Google Patents
A superjunction power MOSFET with two types of carrier conduction Download PDFInfo
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
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- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
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Abstract
本发明公开了一种超结功率MOSFET，属于半导体功率器件技术领域，其具有第一种导电类型的MOSFET及第二种导电类型的双极结型晶体管，并通过第一种导电类型的MOSFET及受所述MOSFET驱动的第二种导电类型的双极结型晶体管使第一种导电类型和第二种导电类型的载流子分别在所述半导体第一漂移区和所述半导体第二漂移区中流动，同时通过所述半导体少子阻挡区阻挡第二种导电类型的载流子进入所述半导体第一漂移区中，从而避免在所述耐压层中形成电导调制。本发明达到了在超结MOSFET中实现了两种载流子同时参与导电且保证同时不形成电导调制的目的。
The invention discloses a super-junction power MOSFET, which belongs to the technical field of semiconductor power devices. It has a MOSFET of a first conductivity type and a bipolar junction transistor of a second conductivity type. The bipolar junction transistor of the second conductivity type driven by the MOSFET keeps the carriers of the first conductivity type and the second conductivity type in the semiconductor first drift region and the semiconductor second drift region, respectively At the same time, carriers of the second conductivity type are blocked by the semiconductor minority carrier blocking region from entering the semiconductor first drift region, thereby avoiding the formation of conductance modulation in the withstand voltage layer. The present invention achieves the purpose of realizing that two kinds of carriers participate in conduction at the same time in the superjunction MOSFET and ensuring that no conduction modulation is formed at the same time.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a super junction power MOSFET with two conductive carriers.
Background
A super-junction power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is used for improving the Breakdown Voltage (BV) and specific on-resistance (R) in the conventional power MOSFETON,SP) The structure is shown in figure 1. It relates the breakdown voltage to the specific on-resistance from R of the conventional power MOSFETON,SP∝BV2.5Rewritten as RON,SP∝BV1.3Greatly reducing the conductance of the power MOSFETThe on-resistance reduces the area of the chip, and therefore, the on-resistance is widely applied to medium and low power supply equipment. The super-junction power MOSFET is a multi-electron conducting device, only one kind of current carrier participates in conduction when the super-junction power MOSFET is conducted, for example, in an n-type channel device, only electrons participate in conduction, and the electrons flow in an n column of a super-junction structure; meanwhile, the p column in the super junction structure does not contribute to the current conducting capacity of the device, and the effect of the super junction structure is to provide ionized acceptor impurities during forward blocking so as to absorb electric lines emitted by the ionized donor impurities in the n column, thereby improving the breakdown voltage of the device. Therefore, how to further improve the on-current capability of the device by utilizing p-pillar conduction, reduce the specific on-resistance of the device, and reduce the chip area becomes a new research direction.
The super-junction power IGBT (Insulated gate bipolar Transistor) structure proposed based on the above research direction is a practical solution, and the structure thereof is shown in fig. 2, and it utilizes both electrons and holes to conduct current, wherein the electrons and holes participate in conduction in the form of unbalanced carriers, and they form conductivity modulation in the drift region, thereby greatly reducing the specific on-resistance of the device. However, the device must extract both these non-equilibrium electrons and holes when turned off, thus increasing the turn-off time.
In summary, there is no technology in the prior art that can effectively achieve the purpose of achieving the purpose of not forming conductance modulation while two carriers simultaneously participate in conduction in the super junction power MOSFET.
Disclosure of Invention
In view of the defects in the prior art, the present invention aims to provide a super junction power MOSFET, so as to achieve the purpose of simultaneously participating in the conduction of two carriers and ensuring that the conductance modulation is not formed at the same time in the super junction MOSFET.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a super junction power MOSFET is characterized in that a cellular structure of the super junction power MOSFET comprises:
a voltage-withstanding layer which is composed of a semiconductor first drift region having a certain conductivity type and a semiconductor second drift region having a conductivity type opposite to that of the semiconductor first drift region, which are in contact with each other;
a semiconductor substrate region which is opposite to the conductivity type of the semiconductor first drift region and is covered with a conductor serving as a drain electrode on the surface of the semiconductor substrate region;
at least one semiconductor body region which is opposite to the conductivity type of the semiconductor first drift region and is mutually contacted with the voltage-proof layer;
at least one semiconductor source region having the same conductivity type as the semiconductor first drift region and located within the semiconductor body region; meanwhile, a part of the semiconductor source region and a part of the semiconductor body region are connected through a conductor to form a source electrode of the device;
the gate insulating layer is covered on the surfaces of part of the semiconductor source region, part of the semiconductor body region and part of the voltage-resisting layer, and a gate electrode is formed by a semiconductor polycrystalline silicon gate region covered on the surface of the gate insulating layer and a conductor partially covered on the semiconductor polycrystalline silicon gate region, and the semiconductor polycrystalline silicon gate region and the semiconductor first drift region correspond to the same conductive type; a gate structure of the transistor is formed by a part of the semiconductor source region, a part of the semiconductor body region, the gate insulating layer, the semiconductor polycrystalline silicon gate region, the gate electrode and a part of the voltage-resisting layer;
at least one semiconductor buffer region of the same conductivity type as the semiconductor first drift region and in mutual contact with the semiconductor substrate region;
at least one semiconductor minority carrier blocking region of the same conductivity type as the semiconductor first drift region and located outside the semiconductor buffer region or within the semiconductor buffer region;
wherein a portion of the source electrode and the gate structure, the semiconductor first drift region, the semiconductor minority carrier blocking region, the semiconductor substrate region and the drain electrode constitute a MOSFET of the same conductivity type as the semiconductor first drift region; part of the source electrode and the semiconductor body region, the semiconductor second drift region, the semiconductor buffer region, part of the semiconductor substrate region and the drain electrode form a bipolar junction transistor with a conductivity type opposite to that of the semiconductor first drift region.
Further, the conductivity type is N-type or P-type.
Further, the semiconductor material adopted by the super junction power MOSFET includes but is not limited to any one of silicon, gallium arsenide, gallium nitride or silicon carbide.
Further, when the semiconductor minority carrier blocking region is located outside the semiconductor buffer region, the thickness of the semiconductor minority carrier blocking region in the longitudinal direction relative to the semiconductor buffer region is increased.
Further, the doping concentration of the semiconductor minority carrier blocking region is not lower than that of the semiconductor buffer region.
Further, the gate structure is a planar gate structure or a trench gate structure.
Further, the shape of the cell gate structure includes, but is not limited to, any one of a stripe shape, a hexagonal shape, a rectangular shape, or a circular shape.
Further, the arrangement mode of the super junction structure formed by the semiconductor first drift region and the semiconductor second drift region in the voltage-proof layer includes, but is not limited to, any one of a stripe shape, a hexagon shape, a rectangle shape or a circle shape.
Compared with the prior art, the invention has the beneficial effects that:
the invention effectively realizes the purpose that two current carriers participate in conduction simultaneously in the super junction power MOSFET and ensure that the conduction modulation is not formed simultaneously, and particularly, the current carriers of a first conduction type and a second conduction type respectively flow in the first drift region and the second drift region of the semiconductor through the MOSFET grid structure and the bipolar junction transistor driven by the MOSFET, and simultaneously the current carriers of the second conduction type are blocked by the semiconductor minority carrier blocking region to enter the first drift region of the semiconductor, thereby avoiding the formation of the conduction modulation in the voltage-resistant layer; wherein, for the first conductivity type MOSFET, the second conductivity type carriers are minority carriers, and thus the blocking region is referred to as a semiconductor minority carrier blocking region.
Drawings
Fig. 1 is a schematic structural diagram of a conventional super junction power MOSFET;
fig. 2 is a schematic structural diagram of a super junction power IGBT;
fig. 3 is a schematic structural diagram of a super junction power MOSFET corresponding to example 1 of the present invention;
fig. 4 is a schematic structural diagram of a super junction power MOSFET corresponding to example 2 of the present invention;
fig. 5 is a schematic structural diagram of a super junction power MOSFET corresponding to example 3 according to the present invention;
fig. 6 is a schematic structural diagram of a super junction power MOSFET corresponding to example 4 of the present invention;
fig. 7 is a schematic structural diagram of a super junction power MOSFET corresponding to example 5 of the present invention;
fig. 8 is a schematic structural diagram of a super junction power MOSFET corresponding to example 6 according to the present invention.
In the figure: 01. the semiconductor substrate comprises a drain electrode 02, a source electrode 03, a gate electrode 10, a semiconductor source region 11, a semiconductor first drift region 13, a semiconductor buffer region 14, a first semiconductor minority carrier blocking region 15, a second semiconductor minority carrier blocking region 20, a semiconductor body region 21, a semiconductor second drift region 22, a semiconductor substrate region 30, a semiconductor polycrystalline silicon gate region 40 and a gate insulating layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a cell structure corresponding to a super junction power MOSFET. The super junction power MOSFET comprises a cellular structure: the super junction structure comprises a voltage-resistant layer and a second voltage-resistant layer, wherein the voltage-resistant layer is composed of a semiconductor first drift region with a certain conductive type and a semiconductor second drift region with a conductive type opposite to that of the semiconductor first drift region, which are in contact with each other, and the arrangement mode of the super junction structure formed by the semiconductor first drift region and the semiconductor second drift region in the voltage-resistant layer comprises but is not limited to any one of a strip shape, a hexagon shape, a rectangle shape or a circle shape; a semiconductor substrate region which is opposite to the conductivity type of the semiconductor first drift region and is covered with a conductor serving as a drain electrode on the surface of the semiconductor substrate region; at least one semiconductor body region which is opposite to the conductivity type of the semiconductor first drift region and is mutually contacted with the voltage-proof layer; at least one semiconductor source region having the same conductivity type as the semiconductor first drift region and located within the semiconductor body region; meanwhile, a part of the semiconductor source region and a part of the semiconductor body region are connected through a conductor to form a source electrode of the device; the gate insulating layer is covered on the surfaces of part of the semiconductor source region, part of the semiconductor body region and part of the voltage-resisting layer, and a gate electrode is formed by a semiconductor polycrystalline silicon gate region covered on the surface of the gate insulating layer and a conductor partially covered on the semiconductor polycrystalline silicon gate region, and the semiconductor polycrystalline silicon gate region and the semiconductor first drift region correspond to the same conductive type; a gate structure of the transistor is formed by a part of the semiconductor source region, a part of the semiconductor body region, the gate insulating layer, the semiconductor polycrystalline silicon gate region, the gate electrode and a part of the voltage-resisting layer; at least one semiconductor semi-buffer region of the same conductivity type as the semiconductor first drift region and in mutual contact with the semiconductor substrate region; at least one semiconductor minority carrier blocking region of the same conductivity type as the semiconductor first drift region and located outside the semiconductor buffer region or within the semiconductor buffer region;
wherein a portion of the source electrode and the gate structure, the semiconductor first drift region, the semiconductor minority carrier blocking region, the semiconductor substrate region and the drain electrode constitute a MOSFET of the same conductivity type as the semiconductor first drift region; part of the source electrode and the semiconductor body region, the semiconductor second drift region, the semiconductor buffer region, part of the semiconductor substrate region and the drain electrode form a bipolar junction transistor with a conductivity type opposite to that of the semiconductor first drift region.
There are two optional embodiments of the above structure position relationship between the semiconductor minority carrier blocking region and the semiconductor buffer region, in an optional embodiment, the semiconductor minority carrier blocking region has the same conductivity type as the semiconductor first drift region and is located outside the semiconductor buffer region, that is, when the semiconductor buffer region is located below the semiconductor second drift region, the semiconductor minority carrier blocking region is located between the semiconductor first drift region and the semiconductor substrate region and directly contacts with the semiconductor buffer region, and meanwhile, the thickness of the semiconductor minority carrier blocking region is increased relative to the semiconductor buffer region in the longitudinal direction; in another optional embodiment, the semiconductor minority carrier blocking region has the same conductivity type as the semiconductor first drift region and is located in the semiconductor buffer region, that is, the semiconductor minority carrier blocking region is not directly contacted with the voltage-withstanding layer and the semiconductor substrate region; further, when the semiconductor minority carrier blocking region is located outside the semiconductor buffer region, in an alternative embodiment, the doping concentration of the semiconductor minority carrier blocking region is higher than that of the semiconductor buffer region, and in another alternative embodiment, the semiconductor minority carrier blocking region may use the same doping level as that of the semiconductor buffer region instead of being heavily doped, that is, the doping concentration of the semiconductor minority carrier blocking region is the same as that of the semiconductor buffer region, which may also block minority carriers by further increasing the thickness of the semiconductor minority carrier blocking region.
In an optional embodiment, the conductivity type is N-type or P-type, that is, when the conductivity type of the first drift region of the semiconductor is first conductivity type-N-type, the conductivity type of the second drift region of the semiconductor is second conductivity type-P-type, the carriers of the first conductivity type are electrons, and the carriers of the second conductivity type are holes; on the contrary, if the conductivity type of the first drift region of the semiconductor is the first conductivity type-P type, the conductivity type of the second drift region of the semiconductor is the second conductivity type-N type, the carriers of the first conductivity type are holes, and the carriers of the second conductivity type are electrons.
In an alternative embodiment, the semiconductor material used for the super junction power MOSFET includes, but is not limited to, any one of silicon, gallium arsenide, gallium nitride, or silicon carbide.
In an alternative embodiment, the gate structure is a planar gate structure or a trench gate structure.
In an alternative embodiment, the shape of the cell gate structure includes, but is not limited to, any one of a stripe shape, a hexagonal shape, a rectangular shape, or a circular shape.
In an alternative embodiment, the semiconductor substrate region has a doping concentration greater than 1018cm-3。
The above is illustrated below by means of several alternative embodiments:
as example 1 shown in fig. 3, the super junction power MOSFET has a planar gate structure, and its cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the semiconductor polysilicon gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22; at least one semiconductor minority carrier blocking region 14 to block carriers of a second conductivity type from entering the semiconductor first drift region 11 through the semiconductor minority carrier blocking region 14, thereby avoiding the formation of conductance modulation in the voltage-withstanding layer, the semiconductor minority carrier blocking region 14 is in direct contact with the semiconductor buffer region 13, the conductivity type of which is N-type and is located outside the semiconductor buffer region 13, which is the first semiconductor minority carrier blocking region 14, specifically when the semiconductor buffer region 13 is located below the semiconductor second drift region 21, the semiconductor minority carrier blocking region 14 is located between the semiconductor first drift region 11 and the semiconductor substrate region 22, while the boundary of the semiconductor minority carrier blocking region 14 and the semiconductor buffer region 13 is located below the semiconductor second drift region 21 and the thickness of the semiconductor minority carrier blocking region 14 relative to the semiconductor buffer region 13 is increased in the longitudinal direction; preferably, the doping concentration of the semiconductor minority carrier blocking region 14 is higher than that of the semiconductor buffer region 13;
wherein a part of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region 14, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
As example 2 shown in fig. 4, the super junction power MOSFET has a planar gate structure, and its cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the semiconductor polysilicon gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22, the semiconductor first drift region 11 and the semiconductor second drift region 21; the semiconductor buffer region 13 is divided into two parts according to the thickness, wherein the thicker part is positioned below the semiconductor first drift region 11, and the thinner part is positioned below the semiconductor second drift region 21; the thicker part of the semiconductor buffer region 13 is simultaneously used as a semiconductor minority carrier blocking region to block the carriers of the second conductivity type from entering the semiconductor first drift region 11, so that the formation of conductance modulation in the voltage-resisting layer is avoided; preferably, the semiconductor minority carrier blocking region semiconductor buffer region can block minority carriers by further increasing the thickness of the thicker part of the semiconductor minority carrier blocking region of the semiconductor buffer region 13;
wherein a part of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region 14, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
As example 3 shown in fig. 5, the super junction power MOSFET has a planar gate structure, and its cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the semiconductor polysilicon gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22; at least one semiconductor minority carrier blocking region, which is used for blocking carriers of a second conductivity type from entering the semiconductor first drift region 11 through the semiconductor minority carrier blocking region, so as to avoid forming conductivity modulation in the voltage-withstanding layer, wherein the semiconductor minority carrier blocking region is directly contacted with the semiconductor buffer region 13, the conductivity type of the semiconductor minority carrier blocking region is N-type and is located in the semiconductor buffer region 13, which is the second semiconductor minority carrier blocking region 15, namely the semiconductor minority carrier blocking region is not directly contacted with the voltage-withstanding layer and the semiconductor substrate region 22 but is directly buried in the semiconductor buffer region 13;
wherein a portion of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
As example 4 shown in fig. 6, the super junction power MOSFET has a trench-type gate structure whose cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the semiconductor polysilicon gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22; at least one semiconductor minority carrier blocking region 14 to block carriers of a second conductivity type from entering the semiconductor first drift region 11 through the semiconductor minority carrier blocking region 14, thereby avoiding the formation of conductance modulation in the voltage-withstanding layer, the semiconductor minority carrier blocking region 14 is in direct contact with the semiconductor buffer region 13, the conductivity type of which is N-type and is located outside the semiconductor buffer region 13, which is the first semiconductor minority carrier blocking region 14, specifically when the semiconductor buffer region 13 is located below the semiconductor second drift region 21, the semiconductor minority carrier blocking region 14 is located between the semiconductor first drift region 11 and the semiconductor substrate region 22, while the boundary of the semiconductor minority carrier blocking region 14 and the semiconductor buffer region 13 is located below the semiconductor second drift region 21 and the thickness of the semiconductor minority carrier blocking region 14 relative to the semiconductor buffer region 13 is increased in the longitudinal direction; preferably, the doping concentration of the semiconductor minority carrier blocking region 14 is higher than that of the semiconductor buffer region 13;
wherein a portion of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
As example 5 shown in fig. 7, the super junction power MOSFET has a trench-type gate structure whose cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the semiconductor polysilicon gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22, the semiconductor first drift region 11 and the semiconductor second drift region 21; the semiconductor buffer region 13 is divided into two parts according to the thickness, wherein the thicker part is positioned below the semiconductor first drift region 11, and the thinner part is positioned below the semiconductor second drift region 21; the thicker part of the semiconductor buffer region 13 is simultaneously used as a semiconductor minority carrier blocking region to block the carriers of the second conductivity type from entering the semiconductor first drift region 11, so that the formation of conductance modulation in the voltage-resisting layer is avoided; preferably, the semiconductor minority carrier blocking region semiconductor buffer region can block minority carriers by further increasing the thickness of the thicker part of the semiconductor minority carrier blocking region of the semiconductor buffer region 13;
wherein a portion of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
As example 6 shown in fig. 8, the super junction power MOSFET has a trench-type gate structure whose cell structure includes: a voltage-withstanding layer, which is composed of a semiconductor first drift region 11 having a first conductivity type and a semiconductor second drift region 21 having a second conductivity type opposite to the conductivity type of the semiconductor first drift region 11, wherein the first conductivity type is N-type, and the second conductivity type is P-type; a semiconductor substrate region 22, the conductivity type of which is P-type, and the surface of the semiconductor substrate region 22 is covered with a conductor as a drain electrode 01; at least one semiconductor body region 20, the conductivity type of which is P-type and is in contact with the voltage-resistant layer; at least one semiconductor source region 10, the conductive type phase of which is N-type and located in the semiconductor body region 20; meanwhile, a part of the semiconductor source region 10 and a part of the semiconductor body region 20 are connected through a conductor to form a source electrode 02 of the device; a gate insulating layer 40, which is covered on the surfaces of part of the semiconductor source region 10, part of the semiconductor body region 20 and part of the voltage-proof layer, and forms a gate electrode 03 by a semiconductor polysilicon gate region 30 covered on the surface of the gate insulating layer 40 and a conductor partly covered on the semiconductor polysilicon gate region 30, wherein the conductivity type of the gate region 30 is N-type; a gate structure of the transistor is formed by a part of the semiconductor source region 10, a part of the semiconductor body region 20, the gate insulating layer 40, the semiconductor polycrystalline silicon gate region 30, the gate electrode 03 and a part of the voltage-resisting layer; at least one semiconductor buffer region 13, the conductivity type of which is N-type and which is in mutual contact with the semiconductor substrate region 22; at least one semiconductor minority carrier blocking region 15, for blocking the carriers of the second conductivity type from entering the semiconductor first drift region 11 through the semiconductor minority carrier blocking region 15, so as to avoid forming conductivity modulation in the voltage-withstanding layer, wherein the semiconductor minority carrier blocking region 15 is directly contacted with the semiconductor buffer region 13, the conductivity type of the semiconductor minority carrier blocking region is N-type and is located in the semiconductor buffer region 13, which is the second semiconductor minority carrier blocking region 15, that is, the semiconductor minority carrier blocking region is not directly contacted with the voltage-withstanding layer and the semiconductor substrate region but is directly buried in the semiconductor buffer region 13;
wherein a portion of the source electrode 02 and the gate structure, the semiconductor first drift region 11, the semiconductor minority carrier blocking region, the semiconductor substrate region 22 and the drain electrode 01 constitute a MOSFET having a conductivity type of N, such that carriers of the first conductivity type mainly flow in the MOSFET; part of the source electrode 02 and the semiconductor body region 20, the semiconductor second drift region 21, the semiconductor buffer region 13, part of the semiconductor substrate region 22 and the drain electrode 01 constitute a bipolar junction transistor-BJT of P-type conductivity type, so that carriers of the second conductivity type mainly flow in the BJT.
In addition, since the first conductivity type is P-type, the structure and the principle of the super junction power MOSFET corresponding to the second conductivity type being N-type are similar to those of the first conductivity type being N-type, and are not described herein again.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (8)
1. A super junction power MOSFET is characterized in that a cellular structure of the super junction power MOSFET comprises:
a voltage-withstanding layer which is composed of a semiconductor first drift region having a certain conductivity type and a semiconductor second drift region having a conductivity type opposite to that of the semiconductor first drift region, which are in contact with each other;
a semiconductor substrate region which is opposite to the conductivity type of the semiconductor first drift region and is covered with a conductor serving as a drain electrode on the surface of the semiconductor substrate region;
at least one semiconductor body region which is opposite to the conductivity type of the semiconductor first drift region and is mutually contacted with the voltage-proof layer;
at least one semiconductor source region having the same conductivity type as the semiconductor first drift region and located within the semiconductor body region; meanwhile, a part of the semiconductor source region and a part of the semiconductor body region are connected through a conductor to form a source electrode of the device;
the gate insulating layer is covered on the surfaces of part of the semiconductor source region, part of the semiconductor body region and part of the voltage-resisting layer, and a gate electrode is formed by a semiconductor polycrystalline silicon gate region covered on the surface of the gate insulating layer and a conductor partially covered on the semiconductor polycrystalline silicon gate region, and the semiconductor polycrystalline silicon gate region and the semiconductor first drift region correspond to the same conductive type; the gate structure of the MOSFET is formed by a part of the semiconductor source region, a part of the semiconductor body region, the gate insulating layer, the semiconductor polycrystalline silicon gate region, the gate electrode and a part of the voltage-resisting layer;
at least one semiconductor buffer region of the same conductivity type as the semiconductor first drift region and in mutual contact with the semiconductor substrate region;
at least one semiconductor minority carrier blocking region of the same conductivity type as the semiconductor first drift region and located outside the semiconductor buffer region or within the semiconductor buffer region;
wherein a portion of the source electrode and the gate structure, the semiconductor first drift region, the semiconductor minority carrier blocking region, the semiconductor substrate region and the drain electrode constitute a MOSFET of the same conductivity type as the semiconductor first drift region; part of the source electrode and the semiconductor body region, the semiconductor second drift region, the semiconductor buffer region, part of the semiconductor substrate region and the drain electrode form a bipolar junction transistor with a conductivity type opposite to that of the semiconductor first drift region.
2. The super junction power MOSFET of claim 1, wherein: the conductive type is N type or P type.
3. The super junction power MOSFET of claim 1, wherein:
the semiconductor material adopted by the super junction power MOSFET comprises any one of silicon, gallium arsenide, gallium nitride or silicon carbide.
4. The super junction power MOSFET of claim 1, wherein:
when the semiconductor minority carrier blocking region is located outside the semiconductor buffer region, the thickness of the semiconductor minority carrier blocking region in the longitudinal direction relative to the semiconductor buffer region is increased.
5. The super junction power MOSFET of claim 4, wherein:
and the doping concentration of the semiconductor minority carrier blocking region is not lower than that of the semiconductor buffer region.
6. The super junction power MOSFET of claim 1, wherein:
the gate structure is a planar gate structure or a trench gate structure.
7. The super junction power MOSFET of claim 1, wherein: the shape of the cellular gate structure includes, but is not limited to, any one of a stripe shape, a hexagonal shape, a rectangular shape, or a circular shape.
8. The super junction power MOSFET of claim 1, wherein: the arrangement mode of the super junction structure formed by the semiconductor first drift region and the semiconductor second drift region in the voltage-proof layer includes, but is not limited to, any one of a strip shape, a hexagon shape, a rectangle shape or a circle shape.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1290404A (en) * | 1998-12-04 | 2001-04-04 | 通用电气公司 | Insulated gate bipolar transistor for zero-voltage switching |
| EP1276156A1 (en) * | 2001-07-13 | 2003-01-15 | Abb Research Ltd. | High power bipolar transistor |
| CN104241365A (en) * | 2014-04-10 | 2014-12-24 | 电子科技大学 | SOI horizontal power MOSFET device |
| CN105932056A (en) * | 2016-07-01 | 2016-09-07 | 电子科技大学 | RB-IGBT (Reverse Blocking-Insulated Gate Bipolar Transistor) with super junction |
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| JP4929304B2 (en) * | 2009-03-13 | 2012-05-09 | 株式会社東芝 | Semiconductor device |
| JP2010283132A (en) * | 2009-06-04 | 2010-12-16 | Mitsubishi Electric Corp | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290404A (en) * | 1998-12-04 | 2001-04-04 | 通用电气公司 | Insulated gate bipolar transistor for zero-voltage switching |
| EP1276156A1 (en) * | 2001-07-13 | 2003-01-15 | Abb Research Ltd. | High power bipolar transistor |
| CN104241365A (en) * | 2014-04-10 | 2014-12-24 | 电子科技大学 | SOI horizontal power MOSFET device |
| CN105932056A (en) * | 2016-07-01 | 2016-09-07 | 电子科技大学 | RB-IGBT (Reverse Blocking-Insulated Gate Bipolar Transistor) with super junction |
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