CN108281163B - Consumable chip memory voltage feedback method and consumable chip - Google Patents
Consumable chip memory voltage feedback method and consumable chip Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17503—Ink cartridges
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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Abstract
The invention relates to the technical field of printer consumable materials, in particular to a consumable chip memory voltage feedback method and a consumable chip. Switching a feedback type according to a high M bit data level of memory output data and adjusting a feedback voltage according to a low N-M bit data level of the output data; wherein: when the N bit data is rewritable data, the feedback type corresponding to the high M bit data level is a first feedback type; when the N bit data is non-rewritable data, the feedback type corresponding to the high M bit data level is a second feedback type; when the N is the non-rewritable data after being rewritten, the feedback type corresponding to the high M bit data is a third type; the intervals of the feedback voltages of the second feedback type and the third feedback type are different.
Description
Technical Field
The invention relates to the technical field of printer consumable materials, in particular to a consumable chip memory voltage feedback method and a consumable chip.
Background
Fig. 1 is a schematic diagram of a system of a consumable chip and an imaging device in the prior art. The imaging device comprises a read-write control circuit and an ADC voltage detection circuit; the consumable chip comprises a decoding circuit and a storage circuit. And the consumable chip storage circuit is respectively and electrically connected with the read-write control circuit and the ADC voltage detection circuit of the imaging device through the ID line of the imaging system. The consumable chip storage circuit comprises a plurality of storage modules, and each storage module is used for storing N-bit data of a consumable chip. Each storage module comprises N bit data storage units which respectively and correspondingly store each bit data in the N bit data. Each data storage unit comprises four different types of feedback circuits, and the data storage units select the corresponding feedback circuits to store bit data according to the output signals of the decoding circuits and output feedback voltages to the imaging equipment.
Imaging equipment can detect whether the feedback voltage of consumptive material chip satisfies printing imaging equipment's requirement to the feedback voltage of the all data of a plurality of consumptive material chips of record, when the feedback voltage of consumptive material chip and the feedback voltage of the all data of one of them consumptive material chip of record were unanimous, printing imaging equipment can report the mistake. This requires that the feedback voltage values corresponding to each data in each consumable chip are inconsistent.
The printing imaging device can detect corresponding feedback voltage after writing action is carried out on the storage unit, and the printing imaging module can report errors after the feedback voltage of the storage unit corresponding to the consumable chip storing the rewritable data is changed.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a voltage feedback method for a consumable chip memory, comprising:
switching a feedback type according to a high M bit data level of memory output data and adjusting a feedback voltage according to a low N-M bit data level of the output data;
wherein:
when the N bit data is rewritable data, the feedback type corresponding to the high M bit data level is a first feedback type;
when the N bit data is non-rewritable data, the feedback type corresponding to the high M bit data level is a second feedback type;
when the N is the non-rewritable data after being rewritten, the feedback type corresponding to the high M bit data is a third feedback type;
the intervals of the feedback voltages of the second feedback type and the third feedback type are different.
In the above technical solution, the feedback voltage of the memory is different according to the different values (i.e. levels) of the low N-M bit data of the output data, so that the feedback voltage corresponding to each data in each consumable chip is different. Controlling whether the feedback voltage of the feedback circuit can be changed due to the writing action of the imaging device according to the high M data value (i.e. level) of the memory output data: when the imaging device rewrites the rewritable data, the feedback voltage corresponding to the data does not cause the change of the feedback voltage interval during reading due to the writing action of the imaging device; when the imaging device rewrites the non-rewritable data, the feedback voltage interval corresponding to the data may cause the feedback voltage change during reading due to the writing action of the imaging device.
Preferably, M is greater than or equal to 2; the highest-order data level of the rewritable data is different from the highest-order data level of the rewritable data. When the imaging device writes the consumable chip, only the highest bits of the data are allowed to be written, and whether the data are rewritten or not can be reflected according to the highest bit data level.
Preferably, the intervals of the feedback voltages of the second feedback type and the first feedback type are the same.
Preferably, the feedback voltage is equal to the power supply voltage when the low N-M bit data levels of the output data are all the same.
Preferably, the memory circuit includes a first memory cell for storing the non-rewritable data, a second memory cell for storing the writable data, and a bit data output terminal for outputting data of a certain memory cell; the feedback circuit is electrically connected with each bit data output end to receive the data output by the storage circuit; the feedback circuit outputs different feedback voltages for data stored in different storage units; the feedback circuit is used for outputting different feedback voltage ranges before and after the rewriting of the non-rewritable data stored in the same first storage unit; the feedback circuit outputs the same feedback voltage range before and after rewriting the rewritable data stored in the same second storage unit.
In the above technical scheme, the feedback circuit outputs different feedback voltages for the data stored in different storage units, so that the feedback voltages corresponding to each data in each consumable chip are different. When the imaging equipment rewrites rewritable data, the feedback voltage interval corresponding to the data does not cause the feedback voltage change during reading because of the writing action of the imaging equipment; when the image forming apparatus rewrites the data that is not rewritable, the feedback voltage interval corresponding to the data may cause a change in the feedback voltage at the time of reading due to the writing action of the print image forming apparatus.
Preferably, the feedback circuit comprises a feedback module; the feedback module switches feedback types according to the data output by the storage circuit; the feedback types comprise a first feedback type, a second feedback type and a third feedback type, the feedback voltages of the first feedback type and the second feedback type are the same in interval, and the feedback voltages of the feedback modules of the second feedback type and the third feedback type are different in interval; the feedback circuit is configured to set the non-rewritable data stored in the same first storage unit to a second feedback type before the non-rewritable data is rewritten, and to set the non-rewritable data to a third feedback type after the non-rewritable data is rewritten. The feedback circuit effects a change in the feedback voltage interval by switching between different feedback types.
Preferably, the feedback circuit is configured to perform the first feedback type for both rewritable data stored in the same second storage unit before the rewritable data is rewritten and after the rewritable data is rewritten. So that the feedback voltage interval before and after rewriting of rewritable data is not changed.
Preferably, feedback voltage intervals of the feedback modules of the first feedback type and the second feedback type are the same.
Preferably, the N bit data output terminals include M high bit data output terminals; the feedback module is electrically connected with each high-bit data output end and switches feedback types according to the electric signals of the high-bit data output ends; the first feedback type corresponds to a first level combination state of the high-bit data output end; the second feedback type corresponds to a second level combination state of the high-bit data output end; the third feedback type corresponds to a third level combination state of the high-bit data output end; the first level combination state is a level combination state of the high-bit data output end when the data output by the storage circuit is the rewritable data; the second level combination state is a level combination state of the high-bit data output end when the data output by the storage circuit is the non-rewritable data; the third level combination state is a level combination state of the high-order data output terminal when the data output from the memory circuit is the rewritten non-rewritable data.
Preferably, M is greater than or equal to 2; the highest bit level of the second level combination state is opposite to the highest bit level of the corresponding third level combination state. When the imaging device writes the consumable chip, only the highest bits of the data are allowed to be written, and whether the data are rewritten or not can be reflected according to the highest bit data level.
Preferably, when the levels of the N-M lower data terminals are the same, the voltage of the feedback output terminal is equal to the power supply voltage.
Preferably, the feedback module comprises a gating unit, a feedback voltage adjusting unit and a feedback type switching unit, wherein the feedback type switching unit is electrically connected with the feedback voltage adjusting unit and the gating unit; the gating unit and the feedback voltage adjusting unit are connected between the output end of the feedback module and the ground in series; the type switching unit is electrically connected with the high-bit data output end and switches the feedback type according to the level combination state of the high-bit data output end; the feedback voltage adjusting unit is electrically connected with the low-bit data output end and adjusts the voltage of the feedback output end according to the level combination state of the low-bit data output end.
Preferably, the feedback voltage adjusting unit includes a plurality of voltage adjusting components connected in parallel with each other; the voltage adjusting component comprises a voltage adjusting transistor and a first voltage adjusting control element, and the first voltage adjusting control element is electrically connected with the voltage adjusting transistor so as to connect the voltage adjusting transistor into the feedback voltage adjusting unit or remove the voltage adjusting transistor from the feedback voltage adjusting unit; the voltage adjusting components are in one-to-one correspondence with the low-bit data output ends, and first voltage adjusting control elements of the voltage adjusting components are electrically connected with the corresponding low-bit data output ends.
Preferably, the voltage regulating transistor is an NMOS transistor, and the first voltage regulating control element is electrically connected to the drain and the gate of the voltage regulating transistor; the first voltage regulation control element can short-circuit the drain and the gate of the voltage regulation transistor; the first voltage regulation control element is capable of pulling the gate of the voltage regulation transistor to ground potential.
Preferably, the feedback type switching unit includes an operational amplifier element, a switching transistor, a feedback resistor, a first switching control element, a second switching control element, and a third switching control element; the drain electrode of the switching transistor is electrically connected with the feedback voltage adjusting unit, the source electrode of the switching transistor is electrically connected with the gating unit, and the grid electrode of the switching transistor is electrically connected with the first switching control element; the output end of the operational amplifier element is connected to the grid electrode of the switching transistor through the second switching control element; one end of the feedback resistor is grounded, and the other end of the feedback resistor is connected to the drain electrode of the switching transistor through the third switching control element; the first switching control element, the second switching control element and the third switching control element are electrically connected with the high-order data output end.
Preferably, the feedback circuit includes a plurality of the feedback modules, and the feedback modules correspond to the storage units one to one.
Preferably, the device also comprises a decoding circuit; the output end of the decoding circuit is connected to the gating unit.
Preferably, the gating unit includes a first gating transistor and a second gating transistor connected in series with each other; and the control end of the first gating transistor and the control end of the second gating transistor are electrically connected with the output end of the decoding circuit.
Drawings
FIG. 1 is a system diagram of a consumable chip and an imaging device according to the prior art.
FIG. 2 is a system diagram of a consumable chip and an imaging device according to the present invention.
FIG. 3 is a schematic diagram of a consumable chip according to the present invention.
Fig. 4 shows an equivalent circuit of the first feedback type feedback module according to different voltage regulation control signals in the first embodiment of the present invention.
Fig. 5 shows an equivalent circuit of a second feedback type feedback module according to different voltage regulation control signals in the first embodiment of the present invention.
Fig. 6 shows an equivalent circuit of a third feedback type feedback module according to different voltage regulation control signals in the first embodiment of the present invention.
Fig. 7 shows an equivalent circuit when the voltage regulation control signals are all inactive in the first embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The present embodiment is only for explaining the present invention, and it is not limited to the invention, and those skilled in the art can make modifications without inventive contribution to the present embodiment as needed after reading the present specification, but all of them are protected by patent laws within the scope of the claims of the present invention.
Example one
A consumable includes a consumable container for holding the consumable, and a consumable chip mounted on the consumable container. The consumable communicates with the imaging device through the consumable chip, and sends consumable data to the imaging device and responds to a control command of the imaging device.
As shown in fig. 2, the imaging apparatus controls the read-write control circuit through the controller 101 to realize switching between read operation and write operation of the consumable chip.
The consumable chip includes a memory circuit for storing consumable chip data. In order to enable the feedback voltage of the consumable chip to conform to the expectations of the imaging device. The consumable chip of the embodiment adopts a memory voltage feedback method as follows:
the consumable chip switches the feedback type according to the high M bit data level of the output data of the memory and adjusts the feedback voltage according to the low N-M bit data level of the output data. In this embodiment, the data of the memory is N-bit data. When the imaging device carries out writing operation on the consumable chip, only the highest bits of the data are allowed to be written. The image forming apparatus in the present embodiment performs a one-way write operation only on the most significant bit of data in the storage unit, for example, rewrites the most significant bit of data in the storage unit from 1 to 0. Therefore, the consumable chip can judge whether the data is rewritten according to the highest data level of the data output by the storage circuit. The consumable chip switches the feedback type according to the highest 2-bit data level of the memory output data and adjusts the feedback voltage according to the remaining low-bit data (i.e., low N-2-bit data) level of the output data.
The feedback types include: the first feedback type, the second feedback type and the third feedback type. The feedback voltage regions of the first feedback type and the second feedback type are the same; the second and third feedback types differ in the interval (i.e., range) of feedback voltages. Specifically, in the embodiment, the feedback voltage range output by the first feedback type and the second feedback type is 2.8-5V; the feedback voltage range of the third feedback type output is 5.5-10V.
When the N bit data output by the storage circuit is rewritable data, the consumable chip is a first feedback type according to the feedback type corresponding to the high M bit data level. So that the feedback voltage range corresponding to the rewritable data in the storage circuit is 2.8-5V before or after the write operation is performed.
When the N bit data output by the storage circuit is the non-rewritable data, the consumable chip is a second feedback type according to the feedback type corresponding to the high M bit data level; and when the N bit data output by the storage circuit is the rewritten non-rewritable data, the consumable chip is of a third type according to the feedback type corresponding to the high M bit data. Making the non-rewritable data in the memory circuit correspond to a feedback voltage range of 2.8-5V before the write operation is performed; when data is not rewritable in the memory circuit, the corresponding feedback voltage range after the write operation is performed is 5.5-10V. Thereby making the feedback voltage of the consumable chip conform to the expectations of the imaging device.
When the imaging device performs a write operation on the consumable chip, only the write operation on the top few bits of the data is allowed, and the write operation can only be unidirectional (for example, in the same consumable chip, the data can only be changed from 1 to 0 or can only be changed from 0 to 1). The high-order data output end used for controlling the switching of the feedback type needs to comprise a data output end corresponding to several-order data which allows the writing operation and a data output end corresponding to the highest-order data in the data which does not allow the writing operation; the other bit data output ends are used as low bit data output ends. In this way, the second feedback type (corresponding to the set of combinations of level states of the bit data output terminals before these bit data are rewritten) and the third feedback type (corresponding to the set of combinations of level states of the bit data output terminals after these bit data are rewritten) can be distinguished by the electric signal of the bit data output terminal corresponding to the several bit data which are allowed to perform the write operation. The first feedback type and the third feedback type are distinguished by an electric signal at a bit data output terminal corresponding to the most significant bit data among the bit data not allowed to enter the write operation.
Specifically, in this embodiment, only the most significant bit is allowed to be written, and the write operation changes 1 to 0. Controlling the feedback type of the feedback module according to the electric signal of the highest 2-bit data of the N-bit data, specifically:
TABLE 1
Before and after writing different types of data, the corresponding feedback units and feedback voltages have the following relationship:
TABLE 2
As can be seen from the above table, the N-bit data 11XXXXXX becomes 01 xxxxxxxx after the write operation, the feedback module changes from the second feedback type to the third feedback type, the feedback voltage value changes, and this data is non-rewritable data. After the N-bit data 10 XXXXXXX is written, the data becomes 00 XXXXXXXXX, the feedback module is still in the first feedback type, the feedback voltage value is not changed, and the data is rewritable data. The data after the write operation of the N bit data 01XXXXXXX is still 01 XXXXXXXXX, the feedback type of the feedback module is still the third feedback type, the feedback voltage value is unchanged, and the data is rewritable data. The data 00XXXXXXX after the N bit data 00XXXXXXX is still written, the feedback module is still of the first feedback type, the feedback voltage value is unchanged, and the data is rewritable data.
In addition, when the low N-M bit data levels of the output data of the consumable chip are the same, the feedback voltage is equal to the power supply voltage. For example, in the embodiment, when the low N-2 bit data of the output data of the consumable chip is all 0 or all 1, the feedback voltage of the consumable chip is about 15.5V.
The consumable chip for implementing the memory voltage feedback method in this embodiment is shown in fig. 2, and includes: a memory circuit 201, a decoding circuit 202, and a feedback circuit 203.
The memory circuit includes a plurality of memory cells for storing data and a bit data output terminal for outputting data stored in each memory cell. For example, the bit data output terminals CONT for outputting the data stored in the first memory cell1-CONTNBit-by-bit data output terminal CONT1-CONTNAnd the data storage unit is in one-to-one correspondence with each storage bit of the storage unit and is used for outputting each bit of data in the storage unit. Bit data output terminal CONT for outputting data stored in nth memory cellN1-CONTNNBit-by-bit data output terminal CONTN1-CONTNNAnd the data storage unit is in one-to-one correspondence with each storage bit of the storage unit and is used for outputting each bit of data in the storage unit. The storage unit is divided into a first storage unit for storing rewritable data and a second storage unit for storing non-rewritable data. The memory unit can be realized by EEPROM, FLASH, FRAM, OTP, MTP, MRAM, ROM, SRAM and other memories. The memory circuit is connected to the imaging device through a signal line ID, and performs a write operation and a read operation according to a control signal of the imaging device.
The feedback circuit is electrically connected with each data transmission output end of the corresponding storage unit to receive the data output by the storage circuit; meanwhile, the feedback voltage output terminal OUT of the feedback circuit is electrically connected to the imaging device through the signal line ID. So that the memory circuit can adjust the feedback voltage output to the imaging device according to the level of each bit data output terminal after performing the write operation. The imaging device reads the feedback voltage on the signal line ID to verify the consumable chip. Specifically, the feedback circuit includes a plurality of feedback modules, and the feedback modules of the feedback circuit correspond to the storage units of the storage circuit one to one.
And the decoding circuit is electrically connected with the imaging device through an address line ADD, receives address information sent by the imaging device and determines a memory cell selected to be operated by the imaging device. The output end of the decoding circuit is connected to the feedback circuit so as to gate the feedback module corresponding to the storage unit selected by the imaging equipment.
Fig. 3 is an implementation manner of the feedback module of the present embodiment. The feedback module comprises a gating unit, a feedback voltage adjusting unit and a feedback type switching unit.
The feedback voltage adjusting unit includes a plurality of voltage adjusting components connected in parallel to each other. Specifically, each voltage regulation component comprises a voltage regulation transistor and a first voltage regulation control element. The NMOS transistor MN1 and the control unit 1 in fig. 3 form a voltage regulation component; the NMOS transistor MN2 and the control unit 2 constitute another voltage regulation component. The feedback type switching unit includes an operational amplifier Q1, a switching transistor MN11, feedback resistors R1, R2, and switching control elements X1, X2, X3. The gate unit includes gate transistors MN12 and MN12 connected in series with each other.
The output end of a feedback voltage adjusting unit composed of a plurality of voltage adjusting components connected in parallel is connected to the feedback voltage output end OUT of the feedback module, and the other end of the voltage feedback adjusting unit is connected to the drain electrode of the first switching transistor MN 11. The drain electrode of the voltage regulating transistor is connected to the feedback voltage output end OUT, the source electrode of the voltage regulating transistor is connected to the drain electrode of the first switching transistor MN11, one end of the first voltage regulating control element is connected with the drain electrode of the voltage regulating transistor MN11, and the other end of the first voltage regulating control element is connected with the source electrode of the voltage regulating transistor MN 11. The positive input of the operational amplifier Q1 is connected to the negative terminal of the feedback resistor R1 and the positive terminal of the feedback resistor R2, the negative input of the operational amplifier Q1 is connected to the reference voltage VREF, and the output of the operational amplifier Q1 is connected to the gate of the switching transistor MN11 through the first switching control element X1. One end of the second switching control element X2 is connected to the feedback voltage output terminal OUT, and the other end of the second switching control element X2 is connected to the gate of the switching transistor MN 11. The source of the switching transistor MN11 is connected to the drain of the first gating transistor MN12, the source of the first gating transistor MN12 is connected to the drain of the second gating transistor MN13, and the source of the second gating transistor is connected to ground. The positive terminal of the feedback resistor R1 is connected to the feedback voltage adjusting unit through the third switching control unit X3, the feedback resistor R1 is connected to the positive terminal of the feedback resistor R2, and the negative terminal of the feedback resistor R2 is grounded. In the gating unit, the drain of a first gating transistor MN12 is connected to the source of the switching transistor NM11, the gate of the first gating transistor is connected to the output terminal of the operational amplifier Q1 through a first switching control element, the source of the first gating transistor is connected to the drain of a second gating transistor MN13, and the source of the second gating transistor is grounded.
The decoding unit outputs control gating signals WL1-N and BL1-N to gate corresponding feedback modules in the feedback circuit. The control gating signal WL is connected with the grid electrode of the first gating transistor corresponding to the feedback module, and the control gating signal BL is connected with the grid electrode of the second gating transistor corresponding to the feedback module. When the control strobe signal WL and the control strobe signal BL are active, the corresponding feedback block is gated, and the feedback block will output a feedback voltage to the feedback voltage output terminal OUT.
The storage unit comprises N-by-N bit data output ends which are used for outputting N bit data in the N storage units. Next, a voltage feedback method for outputting N-bit data stored in the first memory cell will be described as an example. The voltage feedback method of the rest of the memory cells is similar to that of the cell, and is not described herein again. In the bit data output terminal for outputting the N-bit data stored in the first memory cell, CONT1-CONTN-MA low N-M bit for outputting N bit data, which is a low bit data output terminal; bit data output terminal CONTN-M+1-CONTNThe upper M bits for outputting the N-bit data are the upper data output terminals. The high data output terminal is electrically connected to three switching control elements X1, X2, X3 to control the feedback type of the feedback module. The low-bit data end corresponds to each feedback voltage adjusting unit of the voltage feedback unit one by one and is used for controlling whether the voltage feedback unit acts on the feedback voltage or not. The low-bit data output end is electrically connected with the control input end of the first voltage regulation control element in the corresponding voltage feedback unit: when the electric signal output by the low-bit data output end enables the first voltage regulation control element electrically connected with the low-bit data output end to take effect, the source and drain of the voltage regulation transistor of the voltage feedback unit are in short circuit, and the voltage regulation transistor is connected into the voltage feedback unit to act on the feedback voltage; when the electric signal output by the low-bit data output end makes the first voltage regulating control element electrically connected with the low-bit data output end fail, the voltage feedback unit can be enabled to beThe gate of the cell's regulating transistor, which is equivalently removed from the voltage feedback unit without contributing to the feedback voltage, is grounded. The data of the voltage feedback unit acting in the voltage feedback unit is the feedback voltage value output by the voltage feedback output end OUT, so that the feedback voltage output by the voltage feedback unit can be adjusted and changed in the output voltage interval of the feedback module of the current feedback type according to the electric signal of the low-bit data output end. In the voltage feedback unit in this embodiment, the output voltage value of the feedback module adjusted according to the electrical signal at the N-2 low-bit data output ends can theoretically have at most 2N-2And a feedback voltage value.
(1) The first feedback type (high data output 00/10)
At this time, the first switching control element X1 is non-conductive, the second switching control element X2 is conductive, and the third switching control element X3 is non-conductive; resulting in the gate of the switching transistor MN11 being connected to the feedback voltage output terminal OUT, the drain of the switching transistor being unconnected to the feedback resistor R1, and the output of the operational amplifier Q1 being unconnected to the gate of the switching transistor MN 11.
The voltage regulation control element 1 to the voltage regulation control unit N-M are controlled by a voltage regulation control signal CONT1-CONTN-M(i.e., the combination of the level states of the N-M lower data outputs). When these voltage regulating control elements are active, e.g. CONT1When the voltage regulation control elements are effective, the left end and the right end of the voltage regulation control element 1 are equivalent to short circuits, the source and the drain of the voltage regulation transistor MN1 are in short circuit, and when the voltage regulation control elements are ineffective, such as CONT1When the voltage regulating transistor MN1 is not active, the voltage regulating control element 1 pulls down the gate of the voltage regulating transistor MN1 to ground potential, and the voltage regulating transistor MN1 is equivalent to open circuit and does not act on the feedback voltage.
Voltage regulating control signal CONT1-CONTN-MWhen the NMOS transistor takes effect, the corresponding NMOS transistor can act on the feedback voltage; when CONT1In effect, the voltage regulating transistor MN1The source and drain are in short circuit; voltage regulating control signal CONTN-MIn effect, the voltage regulating transistor MNN-MThe source and drain are in short circuit; voltage regulating control signal CONT1And voltage regulation control signal CONTN-MAll give birth toTime-efficient, voltage-regulating transistor MN1And a voltage regulating transistor MNN-MThe source and the drain are all in short circuit; voltage regulating control signal CONT1-CONTN-MWhen all are effective, the voltage regulating transistor MN1-a voltage regulating transistor MNN-MThe source and drain are all shorted, and the equivalent circuits are respectively shown in fig. 4.
When the voltage-regulating control signal CONT1When the feedback voltage becomes effective, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONTN-MWhen the feedback voltage becomes effective, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1And voltage regulation control signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1-voltage regulation control signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
by analysis, the voltage-regulating transistor MN1-a voltage regulating transistor MNN-MThe width-to-length ratio of the NMOS transistor is inconsistent, one or more NMOS transistors can be selected to be connected into the feedback voltage adjusting unit, and the feedback voltages V of different feedback voltage output ends can be obtainedID。
(2) Second feedback type (high data output 11)
At this time, the first switching control element X1 is not turned on, the second switching control element X2 is turned on, and the third switching control elementX3 is not conductive; resulting in the gate of the switching transistor MN11 being connected to the feedback voltage output terminal OUT, the drain of the switching transistor being unconnected to the feedback resistor R1, and the output of the operational amplifier Q1 being unconnected to the gate of the switching transistor MN 11. The operational amplifier Q1, the switching transistor MN11, the feedback resistor R1, and the feedback resistor R2 constitute a negative feedback circuit. Due to the existence of the negative feedback circuit, the voltage of the A point is clamped at
So that the operational amplifier Q1 is equivalent to one
Is constant voltage source.
Voltage regulating control signal CONT1-CONTN-MWhen the NMOS transistor takes effect, the corresponding NMOS transistor can act on the feedback voltage; when CONT1In effect, the voltage regulating transistor MN1The source and drain are in short circuit; voltage regulating control signal CONTN-MIn effect, the voltage regulating transistor MNN-MThe source and drain are in short circuit; voltage regulating control signal CONT1And voltage regulation control signal CONTN-MWhen all are effective, the voltage regulating transistor MN1And a voltage regulating transistor MNN-MThe source and the drain are all in short circuit; voltage regulating control signal CONT1-CONTN-MWhen all are effective, the voltage regulating transistor MN1-a voltage regulating transistor MNN-MThe source and drain are all shorted, and the equivalent circuits are respectively shown in fig. 5.
Voltage regulating control signal CONT1When the feedback voltage becomes effective, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONTN-MWhen the feedback voltage becomes effective, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1And voltage regulation controlControl signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1-voltage regulation control signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
by analysis, the voltage-regulating transistor MN1-a voltage regulating transistor MNN-MThe feedback voltage VID of different feedback voltage output ends can be obtained by selecting one or more NMOS to be connected into the feedback voltage adjusting unit.
(3) The third feedback type (01 for high-order data output)
At this time, the first switching control element X1 is turned on, the second switching control element X2 is turned off, and the third switching control element X3 is turned on; resulting in the gate of the switching transistor MN11 being connected to the output terminal of the operational amplifier Q1, the drain of the switching transistor MN11 being connected to the feedback resistor R1, and the gate of the switching transistor MN11 not being connected to the feedback voltage output terminal OUT.
Voltage regulating control signal CONT1-CONTN-MWhen the NMOS transistor takes effect, the corresponding NMOS transistor can act on the feedback voltage; when the CONT1 is effective, the source and the drain of the voltage regulating transistor MN1 are short-circuited; voltage regulating control signal CONTN-MIn effect, the voltage regulating transistor MNN-MThe source and drain are in short circuit; voltage regulating control signal CONT1And voltage regulation control signal CONTN-MWhen all are effective, the voltage regulating transistor MN1And a voltage regulating transistor MNN-MThe source and the drain are all in short circuit; voltage regulating control signal CONT1-CONTN-MWhen all are effective, the voltage regulating transistor MN1-a voltage regulating transistor MNN-MThe source and drain are all shorted, and the equivalent circuits are respectively shown in fig. 6.
When the voltage-regulating control signal CONT1In effect, feedbackThe feedback voltage of the voltage output terminal OUT is:
voltage regulating control signal CONTN-MWhen the feedback voltage becomes effective, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1And voltage regulation control signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
voltage regulating control signal CONT1-voltage regulation control signal CONTN-MWhen both are in effect, the feedback voltage of the feedback voltage output end OUT is as follows:
by analysis, the voltage-regulating transistor MN1-a voltage regulating transistor MNN-MThe feedback voltage VID of different feedback voltage output ends can be obtained by selecting one or more NMOS to be connected into the feedback voltage adjusting unit.
In addition, when the voltage-regulating control signal CONT1-voltage regulation control signal CONTN-MAll disabled, the feedback module is equivalent to fig. 7. At this time, all NMOS transistors are invalid, and the voltage V of the voltage feedback output end OUTIDEqual to the input voltage (i.e., the power supply voltage) of the image forming apparatus, about 15.5V.
The voltage regulation control element and the switching control element in the circuit can be realized by the same electronic element. For example, the voltage-regulating control element/switching control element in this embodiment is composed of a PMOS transistor and an NMOS transistor, where the source of the PMOS transistor is shorted with the source of the NMOS transistor as input, the drain of the PMOS transistor is shorted with the drain of the NMOS transistor as output, the gate of the PMOS transistor and the gate of the NMOS transistor are connected to opposite input signals, and when the gate of the PMOS transistor inputs a low level and the gate of the NMOS transistor inputs a high level, the switch is closed; when the grid input of the PMOS tube is high level and the grid input of the NMOS tube is low level, the switch is switched off.
The above circuit is not limited to the use of MOS transistors, and may be implemented using other active or passive devices.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various changes or modifications within the scope of the appended claims.
Claims (18)
1. A voltage feedback method for a consumable chip memory is characterized by comprising the following steps:
switching a feedback type according to a high 2-bit data level of memory output data and adjusting a feedback voltage according to a low 6-bit data level of the output data;
wherein:
when the 8-bit data is rewritable data, the feedback type corresponding to the high 2-bit data level is a first feedback type;
when the 8-bit data is non-rewritable data, the feedback type corresponding to the high 2-bit data level is a second feedback type;
when the 8-bit data is the rewritten non-rewritable data, the feedback type corresponding to the high 2-bit data is a third feedback type;
the intervals of the feedback voltages of the second feedback type and the third feedback type are different.
2. The method of claim 1, wherein the method comprises:
the highest-order data level of the rewritable data is different from the highest-order data level of the rewritable data.
3. The method of claim 1, wherein the method comprises:
the intervals of the feedback voltages of the second feedback type and the first feedback type are the same.
4. The method of claim 3, wherein the method comprises:
when the lower 6-bit data levels of the output data are the same, the feedback voltage is equal to the power supply voltage.
5. A consumable chip, comprising:
the storage circuit comprises a first storage unit for storing non-rewritable data, a second storage unit for storing rewritable data, and an 8-bit data output end for outputting the data of a certain storage unit;
the 8-bit data output ends comprise 2 high-bit data output ends and 6 low-bit data output ends;
the feedback circuit is electrically connected with each bit data output end to receive the data output by the storage circuit;
the feedback circuit outputs different feedback voltages according to the electric signals of the corresponding high-bit data output ends of the data stored in different storage units;
the feedback circuit is used for outputting different feedback voltage ranges before and after the rewritable data are rewritten for the rewritable data stored in the same first storage unit;
the feedback circuit outputs the same feedback voltage range before and after rewriting the rewritable data stored in the same second storage unit.
6. The consumable chip of claim 5, comprising:
the feedback circuit comprises a feedback module;
the feedback module switches feedback types according to the data output by the storage circuit;
the feedback types comprise a first feedback type, a second feedback type and a third feedback type, the feedback voltages of the first feedback type and the second feedback type are the same in interval, and the feedback voltages of the feedback modules of the second feedback type and the third feedback type are different in interval;
the feedback circuit is configured to set the non-rewritable data stored in the same first storage unit to a second feedback type before the non-rewritable data is rewritten, and to set the non-rewritable data to a third feedback type after the non-rewritable data is rewritten.
7. The consumable chip of claim 6, wherein:
the feedback circuit is configured to perform a first feedback type for rewritable data stored in the same second storage unit before the rewritable data is rewritten and after the rewritable data is rewritten.
8. The consumable chip of claim 7, wherein:
feedback voltage regions of the feedback modules of the first feedback type and the second feedback type are the same.
9. The consumable chip of claim 7, wherein:
the feedback module is electrically connected with each high-bit data output end and switches feedback types according to the electric signals of the high-bit data output ends;
the first feedback type corresponds to a first level combination state of the high-bit data output end;
the second feedback type corresponds to a second level combination state of the high-bit data output end;
the third feedback type corresponds to a third level combination state of the high-bit data output end;
the first level combination state is a level combination state of the high-bit data output end when the data output by the storage circuit is the rewritable data;
the second level combination state is a level combination state of the high-bit data output end when the data output by the storage circuit is the non-rewritable data;
the third level combination state is a level combination state of the high-order data output terminal when the data output from the memory circuit is the rewritten non-rewritable data.
10. The consumable chip of claim 9, wherein:
the highest bit level of the second level combination state is opposite to the highest bit level of the corresponding third level combination state.
11. The consumable chip of claim 9, wherein:
when the levels of the 6 low-bit data output ends are the same, the voltage of the feedback output end is equal to the power supply voltage.
12. The consumable chip of claim 9, wherein:
the feedback module comprises a gating unit, a feedback voltage adjusting unit and a feedback type switching unit, wherein the feedback type switching unit is electrically connected with the feedback voltage adjusting unit and the gating unit;
the gating unit and the feedback voltage adjusting unit are connected between the output end of the feedback module and the ground in series;
the type switching unit is electrically connected with the high-bit data output end and switches the feedback type according to the level combination state of the high-bit data output end;
the feedback voltage adjusting unit is electrically connected with the low-bit data output end and adjusts the voltage of the feedback output end according to the level combination state of the low-bit data output end.
13. The consumable chip of claim 12, wherein:
the feedback voltage adjusting unit comprises a plurality of voltage adjusting components which are connected in parallel; the voltage adjusting component comprises a voltage adjusting transistor and a voltage adjusting control element, and the voltage adjusting control element is electrically connected with the voltage adjusting transistor so as to connect the voltage adjusting transistor into the feedback voltage adjusting unit or remove the voltage adjusting transistor from the feedback voltage adjusting unit;
the voltage adjusting components are in one-to-one correspondence with the low-bit data output ends, and voltage adjusting control elements of the voltage adjusting components are electrically connected with the corresponding low-bit data output ends.
14. The consumable chip of claim 13, wherein:
the voltage regulating transistor is an NMOS (N-channel metal oxide semiconductor) tube, and the voltage regulating control element is electrically connected with the drain electrode and the grid electrode of the voltage regulating transistor;
the voltage regulation control element can short-circuit the drain and the gate of the voltage regulation transistor;
the voltage regulation control element is capable of pulling the gate of the voltage regulation transistor to ground potential.
15. The consumable chip of claim 12, wherein:
the feedback type switching unit comprises an operational amplifier element, a switching transistor, a feedback resistor, a first switching control element, a second switching control element and a third switching control element;
the drain electrode of the switching transistor is electrically connected with the feedback voltage adjusting unit, the source electrode of the switching transistor is electrically connected with the gating unit, and the grid electrode of the switching transistor is electrically connected with the first switching control element;
the output end of the operational amplifier element is connected to the grid electrode of the switching transistor through the second switching control element;
one end of the feedback resistor is grounded, and the other end of the feedback resistor is connected to the drain electrode of the switching transistor through the third switching control element;
the first switching control element, the second switching control element and the third switching control element are electrically connected with the high-order data output end.
16. The consumable chip of claim 12, wherein:
the feedback circuit comprises a plurality of feedback modules, and the feedback modules correspond to the storage units one by one.
17. The consumable chip of claim 12, wherein:
the device also comprises a decoding circuit;
the output end of the decoding circuit is connected to the gating unit.
18. The consumable chip of claim 17, wherein:
the gating unit comprises a first gating transistor and a second gating transistor which are connected in series;
and the control end of the first gating transistor and the control end of the second gating transistor are electrically connected with the output end of the decoding circuit.
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|---|---|---|---|---|
| CN1195176A (en) * | 1997-01-31 | 1998-10-07 | 东芝株式会社 | Memory having plurality of threshold level in memory cell |
| US6016276A (en) * | 1997-06-20 | 2000-01-18 | Nec Corporation | Semiconductor memory device which can be set one from multiple threshold value |
| CN1505153A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���綫֥ | semiconductor storage device |
| CN107589920A (en) * | 2017-07-31 | 2018-01-16 | 杭州旗捷科技有限公司 | For the repositioning method of chip, electronic equipment, storage medium and equipment |
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2018
- 2018-02-05 CN CN201810111202.1A patent/CN108281163B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195176A (en) * | 1997-01-31 | 1998-10-07 | 东芝株式会社 | Memory having plurality of threshold level in memory cell |
| US6016276A (en) * | 1997-06-20 | 2000-01-18 | Nec Corporation | Semiconductor memory device which can be set one from multiple threshold value |
| CN1505153A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���綫֥ | semiconductor storage device |
| CN107589920A (en) * | 2017-07-31 | 2018-01-16 | 杭州旗捷科技有限公司 | For the repositioning method of chip, electronic equipment, storage medium and equipment |
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