CN108269776A - Circuit structure under bonding pad and manufacturing method thereof - Google Patents

Abstract

The invention provides a Circuit Under Pad (CUP) structure and a manufacturing method thereof. The CUP structure comprises: an element layer formed on the substrate and including a plurality of elements; at least one metal layer formed on the element layer; a plurality of connecting layers formed between the metal layer and the element layer and at least one metal layer for electrically connecting the metal layer and the element layer and for electrically connecting the at least one metal layer; and a solder pad layer formed on the uppermost connection layer for connecting solder balls; the element layer comprises a forbidden region, the forbidden region does not comprise any element, and the range of the forbidden region is defined according to at least one parameter in the process step of wire bonding, the thickness of a welding electric layer, the thickness of a metal layer or the thickness of a connecting layer, so that the element is prevented from being damaged in the process step of wire bonding.

Description

Under pad circuit structure and manufacturing method thereof

technical field

The invention relates to a circuit under pad (CUP) structure and a manufacturing method thereof, in particular to a circuit under pad (CUP) structure and a manufacturing method thereof that can avoid damage to components.

Background technique

FIG. 1A shows a schematic top view of a typical chip. As shown in FIG. 1A , the chip 1 includes a plurality of bonding pad structures 10 and a main circuit area 11 . As shown in a schematic top view of FIG. 1B, a plurality of bonding pad structures 10 are located in the peripheral region of the chip 1 for connecting solder balls 106, and as shown in a schematic cross-sectional view of FIG. 1C, the bonding pad structures 10 have circuits under bonding pads. (circuit under pad, CUP) structure 10A. Fig. 1C shows a schematic cross-sectional view of line AA' in Fig. 1B. As shown in FIG. 1C , the CUP structure 10A includes a substrate 101 , an element layer 102 , a plurality of metal layers 103 , a plurality of connection layers 104 , and a pad layer 105 . Wherein, the element layer 102 directly below the pad layer 105 has a plurality of elements, which is well known to those skilled in the art, and will not be repeated here.

Generally speaking, the pad layer 105 is used to connect the chip 1 with other external electronic components (not shown) through wire bonding process steps. The wire bonding process step is to bond solder balls and solder wires to the solder layer 105 to connect to other external electronic components. In the wire bonding process step, many parameters are included, such as welding time, welding pressure, welding power, and Process steps with these parameters, such as soldering temperature, will damage the components in the component layer 102 below the pad layer 105 , so that the function of the components will be damaged, resulting in electrical errors or failures of the chip 1 .

In view of this, the present invention proposes a circuit under pad (CUP) structure and a manufacturing method thereof for the improvement of the above-mentioned prior art, which can prevent components in the pad structure 10 from being damaged in the chip.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose a circuit under pad (CUP) structure and a manufacturing method thereof, which can prevent components in the pad structure 10 from being damaged in the chip.

In order to achieve the above object, from one point of view, the present invention provides a circuit underpad (CUP) structure, comprising: an element layer formed on a substrate, including a plurality of elements; at least one metal layer , formed on the element layer; a plurality of connecting layers, formed between the metal layer and the element layer, and between the at least one metal layer, for electrically connecting the metal layer and the element layer, and for electrically connecting the at least one a metal layer; and a pad layer formed on the uppermost connection layer for connecting a solder ball; wherein, the element layer includes a forbidden area, the forbidden area does not include any of the elements, and the forbidden The range of the zone is defined according to at least one parameter in a wire bonding process step, the thickness of the solder layer, the thickness of the metal layer, or the thickness of the connection layer, so as to avoid damage to the wire bonding process step The plurality of elements; wherein, the element includes a junction diode, a metal oxide semiconductor (MOS) transistor or/and a bipolar transistor.

To achieve the above object, from another point of view, the present invention provides a method for manufacturing a circuit underpad (CUP) structure, comprising: forming an element layer on a substrate, wherein the element layer includes a plurality of elements ; forming at least one metal layer on the element layer; forming a plurality of connection layers between the metal layer and the element layer, and between the at least one metal layer, for electrically connecting the metal layer and the element layer, and for electrically connecting the at least one metal layer; and forming a pad layer on the uppermost connection layer for connecting a solder ball; wherein, the element layer includes a forbidden area, and the forbidden area does not include any of the elements, and The range of the forbidden area is defined according to at least one parameter in a wire bonding process step, the thickness of the solder layer, the thickness of the metal layer, or the thickness of the connection layer, so as to avoid the wire bonding process The step damages the plurality of devices; wherein the device includes a junction diode, a metal oxide semiconductor (MOS) transistor or/and a bipolar transistor.

In one preferred implementation form, the parameters in the wire bonding process step include welding time, welding pressure, welding power, welding temperature, and welding wire.

In one of the preferred implementation forms, the forbidden area is a square or circular area centered on the central point of the CUP structure viewed from the top view when viewed from the top view.

In one preferred implementation form, the solder ball is completely located in the forbidden area when viewed from a top view.

In one of the preferred implementation forms, the circuit under pad (CUP) structure further includes a plurality of dielectric layers respectively formed between the element layer and the at least one metal layer, the at least one between the metal layers, and between the plurality of connection layers and the pad layer.

The following will be described in detail through specific examples, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

Figure 1A shows a schematic top view of a typical chip;

FIG. 1B shows a schematic top view of the pad structure 10;

FIG. 1C shows a schematic cross-sectional view of an under-pad circuit structure 10A;

2A-2B show a first embodiment of the present invention;

Figure 3 shows a second embodiment of the present invention;

Figure 4 shows a third embodiment of the present invention;

5A-5H show a fourth embodiment of the present invention.

Explanation of symbols in the figure

1 chip

10,20,30,40 pad structure

10A, 20A under pad circuit structure

11 main circuit area

101,201 Substrates

102,202 component layers

103,203 metal layers

104,204 connection layers

105,205 pad layer

106,206,306,406 solder balls

207 welding wire

208 dielectric layer

209,309,409 Prohibited areas

AA’,BB’ line

Detailed ways

The drawings in the present invention are all schematic, mainly intended to represent the process steps and the upper and lower sequence relationship among the layers, and the shapes, thicknesses and widths are not drawn to scale.

2A-2B show a first embodiment of the present invention, respectively showing a schematic top view of a bonding pad structure 20 and a schematic cross-sectional view of a circuit under pad (CUP) structure 20A according to the present invention. As shown in FIG. 2A , the bonding pad structure 20 has a forbidden area 209 from the top view of FIG. 2A , and the solder ball 206 is completely located in the forbidden area 209 . As shown in the cross-sectional schematic view of FIG. 2B , the bonding pad structure 20 has a circuit under pad (CUP) structure 20A, and FIG. 2B shows a schematic cross-sectional view of the section line BB' in FIG. 2A . As shown in FIG. 2B , the CUP structure 20A includes a substrate 201 , an element layer 202 , a plurality of metal layers 203 , a plurality of connection layers 204 , and a pad layer 205 . Wherein, the substrate 201 may be a semiconductor substrate, such as a crystal silicon substrate, an amorphous silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, an alloy semiconductor substrate, and the like. The element layer 202 is formed on the substrate 201 and includes a plurality of elements for performing various electrical functions.

It should be noted that the above-mentioned elements include junction diodes, metal oxide semiconductor (MOS) transistors or/and bipolar (bipolar) transistors, such as but not limited to various electrostatic protection elements (such as ESD elements or TVS Components, etc.), silicon controlled rectifier (silicon controlled rectifier, SCR), Zener diode (Zener diode), Schottky diode (Schottky diode), MOSFET or BJT with switch or amplification function, etc.

A plurality of metal layers 203 are formed on the element layer 202, including wires of metal or conductive material, respectively connected to a plurality of connection layers 204, and the plurality of metal layers 203 and the plurality of connection layers 204 are used to electrically connect the element layer 202 Components and pad layer 205 . A plurality of connection layers 204 are formed between the metal layer 203 and the device layer 202 , and between different metal layers 203 for electrically connecting the metal layer 203 and the device layer 202 , and for electrically connecting different metal layers 203 respectively. The pad layer 205 is formed on the uppermost connection layer 203 for connecting the solder balls 206 .

As shown in FIG. 2A and FIG. 2B, the element layer 202 includes a forbidden area 209, as shown in the diamond-shaped grid area in FIG. At least one of the parameters, the thickness of the solder layer 205 , the thickness of the metal layer 203 , or the thickness of the connection layer 204 is defined to avoid damage to the components during the wire bonding process.

In a preferred embodiment, for example, the forbidden zone 209 is determined according to parameters in the wire bonding process steps, including but not limited to welding time, welding pressure, welding power, welding temperature, and welding wire. The size of the range. For example, the forbidden area 209 is a square or circular area centered on the central point of the CUP structure 20A viewed from a top view; when the welding pressure is greater, the size (range) of the forbidden area 209 is larger; , when the welding power or the welding temperature is higher, the size (range) of the forbidden area 209 is larger and so on.

As shown in FIG. 2B , the circuit structure 20A under the bonding pad also includes a plurality of dielectric layers 208, which are indicated by dotted areas and are respectively formed between the element layer 202 and the metal layer 203, between the multiple metal layers 203, and between the multiple Between the connection layer 204 and the pad layer 205.

Fig. 3 shows a second embodiment of the present invention. FIG. 3 shows a schematic top view of a bonding pad structure 30 according to the present invention. As shown in FIG. 3 , a preferred embodiment, the forbidden area 309 is a circular area centered on the central point of the CUP structure viewed from the top view, and the solder ball 306 is viewed from the top view. In other words, it is completely located in the exclusion zone 309 .

Fig. 4 shows a third embodiment of the present invention. This embodiment shows a schematic top view of the bonding pad structure 40 according to the present invention. As shown in FIG. 4 , a preferred embodiment, the forbidden area 409 viewed from the top view is a square area centered on the central point of the CUP structure viewed from the top view, and the solder ball 406 is viewed from the top view. , completely within the exclusion zone 409.

5A-5H show a fourth embodiment of the present invention. This embodiment shows a schematic cross-sectional view of the manufacturing method of the CUP structure 20A according to the present invention. First, as shown in FIG. 5A , a substrate 201 is provided, wherein the substrate 201 is, for example but not limited to, a semiconductor substrate, such as a single crystal silicon (crystal silicon) substrate, a polycrystalline silicon (amorphous silicon) substrate, a silicon carbide substrate, an arsenic Gallium substrate, alloy semiconductor (alloy semiconductor) substrate, etc. Next, as shown in FIG. 5B , an element layer 202 is formed on the substrate 201 , and the element layer 202 includes a plurality of elements for performing various electrical functions. A forbidden area 209 is defined in the element layer 202, as shown in the diamond-shaped lattice area in the figure, the forbidden area 209 does not include any elements, and the scope of the forbidden area 209 is based on at least one parameter in the subsequent wire bonding process steps, The thickness of the soldering layer 205 , the thickness of the metal layer 203 , or the thickness of the connecting layer 204 is defined to prevent the components in the component layer 202 from being damaged by the process steps of wire bonding.

Next, as shown in FIG. 5C , a dielectric layer 208 is formed on the device layer 202 , between the device layer 202 and the subsequently formed metal layer 203 in the vertical direction. Next, as shown in FIG. 5D , a connection layer 204 is formed on the device layer 202 , between the device layer 202 and the subsequently formed metal layer 203 in the vertical direction. Next, as shown in FIG. 5E , a metal layer 203 is formed on the element layer 202 , and in a vertical direction, the metal layer 203 is connected to the connection layer 204 below. Next, as shown in FIG. 5F , a dielectric layer 208 is formed on the metal layer 203 .

Next, as shown in FIG. 5G , the connection layer 204 , the metal layer 203 , the uppermost connection layer 204 , and the dielectric layer 208 are formed. Next, as shown in FIG. 5H , a solder pad layer 205 is formed on the uppermost connection layer 204 for connecting solder balls 206 , and the solder balls 206 are connected to solder wires 207 . Wherein, the forbidden area 209 in the element layer 202 does not include any element, so as to avoid the process step of wire bonding from damaging the plurality of elements.

The present invention has been described above with reference to preferred embodiments, and the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, the metal layer/connection layer is not limited to the two layers shown in the figure, and can be other numbers of metal layers/connection layers, such as four layers or ten layers; The semiconductor element may also be other types of elements, such as electrostatic protection elements. The scope of the present invention shall cover the above and all other equivalent variations.

Claims (10)

1. A circuit CUP structure under a pad, characterized in that it comprises: An element layer, formed on a substrate, includes a plurality of elements; at least one metal layer formed on the element layer; a plurality of connecting layers formed between the metal layer and the element layer, and between the at least one metal layer, for electrically connecting the metal layer and the element layer, and for electrically connecting the at least one metal layer; and a pad layer formed on the uppermost connection layer for connecting a solder ball; Wherein, the element layer includes a forbidden area, the forbidden area does not include any of the elements, and the range of the forbidden area is based on at least one parameter in a wire bonding process step, the thickness of the solder layer, the thickness of the metal layer Thickness, or the thickness of the connection layer is defined, in order to avoid the process step of the wire bonding from damaging the plurality of components; Wherein, the element includes a junction diode, a metal oxide semiconductor MOS transistor or/and a bipolar transistor. 2 . The circuit structure under pads according to claim 1 , wherein the parameters in the wire bonding process step include welding time, welding pressure, welding power, welding temperature, and welding wire. 3 . The circuit structure under pads as claimed in claim 2 , wherein the forbidden area is a square or circular area centered on a central point of the CUP structure viewed from a top view when viewed from a top view. 4 . 4. The circuit structure under pads as claimed in claim 1, wherein the solder balls are completely located in the forbidden area as viewed from a top view. 5. The circuit structure under pads as claimed in claim 1, further comprising a plurality of dielectric layers respectively formed between the element layer and the at least one metal layer, between the at least one metal layer, and the plurality of dielectric layers. Between the connection layer and the pad layer. 6. A method for manufacturing a circuit CUP structure under a pad, characterized in that it comprises: forming an element layer on a substrate, wherein the element layer includes a plurality of elements; forming at least one metal layer on the element layer; forming a plurality of connection layers between the metal layer and the element layer, and between the at least one metal layer, for electrically connecting the metal layer and the element layer, and for electrically connecting the at least one metal layer; and forming a pad layer on the uppermost connection layer for connecting a solder ball; Wherein, the element layer includes a forbidden area, the forbidden area does not include any of the elements, and the range of the forbidden area is based on at least one parameter in a wire bonding process step, the thickness of the solder layer, the thickness of the metal layer Thickness, or the thickness of the connection layer is defined, in order to avoid the process step of the wire bonding from damaging the plurality of components; Wherein, the element includes a junction diode, a metal oxide semiconductor MOS transistor or/and a bipolar transistor. 7. The method for manufacturing an under-pad circuit structure according to claim 6, wherein the parameters in the wire bonding process step include welding time, welding pressure, welding power, welding temperature, and welding wire. 8 . The method for manufacturing an under-pad circuit structure as claimed in claim 7 , wherein, viewed from a top view, the forbidden area is a square or circular area centered on a central point of the CUP structure viewed from a top view. 9 . The method for manufacturing the circuit structure under pads as claimed in claim 6 , wherein the solder balls are completely located in the forbidden area when viewed from a top view. 10. The method for manufacturing an under-pad circuit structure according to claim 6, further comprising: forming a dielectric layer between the element layer and the at least one metal layer, between the at least one metal layer, and the multiple layers, respectively. Between a connection layer and the pad layer.