CN108268086B

CN108268086B - Semiconductor device, semiconductor system, and method of operating semiconductor device

Info

Publication number: CN108268086B
Application number: CN201710617460.2A
Authority: CN
Inventors: 全浩渊; 金硪灿; 李宰坤
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-01-03
Filing date: 2017-07-26
Publication date: 2023-05-26
Anticipated expiration: 2037-07-26
Also published as: CN108268086A

Abstract

The application provides a semiconductor device, a semiconductor system, and a method of operating a semiconductor device. The semiconductor device includes a first intellectual property block including a functional unit and an interface unit; a first clock control circuit that controls the first clock source; a second clock control circuit that sends the first clock request to the first clock control circuit and controls a second clock source that receives the clock signal from the first clock source; and a channel management circuit configured to send a second clock request to the second clock control circuit in response to a clock stop request received from the first intellectual property block; wherein the functional unit controls operation of the first intellectual property block and the interface unit receives a first signal provided from a second intellectual property block electrically connected to the first intellectual property block and provides the first signal to the functional unit.

Description

Semiconductor device, semiconductor system, and method of operating semiconductor device

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2017-0000722, which was filed on day 1, month 3, 2017, to korean intellectual property office, and from U.S. patent application No.15/424,028, which was filed on day 2, month 3, 2017, to U.S. patent and trademark office, which are incorporated herein by reference in their entireties.

Technical Field

The present inventive concept relates to a semiconductor device, a semiconductor system, and a method of operating the semiconductor device.

Background

A system-on-a-chip (SoC) may include one or more intellectual property blocks (IP blocks), a Clock Management Unit (CMU), and a power management unit (PUM). The CMU provides a clock signal to the one or more IP blocks. The CMU may not provide clock signals to the non-operational IP blocks, thus reducing the waste of resources for systems employing the SoC.

To control the provision of the clock signal, various clock sources included in the CMU, such as a multiplexing circuit (MUX circuit), a clock dividing circuit, a short stop circuit, and a clock gating circuit, may be controlled by software using Special Function Registers (SFRs). However, the control speed of software is slower than that of hardware.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor apparatus including a first Intellectual Property (IP) block including a functional unit and an interface unit; a first clock control circuit that controls the first clock source; a second clock control circuit that sends the first clock request to the first clock control circuit and controls a second clock source that receives the clock signal from the first clock source; and a channel management circuit configured to send a second clock request to the second clock control circuit in response to the clock stop request received from the first IP block; wherein the functional unit controls the operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the functional unit.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor apparatus including a master IP block that operates in response to a first clock signal provided from a Clock Management Unit (CMU); and a slave IP block including a functional unit that operates in response to the second clock signal supplied from the CMU, and an interface unit configured to receive the bus operation signal from the master IP block at a first point in time and to supply the bus operation signal to the functional unit at a second point in time different from the first point in time.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor system including a system on a chip (SoC) and one or more external devices electrically connected to the SoC. A system-on-a-chip (SoC) comprising: a first IP block including a functional unit and an interface unit; a second IP block electrically connected to the first IP block; a first clock control circuit that controls the first clock source; a second clock control circuit that sends the first clock request to the first clock control circuit and controls a second clock source that receives the clock signal from the first clock source; and a channel management circuit that transmits a second clock request to the second clock control circuit in response to the clock stop request received from the first IP block. The function unit controls the operation of the first IP block, and the interface unit receives a first signal supplied from the second IP block and supplies the first signal to the function unit.

According to an exemplary embodiment of the inventive concept, there is provided a method of operating a semiconductor device, including: receiving a first signal from a primary IP block; sending a clock request to the CMU to wake up a functional unit of the slave IP block; generating a second signal corresponding to the first signal after receiving the clock signal from the CMU from the IP block; and providing the second signal to the functional unit.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including: a first IP block including a functional unit and an interface unit; and a second IP block electrically connected to the first IP block, wherein the interface unit is configured to receive the first signal from the second IP block when the functional unit is in a sleep state and to provide a second signal corresponding to the first signal when the functional unit wakes up.

Drawings

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments with reference to the attached drawings in which:

fig. 1 is a schematic view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 2 and 3 are schematic views of a semiconductor device according to an exemplary embodiment of the inventive concept;

Fig. 4 is a schematic view illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 5 is a timing diagram illustrating an operation of the semiconductor device of fig. 4 according to an exemplary embodiment of the inventive concept;

fig. 6 is a timing diagram illustrating an operation of the semiconductor device of fig. 4 according to an exemplary embodiment of the inventive concept;

fig. 7 and 8 are schematic views of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 9 is a schematic view illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 10 is a timing diagram illustrating an operation of the semiconductor device of fig. 9 according to an exemplary embodiment of the inventive concept;

fig. 11 is a flowchart of a method of operating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 12 is a block diagram of a semiconductor system to which a semiconductor device and a method of operating the semiconductor device according to an exemplary embodiment of the inventive concept are applicable; and

fig. 13, 14 and 15 are semiconductor systems to which semiconductor devices and methods of operating the semiconductor devices according to exemplary embodiments of the inventive concept are applicable.

Detailed Description

Fig. 1 is a schematic view of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, a semiconductor apparatus 1 according to an exemplary embodiment of the inventive concept includes a Clock Management Unit (CMU) 100, intellectual property blocks (IP blocks) 200 and 210, and a Power Management Unit (PMU) 300. The semiconductor apparatus 1 according to an exemplary embodiment of the inventive concept may be provided as a system on chip (SoC), but the inventive concept is not limited thereto.

CMU 100 provides clock signals to

IP blocks

200 and 210. In this embodiment, CMU 100 includes

clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120g,

channel management circuits

130 and 132, and CMU controller 110.

Clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120g generate clock signals to be provided to

IP blocks

200 and 210, and

channel management circuits

130 and 132 are disposed between

clock components

120f and 120g and

IP blocks

200 and 210 to provide a communication channel CH between CMU 100 and

IP blocks

200 and 210. In addition, CMU controller 110 provides clock signals to

IP blocks

200 and 210 using

clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120 g.

In exemplary embodiments of the inventive concept, the communication channels CH provided by the

channel management circuits

130 and 132 may be provided to conform to as in

The Low Power Interface (LPI), Q-channel interface, or P-channel interface defined in the LPI specification, but the inventive concept is not limited thereto. For example, the communication channel CH may conform to any communication protocol according to the implementation of the semiconductor apparatus 1.

Each of the

clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120g includes a

clock source

124a, 124b, 124c, 124d, 124e, 124f, and 124g and a

clock control circuit

122a, 122b, 122c, 122d, 122e, 122f, and 122g that controls each of the

clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124 g.

Clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124g may include, for example, multiplexing circuits (MUX circuits), clock dividing circuits, short stop circuits, clock gating circuits, and the like.

Clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120g have parent-child relationships to each other. In the present exemplary embodiment, clock component 120a is the parent of clock component 120b, and clock component 120b is the child of clock component 120a and is the parent of clock component 120 c. In addition, clock component 120e is the parent of two

clock components

120f and 120g, and

clock components

120f and 120g are children of clock component 120 e. Further, in the present exemplary embodiment, the clock component 120a disposed closest to the Phase Locked Loop (PLL) is a root clock component, and the

clock components

120f and 120g disposed closest to the

IP blocks

200 and 210 are leaf clock components. This parent-child relationship is also formed between

clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g and

clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124g corresponding to the parent-child relationships of

clock components

120a, 120b, 120c, 120d, 120e, 120f, and 120 g.

In an embodiment, the clock component 120a is implemented by a PLL controller. In an embodiment, the PLL controller receives a signal oscillated at a constant or variable frequency by the oscillator OSC and a PLL signal outputted by the PLL from the oscillator OSC, and outputs one of two received signals based on a certain condition. When the component requires a PLL signal, the PLL controller outputs the PLL signal. When the component requires an oscillation signal, the PLL controller outputs the oscillation signal. The PLL controller may be implemented using a ring oscillator or a crystal oscillator, for example. In an embodiment, the clock component 120b is a clock multiplexer unit that receives the first clock signal CLK1 from the first clock component 120a and the second clock signal CLK2 from an external source (e.g., an external CMU).

Clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g send and receive clock Requests (REQ) and Acknowledgements (ACKs) thereof between parent and child, and provide clock signals to

IP blocks

200 and 210.

For example, if IP block 200 does not require a clock signal (e.g., if IP block 200 is in a sleep state), CMU 100 stops providing the clock signal to IP block 200.

For example, under the control of the CMU 100 or the CMU controller 110, the channel management circuit 130 transmits a first signal for stopping the supply of the clock signal to the IP block 200. Upon receiving the first signal, after completing the job being processed, the IP block 200 transmits a second signal indicating that the clock signal can be stopped to the channel management circuit 130. After receiving the second signal from IP block 200, channel management circuit 130 requests clock component 120f to instruct its parent to stop providing the clock signal.

As an example, if the communication channel CH provided by the channel management circuit 130 conforms to the Q channel interface, the channel management circuit 130 sends a qreq signal having a first logic value (e.g., logic low, hereinafter denoted by L) as a first signal to the IP block 200. The channel management circuit 130 then receives, for example, a QACCEPTn signal having a first logic value from the IP block 200 as a second signal. Channel management circuit 130 then sends a clock Request (REQ), for example, with a first logic value, to clock component 120f. In this case, the clock Request (REQ) having the first logic value refers to "clock supply stop request".

Upon receiving a clock Request (REQ) having a first logic value from the channel management circuit 130 (in other words, a clock supply stop request), the clock control circuit 122f instructs the clock source 124f (e.g., clock gating circuit) to stop supplying the clock signal. Thus, IP block 200 may enter a sleep mode. In this process, the clock control circuit 122f may provide an ACK having the first logic value to the channel management circuit 130. It should be noted that although the channel management circuit 130 receives an Acknowledgement (ACK) having the first logic value after transmitting the clock supply stop request having the first logic value, it may not be possible to ensure the stop of the clock supply from the clock source 124 f. This is because the Acknowledgement (ACK) described above may simply mean that the clock control circuit 122f recognizes that the clock component 120f that is the parent of the channel management circuit 130 does not have to provide a clock signal to the channel management circuit 130.

On the other hand, the clock control circuit 122f of the clock component 120f may send a clock Request (REQ) with a first logic value to the clock control circuit 122e of its parent clock component 120 e. If the IP block 210 does not require a clock signal, for example, when the clock control circuit 122e receives a request for clock supply stop from the clock control circuit 122g, the clock control circuit 122e disables the clock source 124e (e.g., clock dividing circuit) to stop supplying the clock signal. As a result, IP blocks 200 and 210 may enter sleep mode.

Such operations may be similarly performed for other

clock control circuits

122a, 122b, 122c, and 122 d.

Further, although clock control circuit 122f of clock component 120f sends a clock Request (REQ) having a first logic value to clock control circuit 122e of its parent clock component 120e, clock control circuit 122e may not disable clock source 124e if IP block 210 is in an operational state. Thereafter, clock control circuit 122e disables clock source 124e and sends a clock Request (REQ) having a first logic value to its parent clock control circuit 120d only when IP block 210 no longer requires a clock signal. In other words, clock control circuit 122e may disable clock source 124e only if clock control circuit 122e receives a clock supply stop request from both of its

sub-clock control circuits

122f and 122 g.

When all

clock sources

124a, 124b, 124c, 124d, 124e, and 124f are disabled in the sleep state of IP blocks 200 and 210 and IP block 200 enters the run state, CMU 100 then resumes providing clock signals to

IP blocks

200 and 210.

The channel management circuit 130 sends a clock Request (REQ) having a second logic value (e.g., logic high, hereinafter denoted by H) to the clock control circuit 122f of its parent clock component 120f and waits for an Acknowledgement (ACK) from the clock control circuit 122f. Here, the clock Request (REQ) having the second logic value refers to a "clock supply request", and the Acknowledgement (ACK) of the clock supply request means that the supply clock signal is recovered from the clock source 124 f. Clock control circuit 122f may not immediately enable clock source 124f (e.g., a clock gating circuit) and, thus, wait for a clock signal to be provided from its parent.

Next, the clock control circuit 122f transmits a clock Request (REQ) having a second logic value (in other words, a clock supply request) to its parent clock control circuit 122e, and waits for an Acknowledgement (ACK) from the clock control circuit 122 e. Such operations may be similarly performed for the

clock control circuits

122a, 122b, 122c, and 122 d.

The clock control circuit 122a, which is the root clock component that has received the clock Request (REQ) having the second logic value from the clock control circuit 122b, enables the clock source 124a (e.g., a multiplexing circuit), and sends an Acknowledgement (ACK) to the clock control circuit 122b. When clock sources 124b, 124c, 124d, and 124e are sequentially enabled in this manner, clock control circuit 122e sends an Acknowledgement (ACK) from clock source 124e indicating recovery of the clock supply to clock control circuit 122f. Upon receipt of the Acknowledgement (ACK), clock control circuit 122f enables clock source 124f, provides a clock signal to IP block 200, and provides the Acknowledgement (ACK) to channel management circuit 130.

In this way, the

clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g operate in a complete handshake manner for sending and receiving clock Requests (REQ) and responses (ACKs) between parent and child. As a result,

clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g

control clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124g with hardware, and thus control clock signals provided to

IP blocks

200 and 210.

Clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g may operate independently to send clock Requests (REQs) to their parent or

control clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124g. In addition,

clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g may operate under the control of CMU controller 110. On the other hand, in exemplary embodiments of the inventive concept, the

clock control circuits

122a, 122b, 122c, 122d, 122e, 122f, and 122g may include a Finite State Machine (FSM) that controls each of the

clock sources

124a, 124b, 124c, 124d, 124e, 124f, and 124g in response to transmitted and received clock Requests (REQ) between the parent and child.

Fig. 2 and 3 are schematic views of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 2, in the semiconductor apparatus 1 according to the present embodiment, an IP block 200 and an IP block 210 have a master-slave relationship. In this embodiment, the IP block 200 may be a slave device and the IP block 210 may be a master device. For example, IP block 210 may include a processor, controller, etc., and IP block 200 may include internal memory devices, external memory interfaces, etc. IP block 210 and IP block 200 may be electrically connected to each other via bus 400.

Hereinafter, for convenience, the IP block 210 and the IP block 200 will be denoted as a master IP block 210 and a slave IP block 200, respectively.

In an exemplary embodiment of the inventive concept, the type of the bus 400 through which the master IP block 210 and the slave IP block 200 can transmit and receive data to and from each other is not particularly limited. It should be noted, however, that the buses to which the exemplary embodiments of the inventive concept may be applied include, for example, buses conforming to protocols such as advanced peripheral bus protocol (APB protocol) and advanced high-performance bus protocol (AHB protocol) regardless of the operation state of the slave device when the master device and the slave device perform the operation of the bus. For example, the master IP block 210 may transmit a bus operation signal for data transmission to the slave IP block 200 regardless of whether the slave IP block 200 is currently in a sleep state or an operational state.

In an exemplary embodiment of the inventive concept, the bus operation signals include address signals, data signals, control signals, etc. necessary for the master IP block 210 and the slave IP block 200 to perform the bus operation. Further, the bus operation signals may be provided in various forms depending on the type of protocol employed by the bus 400. Specific examples thereof will be described later with reference to fig. 4 and 9.

As described above in fig. 1, master IP block 210 and slave IP block 200 issue clock requests to CMU 100 in a complete handshake and may receive clock signals from CMU 100.

For example, the slave IP block 200 transmits a request for clock supply or a request for clock supply stop via a channel CH1 formed between the slave IP block 200 and the channel management circuit 130. The channel management circuit 130 and the clock component 120f transmit and receive clock Requests (REQ) and responses (ACK), and control a clock signal (CLK 1) supplied to the slave IP block 200. As shown in fig. 1 above, clock assembly 120f includes a clock source 124f for generating a clock signal (CLK 1) and a clock control circuit 122f for controlling clock source 124f in hardware.

As in the case of the slave IP block 200, the master IP block 210 transmits a request for clock supply or a request for clock supply stop via a channel CH2 formed between the master IP block 210 and the channel management circuit 132. The clock component 120g and the channel management circuit 132 send and receive clock Requests (REQ) and responses (ACK) and control the clock signal (CLK 2) provided to the master IP block 210. As shown in fig. 1 above, clock assembly 120g includes a clock source 124g for generating clock signal CLK2 and a clock control circuit 122g for controlling clock source 124g in hardware.

Subsequently, referring to fig. 3, the slave IP block 200 includes a functional unit 202 and an interface unit 204.

The functional unit 202 controls the original operation from the IP block 200. For example, the functional unit 202 corresponds to a circuit area in which the original functions of the slave IP block 200 are provided, such as an internal memory device and an external memory interface.

Interface unit 204 sends signals to functional unit 202 and receives signals from functional unit 202 via

channels

410 and 420, and provides signals (e.g., first signals) provided from main IP block 210 to functional unit 202.

Interface unit 204 may receive an operational status signal from functional unit 202 via channel 410. The operational status signal received via channel 410 may include information regarding the operational status of functional unit 202. For example, the operational status signal may include information regarding whether the operational status of the functional unit 202 is in a sleep state or a run state.

On the other hand, the interface unit 204 may send and receive second signals to and from the functional unit 202 via the channel 420. The second signal transmitted and received via channel 420 includes a signal corresponding to the first signal provided from the main IP block 210 via bus 400. For example, the second signal may be a signal that transitions from L to H at the second point in time to correspond to the first signal that transitions from L to H at the first point in time. Here, the second time point may be a time point later than the first time point.

For example, when the slave IP block 200 is in a sleep state, the first signal provided by the master IP block 210 may transition from L to H at a first point in time. In this case, after waking up from the IP block 200, the interface unit 204 may include a signal that transitions from L to H at a second point in time later than the first point in time.

As described above with reference to fig. 2, for example, in the case where the bus 400 conforms to the APB protocol or the AHB protocol, the master IP block 210 may transmit the bus operation signal to the slave IP block 200 regardless of the state of the slave IP block 200. At this time, if the slave IP block 200 is in the sleep state, the slave IP block 200 may not receive the bus operation signal of the master IP block 210. To avoid this, for example, the interface unit 204 may receive the first signal (e.g., the bus operation signal) at a first point in time when the main IP block 210 provides the first signal instead of the functional unit 202 in the sleep state. Furthermore, the interface unit 204 may provide a second signal to the functional unit 202, e.g. at a second point in time when waking up from the IP block 200. In other words, at the second point in time, the interface unit 204 may generate a second signal corresponding to the first signal.

After receiving the first signal from the IP block 210, the interface unit 204 may send a clock request to the channel management circuit 130 of the CMU 100 to wake up the functional unit 202 of the slave IP block 200.

As a result, the functional unit 202 can perform a bus operation with the main IP block 210 immediately after waking up according to the second signal received from the interface unit 204.

To provide such operation, the functional unit 202 and the interface unit 204 may be driven by different clock signals. The provision of different clock signals may vary depending on the particular purpose.

Fig. 4 is a schematic view illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 4, in the semiconductor apparatus 1 according to the current embodiment, the master IP block 210 and the slave IP block 200 may perform a bus operation via a bus 400 conforming to the APB protocol. In an exemplary embodiment of the inventive concept, the master IP block 210 may include an APB bridge block that coordinates data communication with another bus conforming to another protocol (e.g., the AHB protocol). For this discussion, it is first assumed that functional unit 202 of slave IP block 200 is in a sleep state.

The master IP block 210 may transmit a first signal to the slave IP block 200 to perform a bus operation with the slave IP block 200. At this time, the main IP block 210 does not consider the operation state of the functional unit 202. In this embodiment, the first signal transmitted by the main IP block 210 may include signals such as PSEL, PENABLE, PADDR and PWRITE. "AMBA" issued by ARM company ^TM The definition and interpretation of these signals is provided in the 3APB protocol v1.0 specification (ARM IHI 0024B) document, the disclosure of which is incorporated herein by reference in its entirety.

Interface unit 204 recognizes via channel 410 that functional unit 202 is currently in a sleep state. When the functional unit 202 is in the sleep state, the interface unit 204 receives the first signal supplied from the main IP block 210.

Next, in order to wake up the functional unit 202 of the slave IP block 200, the interface unit 204 transmits a clock request to the channel management circuit 130 of the CMU 100 via the channel CH1, and may receive an Acknowledgement (ACK) from the channel management circuit 130. The interface unit 204 may check whether a clock signal is provided to the slave IP block 200 via an Acknowledgement (ACK) received from the channel management circuit 130.

The interface unit 204 then detects via the channel 410 whether the functional unit 202 has transitioned to an operational state. When the functional unit 202 is shifted to the operation state, the interface unit 204 generates a second signal corresponding to the first signal, and supplies the generated second signal to the functional unit 202. Here, the second signal refers to signals such as ip_psel, ip_enable, ip_paddr, and ip_pwrite. These signals correspond to signals such as PSEL, PENABLE, PADDR and PWRITE as the first signal.

As a result, the functional unit 202 can immediately perform bus operations conforming to the main IP block 210 and APB protocol according to the second signal received from the interface unit 204 after waking up.

In addition, the interface unit 204 receives an ip_pready signal output by the function unit 202 of the IP block 200 during a bus operation, and may provide the ip_pready signal to the main IP block 210 as a PREADY signal conforming to the APB protocol.

Fig. 5 is a timing diagram illustrating an operation of the semiconductor device of fig. 4 according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, the functional unit 202 of the slave IP block 200 is in a sleep state at T1.

At T2, the master IP block 210 (e.g., APB bridge block) starts bus operation while transmitting the PSEL signal to the slave IP block 200, after which, at T3, the master IP block 210 transmits the PENABLE signal to the slave IP block 200. The PSEL signal and the PENABLE signal may be provided from the main IP block 210 at constant clock intervals (e.g., one clock interval or two clock intervals), and the specific provision content thereof may be determined according to the specific provision purpose.

At T2, upon receiving the PSEL signal of the master IP block 210, the interface unit 204 sends a clock request to the channel management circuit 130 of the CMU 100 via the channel CH1 to wake up the functional unit 202 of the slave IP block 200. For example, when channel CH1 conforms to the Q channel interface, interface unit 204 may send and receive signals such as QACTIVE, QREQn, QACCEPTn to and from channel management circuit 130. The "low power interface specification" may be issued at ARM corporation: the definition and interpretation of these signals is found in the ARM Q channel and P channel interface (ARM IHI 0068B), the disclosure of which is incorporated herein by reference in its entirety.

The clock PCLK is supplied to the functional unit 202 of the slave IP block 200 near T4 or after T4, and the wake-up process is performed from the IP block 200. At this time, the master IP block 210 also maintains the PSEL and PENABLE signals until the PREADY signal is provided by the slave IP block 200.

After T5 or after T5, the interface unit 204 recognizes the wake-up of the functional unit 202 and generates ip_psel and ip_penable signals corresponding to the PSEL and PENABLE signals. The clock intervals (T5 to T6) of the ip_psel signal and the ip_penable signal may be the same as the clock intervals (T2 to T3) between the PSEL signal and the PENABLE signal. The interface unit 204 also supplies the generated ip_psel and ip_enable signals to the function unit 202.

Upon receiving the ip_psel and ip_pebble signals from the interface unit 204, the functional unit 202 may send a PREADY signal to the master IP block 210 via the interface unit 204, either at T6 or after T6. For example, functional unit 202 sends an ip_pready signal to interface unit 204, and interface unit 204 sends the ip_pready signal as a PREADY signal to master IP block 210.

Thereafter, when the bus operation is completed, in order to transition the functional unit 202 of the slave IP block 200 to the sleep state, the interface unit 204 may transmit a request for clock supply stop to the channel management circuit 130 of the CMU 100 through the channel CH 1. As can be seen from T8 to T10, for example, if the channel CH1 conforms to the Q channel interface, the interface unit 204 can send and receive signals such as QACTIVE, QREQn and QACCEPTn to and from the channel management circuit 130.

Fig. 6 is a timing diagram illustrating an operation of the semiconductor device of fig. 4 according to an exemplary embodiment of the inventive concept.

Fig. 5 shows a case of shifting from the functional unit 202 of the IP block 200 to the sleep state when the bus operation is completed, and fig. 6 shows a case where the interface unit 204 further transmits a clock request (CLKREQ) to the channel management circuit 130 of the CMU 100 after the bus operation is completed.

For example, at T6, in response to receiving the ip_psel and ip_pebble signals from interface unit 204, functional unit 202 may send a PREADY signal to master IP block 210 via interface unit 204. For example, functional unit 202 may send an ip_pready signal to interface unit 204, and interface unit 204 may send the ip_pready signal as a PREADY signal to master IP block 210.

Thereafter, when bus operations are completed but operations are also needed from the IP block 200, the interface unit 204 may autonomously send a clock request (CLKREQ) to the channel management circuit 130 of the CMU 100.

Thereafter, when the additional operation is completed, in order to switch from the functional unit 202 of the IP block 200 to sleep, the interface unit 204 may transmit a request for clock supply stop to the channel management circuit 130 of the CMU 100 through the channel CH 1. As can be seen from T8 to T10, for example, if the channel CH1 conforms to the Q channel interface, the interface unit 204 can send and receive signals such as QACTIVE, QREQn and QACCEPTn to and from the channel management circuit 130.

Fig. 7 and 8 are schematic views of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 7, in the semiconductor apparatus 1 according to the current embodiment, the IP blocks 200 and 210 and the IP block 220 have a master-slave relationship. In this embodiment, the IP blocks 200 and 210 may be slaves and the IP block 220 may be a master. IP block 220 and

IP blocks

200 and 210 may be electrically connected to each other via bus 500.

Hereinafter, for convenience, the IP block 220 and the IP blocks 200 and 210 will be denoted as a master IP block 220 and slave IP blocks 200 and 210, respectively.

As described above, referring to fig. 2, the type of the bus 500 is not particularly limited, and the bus 500 also includes a bus conforming to a protocol that does not consider the operation state of the slave when the master and the slave perform bus operations (for example, bus operations in the AHB protocol).

As described with reference to fig. 1, the master IP block 220 and the slave IP blocks 200 and 210 issue clock requests to the CMU 100 in a complete handshake and receive clock signals from the CMU 100.

For example, a request for clock supply or a request for clock supply stop is transmitted from the IP blocks 200 and 210 via the channels CH1 and CH2 formed with the

channel management circuits

130 and 132, respectively. The

channel management circuits

130 and 132 respectively transmit and receive clock Requests (REQ) and responses (ACK) to the

clock components

120f and 120g, and respectively control each of the clock signals (CLK 1 and CLK 2) to be supplied to the slave IP blocks 200 and 210. As described above with reference to fig. 1,

clock assemblies

120f and 120g include

clock sources

124f and 124g for generating each of clock signals CLK1 and CLK2, respectively, and

clock control circuits

122f and 122g for hardware-controlled

clock sources

124f and 124g, respectively.

As in the case of the slave IP blocks 200 and 210, the master IP block 220 transmits a request for clock supply or a request for clock supply stop via a channel CH3 formed between the master IP block 220 and the channel management circuit 134. Channel management circuit 134 and clock component 120h send and receive clock Requests (REQ) and responses (ACK) and control the clock signal (CLK 3) to be provided to master IP block 220. As described with reference to fig. 1, clock component 120h includes a clock source 124h for generating a clock signal (CLK 3) and a clock control circuit 122h for controlling clock source 124h in hardware.

Subsequently, referring to fig. 8, slave IP blocks 200 and 210 include

functional units

202 and 212 and

interface units

204 and 214, respectively.

The

functional units

202 and 212 control the original operations of the slave IP blocks 200 and 210, and the

interface units

204 and 214 transmit signals to the

functional units

202 and 212 and receive signals from the

functional units

202 and 212 through the

channels

510, 520, 512 and 522 and provide the first signals provided from the master IP block 220 to the

functional units

202 and 212.

Interface units

204 and 214 may receive operating state signals from

functional units

202 and 212 via

channels

510 and 512, respectively. On the other hand,

interface units

204 and 214 may send and receive second signals to and from functional unit 202 via channels 520 and 522, respectively. Since the descriptions of the first signal and the second signal are repeated with the descriptions provided with reference to fig. 3, descriptions thereof will be omitted herein.

The

interface units

204 and 214 receive the first signal on behalf of the

functional units

202 and 212 that are in a sleep state at a first point in time when the primary IP block 220 provides the first signal. The

interface units

204 and 214 may provide a second signal to the

functional units

202 and 212 at a second point in time when they wake up from the IP blocks 200 and 210. In other words, at the second point in time, the

interface units

204 and 214 may generate a second signal corresponding to the first signal.

Further, after receiving the first signal from the master IP block 220, the

interface units

204 and 214 may send clock requests to the

channel management circuits

130 and 132 of the CMU 100 in order to wake up the

functional units

202 and 212 of the slave IP blocks 200 and 210.

As a result, the

functional units

202 and 204 can perform bus operations with the master IP block 220 immediately after waking up according to the second signals received from the

interface units

204 and 214.

Fig. 9 is a schematic view illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 9, in the semiconductor apparatus 1 according to the current embodiment, the master IP block 220 and the slave IP block 200 may perform a bus operation via the bus 400 compliant with the AHB protocol. Here, it is first assumed that the functional unit 202 of the slave IP block 200 is in a sleep state.

The master IP block 220 may transmit a first signal to the slave IP block 200 to perform a bus operation with the slave IP block 200. At this time, the main IP block 220 does not consider the operation state of the functional unit 202. In this embodiment, the first signal transmitted by the main IP block 220 may include signals such as HADDR, HWDTA, and HTRANS. Also, the decoder DEC may receive an input of the HADDR signal and provide the HSEL1 signal to the slave IP block 200. The decoder DEC may also provide the SEL signal to the multiplexing circuit MUX. For convenience, the HSEL1 signal will also be represented by the first signal. AMBA, which can be issued at ARM company ^TM The definition and interpretation of these signals is found in the 3AHB-Lite protocol v1.0 Specification (ARM IHI 0033A) document, which is well knownThe entire contents of the disclosure are incorporated herein by reference.

Interface unit 204 recognizes via channel 510 that functional unit 202 is currently in a sleep state. When the functional unit 202 is in the sleep state, the interface unit 204 receives the first signal provided from the main IP block 220.

Next, in order to wake up the functional unit of the slave IP block 200, the interface unit 204 transmits a clock request to the channel management circuit 130 of the CMU 100 via the channel CH1, and may receive an Acknowledgement (ACK) from the channel management circuit 130. The interface unit 204 may check whether a clock signal is provided to the slave IP block 200 through an Acknowledgement (ACK) received from the channel management circuit 130.

The interface unit 204 then detects whether the functional unit 202 has transitioned to an operational state via the channel 410. If the functional unit 202 is shifted to the operation state, the interface unit 204 generates a second signal corresponding to the first signal and supplies the generated second signal to the functional unit 202. Here, the second signal refers to signals such as ip_haddr, ip_hwdata, ip_htrans, and ip_hsel1. These signals correspond to signals such as HADDR, HWDATA, HTRANS and HSEL1 as the first signals, respectively.

As a result, the functional unit 202 immediately performs bus operations conforming to the master IP block 220 and the AHB protocol in response to the second signal received from the interface unit 204 after waking up.

On the other hand, during bus operation, interface unit 204 receives the IP_HRDATA1 and IP_HREADYOUT1 signals output by functional unit 202 of IP block 200 and may provide the IP_HRDATA1 and IP_HREADYOUT1 signals as APB compliant HRDATA1 and HREADYOUT1 signals to master IP block 220 via multiplexing circuitry (MUX) as HRDATA and HREADY signals.

The above disclosure may be similarly applied to interactions between the master IP block 220 and the slave IP block 210.

Fig. 10 is a timing diagram illustrating an operation of the semiconductor device of fig. 9 according to an exemplary embodiment of the inventive concept.

Referring to fig. 10, the functional unit 202 of the slave IP block 200 is in a sleep state at T1.

At T2 the decoder DEC and the master IP block 220 start bus operations while the HSEL and HTRANS signals are sent to the slave IP block 200.

After T2 or after T2, in response to receiving the HSEL and HTRANS signals of the decoder DEC and the master IP block 220, the interface unit 204 sends a clock request to the channel management circuit 130 of the CMU 100 over the channel CH1 to wake up the functional unit 202 of the slave IP block 200. For example, when channel CH1 conforms to a Q channel interface, interface unit 204 may send and receive signals such as QACTIVE, QREQn and QACCEPTn to and from channel management circuit 130.

The master IP block 220 stores the HSEL and HTRANS signals between T2 and T3. After the clock signal (e.g., slave clock) is provided to the functional unit 202 of the slave IP block 200 at T4, the stored HSEL and HTRANS signals are regenerated into ip_hsel and ip_htrans signals at T5. When a clock signal (e.g., a slave clock) is supplied to the functional unit 202 of the slave IP block 200, the slave IP block 200 performs a wake-up process.

At T5, when it is recognized that the functional unit 202 wakes up, the interface unit 204 generates ip_hsel and ip_htrans signals corresponding to the HSEL and HTRANS signals. The interface unit 204 also provides the generated ip_hsel and ip_htrans signals to the functional unit 202.

Upon receiving the ip_hsel and ip_htrans signals from the interface unit 204, the functional unit 202 may send a hreadout signal to a multiplexing circuit (MUX) via the interface unit 204, which may send the HREADY signal to the master IP block 220, either at T6 or after T6. For example, the functional unit 202 transmits an ip_hreadout signal corresponding to the hreadout signal to the interface unit 204, and the interface unit 204 may transmit the ip_hreadout signal as the hreadout signal to a multiplexing circuit (MUX).

Fig. 11 is a flowchart of a method of operating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 3 and 11, the method for operating a semiconductor device according to the present embodiment includes the following steps.

The interface unit 204 receives the first signal from the master IP block 220 (S1101), and transmits a clock request for waking up the functional unit 202 of the slave IP block 200 to the CMU 100 (S1103).

After receiving the clock signal from the CMU 100 from the IP block 200, in other words, after the interface unit 204 receives an Acknowledgement (ACK) in response to the clock request from the CMU 100 (S1105), the interface unit 204 generates a second signal corresponding to the first signal (S1107).

Thereafter, the interface unit 204 supplies the generated second signal to the functional unit 202 (S1109), so that the functional unit 202 can perform a bus operation with the main IP block 220 immediately after waking up the functional unit 202 in a sleep state, according to the second signal received from the interface unit 204.

Fig. 12 is a block diagram of a semiconductor system to which a semiconductor device and a method of operating the semiconductor device according to an exemplary embodiment of the inventive concept are applicable.

Referring to fig. 12, a semiconductor system to which a semiconductor device and a method of operating the semiconductor device according to an exemplary embodiment of the inventive concept are applicable includes a semiconductor device (SoC) 1, a processor 10, a memory device 20, a display device 30, a network device 40, a storage device 50, and an input/output device 60. The semiconductor device (SoC) 1, the processor 10, the memory device 20, the display device 30, the network device 40, the storage device 50, and the input/output device 60 may transmit and receive data to and from each other via the bus 70.

The IP block within the semiconductor device (SoC) 1 described in the exemplary embodiments of the inventive concept includes at least one of a memory controller controlling the memory device 20, a display controller controlling the display device 30, a network controller controlling the network device 40, a memory controller controlling the memory device 50, and an input/output controller controlling the input/output device 60. Moreover, the semiconductor system may also include additional processors that control these devices.

Fig. 13 to 15 are semiconductor systems to which semiconductor devices and methods of operating the semiconductor devices according to exemplary embodiments of the inventive concept are applicable.

Fig. 13 is a schematic diagram showing a tablet PC1200, fig. 14 is a schematic diagram showing a notebook computer 1300, and fig. 15 shows a smartphone 1400. The semiconductor device according to the exemplary embodiments of the inventive concept may be used for a tablet PC1200, a notebook computer 1300, a smart phone 1400, and the like.

It should be understood that the semiconductor device according to the exemplary embodiments of the inventive concept may also be applied to other integrated circuit devices not shown.

For example, although only the tablet PC1200, the notebook computer 1300, and the smartphone 1400 are described above as application examples of the semiconductor system of the present invention, the semiconductor system of the present invention is not limited thereto.

In exemplary embodiments of the inventive concept, the semiconductor system may be a computer, a ultra portable personal computer (UMPC), a workstation, a web book, a Personal Digital Assistant (PDA), a portable computer, a wireless handset, a mobile phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, and the like.

Examples of the inventive concept provide a semiconductor apparatus to perform a bus operation in a master-slave relationship of a system in which a clock signal is controlled by hardware.

An exemplary example of the inventive concept provides a semiconductor system for performing a bus operation in a master-slave relationship of a system in which a clock signal is controlled by hardware.

An exemplary example of the inventive concept provides a method of operating a semiconductor apparatus to perform a bus operation in a master-slave relationship of a system in which a clock signal is controlled by hardware.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.

Claims

1. A semiconductor device, comprising:

a first intellectual property block comprising a functional unit and an interface unit;

a first clock control circuit that controls the first clock source;

a second clock control circuit that sends the first clock request to the first clock control circuit and controls a second clock source that receives the clock signal from the first clock source and controls the second clock source to provide the clock signal directly to the first intellectual property block; and

a channel management circuit configured to send a second clock request to the second clock control circuit in response to a clock stop request received from the first intellectual property block,

wherein, in response to a second clock request from the channel management circuit, the second clock control circuit disables the second clock source and sends a clock supply stop request as a first clock request to the first clock control circuit,

wherein the functional unit controls operation of the first intellectual property block and the interface unit receives a first signal provided from a second intellectual property block electrically connected to the first intellectual property block and provides the first signal to the functional unit.

2. The semiconductor device according to claim 1, wherein the interface unit receives information about an operation state of the functional unit of the first intellectual property block, and

The operating state includes a sleep state or a run state.

3. The semiconductor device of claim 1, wherein the interface unit receives the first signal provided from the second intellectual property block when the functional unit of the first intellectual property block is in a sleep state.

4. The semiconductor device according to claim 3, wherein the interface unit transmits the clock stop request to the channel management circuit after receiving the first signal.

5. The semiconductor device of claim 3, wherein the interface unit generates a second signal corresponding to the first signal after the functional unit of the first intellectual property block wakes up.

6. The semiconductor device of claim 5, wherein the interface unit provides the second signal to the functional unit after the functional unit of the first intellectual property block wakes up.

7. The semiconductor device of claim 1, wherein the first intellectual property block is a slave device and the second intellectual property block is a master device.

8. The semiconductor device according to claim 1, wherein the first signal comprises a bus operation signal.

9. The semiconductor device according to claim 8, wherein the bus operation signal comprises an address signal, a data signal, or a control signal.

10. The semiconductor device of claim 8, wherein the functional unit of the first intellectual property block performs a bus operation with the second intellectual property block after receiving the first signal from the interface unit.

11. A semiconductor device, comprising:

a master intellectual property block that operates in response to a first clock signal provided from a clock management unit; and

a slave intellectual property block comprising a functional unit and an interface unit, the functional unit operating in response to a second clock signal provided directly from a second clock source of the clock management unit, and the interface unit being configured to receive the bus operation signal from the master intellectual property block at a first point in time and to provide the bus operation signal to the functional unit at a second point in time different from the first point in time,

wherein the clock management unit comprises a first clock source for providing a first clock signal and controlled by the first clock control circuit, a second clock source for providing a second clock signal and controlled by the second clock control circuit, and a third clock source for providing a third clock signal to the first clock source and the second clock source and controlled by the third clock control circuit, wherein the first clock signal and the second clock signal are based on the third clock signal,

Wherein the clock management unit further comprises a channel management circuit configured to send a second clock request to the second clock control circuit in response to a clock stop request received from the intellectual property block,

wherein, in response to a second clock request from the channel management circuit, the second clock control circuit disables the second clock source and sends a clock supply stop request to the third clock control circuit.

12. The semiconductor device according to claim 11, wherein the interface unit receives information about an operation state of the functional unit, and

the operating state includes a sleep state or a run state.

13. The semiconductor device according to claim 11, wherein the interface unit receives the bus operation signal from the main intellectual property block when the function unit is in the sleep state.

14. The semiconductor device according to claim 13, wherein the interface unit transmits the clock request to the clock management unit after receiving the bus operation signal from the main intellectual property block.

15. The semiconductor device according to claim 13, wherein the interface unit supplies the bus operation signal to the function unit at a second point in time when the function unit wakes up.

16. The semiconductor device according to claim 15, wherein the function unit performs a bus operation with the main intellectual property block after receiving the bus operation signal from the interface unit.

17. The semiconductor device according to claim 11, wherein the bus operation signal comprises an address signal, a data signal, or a control signal.

18. The semiconductor device of claim 11, wherein the master intellectual property block and the slave intellectual property blocks transmit and receive data according to an advanced peripheral bus protocol or an advanced high-performance bus protocol.

19. The semiconductor device of claim 18, wherein the primary intellectual property block comprises an advanced peripheral bus bridge block.

20. A semiconductor system, comprising:

a system-on-chip, comprising:

a second intellectual property block electrically connected to the first intellectual property block;

a first clock control circuit that controls the first clock source;

A channel management circuit that transmits a second clock request to the second clock control circuit in response to the clock stop request received from the first intellectual property block, an

One or more external devices electrically connected to the system chip,

wherein the functional unit controls operation of the first intellectual property block and the interface unit receives a first signal provided from the second intellectual property block and provides the first signal to the functional unit.