CN108258096A - LED Chips for Communication - Google Patents

Abstract

The invention provides a light-emitting diode chip, which includes a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer and a first metal electrode. The light emitting layer is disposed between the P-type semiconductor layer and the N-type semiconductor layer. The N-type semiconductor layer includes a first N-type semiconductor sub-layer, a second N-type semiconductor sub-layer and an ohmic contact layer, wherein the ohmic contact layer is disposed between the first N-type semiconductor sub-layer and the second N-type semiconductor sub-layer. The first metal electrode is disposed on the first N-type semiconductor sublayer, and the region of the first N-type semiconductor sublayer between the first metal electrode and the ohmic contact layer contains metal atoms diffused from the first metal electrode, so that the first metal electrode forms an ohmic contact with the ohmic contact layer. The light emitting diode chip of the invention has high light extraction efficiency.

Description

Light Emitting Diode Chip

technical field

The invention relates to a light-emitting element, and in particular to a light-emitting diode wafer.

Background technique

With the development of optoelectronic technology, traditional incandescent light bulbs and fluorescent tubes have been gradually replaced by a new generation of solid-state light sources such as light-emitting diodes (light-emitting diodes, LEDs), which have advantages such as long life, small size, Due to the advantages of high shock resistance, high light efficiency and low power consumption, it has been widely used as a light source in household lighting and various equipment. In addition to the backlight modules of liquid crystal displays and household lighting fixtures that have widely used light-emitting diodes as light sources, in recent years, the application fields of light-emitting diodes have expanded to road lighting, large outdoor billboards, traffic lights, UV curing and related fields. Light-emitting diodes have become one of the main projects in the development of light sources with both power saving and environmental protection functions.

In the field of LEDs, a new technology called micro-LEDs has been developed which reduces the size of the original light-emitting diode wafers a lot. When applied in the field of display technology, red, blue, and green miniature light-emitting diode chips are used as display sub-pixels, and these multiple micro-light-emitting diode chips that can emit light independently are arranged into a display screen display technology , which is the technology of micro-light-emitting diode displays.

For large-sized red light emitting diode wafers, the gallium arsenide layer on one side of the N-type semiconductor layer is used as an ohmic contact layer to increase the conductivity of the electrodes. However, because the thickness of the N-type semiconductor layer including the gallium arsenide layer is generally too thick, it is easy to cause light absorption and poor current conduction efficiency. However, when the red light-emitting diode chip is reduced to the size of micro-LEDs, the light-absorbing and poor current conduction efficiency of these N-type semiconductor layers will be more obvious, which will lead to a significant drop in the light extraction efficiency of the micro-LEDs.

Contents of the invention

The invention provides a light-emitting diode chip with high light extraction efficiency.

An embodiment of the present invention provides a light-emitting diode chip, including a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and a first metal electrode. The light emitting layer is disposed between the P-type semiconductor layer and the N-type semiconductor layer. The N-type semiconductor layer includes a first N-type semiconductor sub-layer, a second N-type semiconductor sub-layer and an ohmic contact layer, wherein the ohmic contact layer is disposed between the first N-type semiconductor sub-layer and the second N-type semiconductor sub-layer. The first metal electrode is disposed on the first N-type semiconductor sublayer, and the region of the first N-type semiconductor sublayer between the first metal electrode and the ohmic contact layer contains metal atoms diffused from the first metal electrode, so that the first metal electrode forms an ohmic contact with the ohmic contact layer.

In the light emitting diode wafer according to the embodiment of the present invention, the region of the first N-type semiconductor sublayer between the first metal electrode and the ohmic contact layer contains metal atoms diffused from the first metal electrode, so that The first metal electrode forms an ohmic contact with the ohmic contact layer. Therefore, the embodiments of the present invention can effectively reduce the thickness of the semiconductor layer so as not to absorb light, and can have better current conduction efficiency. Therefore, the light emitting diode chip of the embodiment of the present invention has higher light extraction efficiency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

1A is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present invention;

FIG. 1B is a top view of the light emitting diode wafer of FIG. 1A;

2A is a schematic cross-sectional view of a light emitting diode wafer according to another embodiment of the present invention;

FIG. 2B is a schematic top view of the light emitting diode chip of FIG. 2A;

FIG. 3 is a schematic cross-sectional view of a light emitting diode wafer according to another embodiment of the present invention.

Explanation of reference signs:

100, 100a, 100b: light emitting diode chips

110, 110b: P-type semiconductor layer

112: P-type cladding layer

114: P-type contact layer

120: luminous layer

122: Barrier layer

124: Energy well layer

130, 130a: N-type semiconductor layer

132: the first N-type semiconductor sublayer

134: Ohmic contact layer

136: the second N-type semiconductor sublayer

138: N-type cladding layer

140: first metal electrode

150: Second metal electrode

H: total thickness

M: platform area

R: area

R1, R2: One side of area R

T1, T2, T3: Thickness

W: maximum width

Detailed ways

FIG. 1A is a schematic cross-sectional view of a light emitting diode chip according to an embodiment of the present invention, and FIG. 1B is a top view of the light emitting diode chip of FIG. 1A . Referring to FIG. 1A and FIG. 1B , the light emitting diode chip 100 of this embodiment includes a P-type semiconductor layer 110 , a light emitting layer 120 , an N-type semiconductor layer 130 and a first metal electrode 140 . Here, the light emitting layer 120 is used to emit red light, and the light emitting layer 120 is disposed between the P-type semiconductor layer 110 and the N-type semiconductor layer 130 . In this embodiment, the light-emitting layer 120 is, for example, a multiple quantum well layer (multiple quantum well), which includes alternately stacked energy barrier layers 122 and energy well layers 124 . In this embodiment, the energy barrier layer 122 and the energy well layer 124 are both aluminum gallium indium phosphide layers, but the mole percentages of aluminum and gallium contained in the energy barrier layer 122 are different from those contained in the energy well layer 124. Mole percent of aluminum to gallium. In this embodiment, the chemical formula of the material of the energy barrier layer 122 is, for example, (Al _x Ga _1-x ) _0.5 In _0.5 P, and the chemical formula of the material of the energy well layer 124 is, for example, ( _Aly Ga _1-y ) _0.5 In _0.5 P, where 0<x, y<1.

The N-type semiconductor layer 130 includes a first N-type semiconductor sublayer 132, a second N-type semiconductor sublayer 136, and an ohmic contact layer 134, wherein the ohmic contact layer 134 is configured between the first N-type semiconductor sublayer 132 and the second N-type semiconductor sublayer 132. between sublayers 136 . For example, the material of the first N-type semiconductor sub-layer 132 is (Al _z Ga _1-z ) _0.5 In _{0.5 P doped with silicon, and the material of the second N-type semiconductor sub-layer 136 is (Al z Ga 1-z ) 0.5 In 0.5} P doped with silicon, for example. Al _a Ga _1-a ) _0.5 In _0.5 P, where 0<z≤1, and 0<a≤1. In this embodiment, the material of the first N-type semiconductor sub-layer 132 and the second N-type semiconductor sub-layer 136 is, for example, aluminum gallium indium phosphide. In addition, in this embodiment, the material of the ohmic contact layer 134 is N-type GaAs, for example, an N-type GaAs layer doped with silicon. Preferably, the thickness T1 of the ohmic contact layer 134 is less than or equal to 60 nanometers, and the thicknesses T2 and T3 of the first N-type semiconductor sublayer 132 and the second N-type semiconductor sublayer 136 are both less than or equal to 1.3 microns, which can effectively reduce the ohmic contact. The amount of light absorbed by the layer 134 , the first N-type semiconductor sub-layer 132 and the second N-type semiconductor sub-layer 136 on the light emitted by the light-emitting layer 120 .

The first metal electrode 140 is disposed on the first N-type semiconductor sub-layer 132, and the region R between the first metal electrode 140 and the ohmic contact layer 134 of the first N-type semiconductor sub-layer 132 contains the first metal electrode 140. Diffused metal atoms, so that the first metal electrode 140 forms an ohmic contact with the ohmic contact layer 134. Since the ohmic contact layer 134 is a gallium arsenide layer with a relatively small band gap (Band Gap), the diffusion of the metal atoms allows the The first metal electrode 140 forms a better ohmic contact with the ohmic contact layer 134 , so that the LED chip 100 has better current conduction efficiency. In particular, before forming the light-emitting diode wafer 100, a buffer layer (not shown), an N-type semiconductor layer 130, a light-emitting layer 120, and a P-type semiconductor layer 110 will be formed on a growth substrate (not shown). The growth substrate (not shown) and the buffer layer (not shown) are removed by, for example, an etching process to form the LED wafer 100 . Because the thickness of the ohmic contact layer 134 is relatively thin, the second N-type semiconductor sub-layer 136 can be used as a protective buffer layer for the ohmic contact layer 134 during the etching process, so as to prevent the ohmic contact layer 134 as an ohmic contact from being damaged. Metal atoms diffused from a metal electrode 140 make the first metal electrode 140 form an ohmic contact with the ohmic contact layer 134 . In addition, the surface of the second N-type semiconductor sub-layer 136 can also be roughened during the manufacturing process to increase light output. Here, the concentration of the metal atoms on the side R1 of the region R close to the ohmic contact layer 134 is smaller than the concentration of metal atoms on the side R1 of the region R away from the ohmic contact layer 134 . In the process, the first metal electrode 140 can be formed on the first N-type semiconductor sub-layer 132 first, and then heated at a high temperature (for example, the process temperature falls within the range of 300° C. to 500° C.) The metal atoms in the electrode 140 diffuse into the region R, so that the first metal electrode 140 forms an ohmic contact with the ohmic contact layer 134 , as shown in FIG. 1B . In particular, the first N-type semiconductor sublayer 132, the contact layer 134, and the second N-type semiconductor sublayer 136 all contain metal atoms diffused from the first metal electrode, so that the first The metal electrode 140 and the ohmic contact layer 134 form better current conduction efficiency. In this embodiment, the material of the first metal electrode 140 is, for example, gold, germanium, nickel or an alloy of any combination of the above metals.

In this embodiment, the N-type semiconductor layer 130 further includes an N-type cladding layer (n-type cladding layer) 138, which is disposed between the ohmic contact layer 134 and the light-emitting layer 120, and the material of the N-type cladding layer 130 is ( Al _b Ga _1-b ) _0.5 In _0.5 P, wherein 0<b≦1, where the N-type cladding layer 138 is, for example, silicon-doped aluminum gallium indium phosphide, but not limited thereto. In this embodiment, the N-type cladding layer 138 is disposed between the first N-type semiconductor sub-layer 132 and the light-emitting layer 120, and the first N-type semiconductor sub-layer 132 is disposed between the N-type cladding layer 138 and the ohmic contact layer. Between 134.

In this embodiment, the P-type semiconductor layer 110 includes a P-type cladding layer 112, and the material of the P-type cladding layer 112 is aluminum indium phosphide, such as Al0.5In0.5P doped with magnesium. In addition, in this embodiment, the LED chip 100 further includes a second metal electrode 150, wherein the P-type semiconductor layer 110 further includes a P-type contact layer 114 doped with carbon, which is disposed between the P-type cladding layer 112 and the second metal electrode 150. between the two metal electrodes 150 . In this embodiment, the P-type cladding layer 112 is disposed between the P-type contact layer 114 and the light emitting layer 120 . The material of the P-type contact layer 114 is, for example, a carbon-doped P-type gallium phosphide layer, and the P-type contact layer 114 is less than or equal to 1 micron, which can be thinned and have better current conduction. In particular, the ratio obtained by dividing the thickness of the P-type semiconductor layer 110 by the total thickness of all semiconductor layers of the light-emitting diode wafer 100 falls within the range of 0.05 to 0.2, and due to the carbon-doped P-type contact The layer 114 has a better current spreading effect, so the light-emitting diode chip 100 can be thinned and have good light extraction efficiency. In this embodiment, the material of the second metal electrode 150 is, for example, gold, germanium, nickel or an alloy of any combination of the above metals.

In this embodiment, as shown in FIG. 1B , the ratio obtained by dividing the total thickness H of all semiconductor layers of the LED wafer 100 by the maximum width W of the LED wafer 100 falls within the range of 0.2 to 1.5. In other words, the size of the light emitting diode chip 100 can be small, such as the size of micro light emitting diodes. In one embodiment, the maximum width W falls within a range of 1 micron to 100 microns, for example. Smaller dimensions are possible compared to known LED wafers.

In the light-emitting diode wafer 100 of this embodiment, the region R of the first N-type semiconductor sub-layer 132 between the first metal electrode 140 and the ohmic contact layer 134 contains metal atoms, so that the first metal electrode 140 forms an ohmic contact with the ohmic contact layer 134 . Therefore, the light-emitting diode chip 100 of the embodiment of the present invention has higher light extraction efficiency, and this advantage is more significant when the size of the light-emitting diode chip 100 is small (for example, when it is the size of a miniature light-emitting diode) .

In addition, in the light-emitting diode chip 100 of this embodiment, the P-type semiconductor layer 110 is located in the raised platform (mesa) region M on the chip. Polar wafer 100) is set in the same way as blue light and green light emitting diode wafers (its P-type semiconductor layer is generally all located in the platform area), which makes the manufacturing process of the micro light emitting diode display easier and more effective. Reduce production costs.

FIG. 2A is a schematic cross-sectional view of a light-emitting diode chip according to another embodiment of the present invention, and FIG. 2B is a schematic top view of the light-emitting diode chip in FIG. 2A . The light emitting diode chip 100 a of this embodiment is similar to the light emitting diode chip 100 of FIG. 1A , and the main differences between the two are as follows. In FIG. 1A, the first metal electrode 140 and the second metal electrode 150 are disposed on the same side of the light-emitting diode chip 100, but in this embodiment, the first metal electrode 140 and the second metal electrode 150 are respectively disposed on opposite sides of the light emitting diode wafer 100a. In other words, the LED chip 100 in FIG. 1A is a horizontal LED chip, and the LED chip 100 a in FIG. 2A is a vertical LED chip. In addition, in this embodiment, the N-type cladding layer 138 of the N-type semiconductor layer 130a is disposed between the second N-type semiconductor sub-layer 136 and the light-emitting layer 120, and the second N-type semiconductor sub-layer 136 is disposed on the N-type between the cladding layer 138 and the ohmic contact layer 134 . In this embodiment, as shown in FIG. 2B , the ratio obtained by dividing the total thickness H of all semiconductor layers of the LED wafer 100 by the maximum width W of the LED wafer 100 falls within the range of 0.2 to 1.5. In other words, the size of the LED chip 100 can be smaller. In particular, at this time, the first N-type semiconductor sublayer 132 can be used as a protective buffer layer for the ohmic contact layer 134 during the etching process, so as to prevent the ohmic contact layer 134 serving as an ohmic contact from being damaged.

FIG. 3 is a schematic cross-sectional view of a light emitting diode wafer according to another embodiment of the present invention. Referring to FIG. 3 , the light emitting diode chip 100 b of this embodiment is similar to the light emitting diode chip 100 of FIG. 1A , and the main differences between the two are as follows. In the light-emitting diode wafer 100 of FIG. 1A, the P-type semiconductor layer 110 is located in the platform area M raised on the wafer, while in the light-emitting diode wafer 100b of this embodiment, the N-type semiconductor layer 130 is located in In the raised platform region M on the wafer. In addition, the second metal electrode 150 can be disposed on the P-type contact layer 114 of the P-type semiconductor layer 110b.

To sum up, in the light-emitting diode wafer according to the embodiment of the present invention, the region between the first metal electrode and the ohmic contact layer of the first N-type semiconductor sublayer contains metal atoms, so that the first metal electrode forms an ohmic contact with the ohmic contact layer. Therefore, the embodiments of the present invention can effectively reduce the thickness of the semiconductor layer so as not to absorb light, and can have better current conduction efficiency. Therefore, the light emitting diode chip of the embodiment of the present invention has higher light extraction efficiency.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the claims.

Claims (11)

1. a kind of LED Chips for Communication, which is characterized in that including：

P type semiconductor layer；

Luminescent layer；

N type semiconductor layer, the luminescent layer are configured between the p type semiconductor layer and the n type semiconductor layer, the n type semiconductor layer Including：

First N-type semiconductor sublayer；

Second N-type semiconductor sublayer；And

Ohmic contact layer is configured between the first N-type semiconductor sublayer and the second N-type semiconductor sublayer；And

First metal electrode is configured in the first N-type semiconductor sublayer, and wherein being located at for the first N-type semiconductor sublayer should Contain the metallic atom spread from first metal electrode in region between first metal electrode and the ohmic contact layer, So that first metal electrode forms Ohmic contact with the ohmic contact layer.

2. LED Chips for Communication according to claim 1, which is characterized in that the metallic atom should in the close of the region The concentration of the side of ohmic contact layer is less than the concentration of the side far from the ohmic contact layer in the region.

3. LED Chips for Communication according to claim 1, which is characterized in that the thickness of the ohmic contact layer is less than or equal to 60 nanometers.

4. LED Chips for Communication according to claim 1, which is characterized in that the ohmic contact layer is n type gaas layer.

5. LED Chips for Communication according to claim 1, which is characterized in that the first N-type semiconductor sublayer with this The material of two N-type semiconductor sublayers is AlGaInP.

6. LED Chips for Communication according to claim 1, which is characterized in that the n type semiconductor layer further includes N-type coating Layer, is configured between the first N-type semiconductor sublayer and the luminescent layer, and the first N-type semiconductor sublayer is configured at the N-type and drapes over one's shoulders Between coating and the ohmic contact layer.

7. LED Chips for Communication according to claim 1, which is characterized in that the n type semiconductor layer further includes N-type coating Layer, is configured between the second N-type semiconductor sublayer and the luminescent layer, and the second N-type semiconductor sublayer is configured at the N-type and drapes over one's shoulders Between coating and the ohmic contact layer.

8. LED Chips for Communication according to claim 1, which is characterized in that all of the LED Chips for Communication partly lead The overall thickness of body layer divided by the obtained ratio of the maximum width of the LED Chips for Communication are fallen in the range of 0.2 to 1.5.

9. LED Chips for Communication according to claim 1, which is characterized in that the thickness of the p type semiconductor layer divided by should The obtained ratio of overall thickness of all semiconductor layers of LED Chips for Communication is fallen in the range of 0.05 to 0.2.

10. LED Chips for Communication according to claim 9, which is characterized in that the p type semiconductor layer includes p-type coating The p-type contact layer of layer and doped carbon, and the p-type coating layer is configured between the p-type contact layer and the luminescent layer.

11. LED Chips for Communication according to claim 1, which is characterized in that the first N-type semiconductor sublayer, the Europe Nurse contact layer is with the second N-type semiconductor sublayer all containing the metallic atom spread from first metal electrode.