CN108257968A - A kind of no pn junction p n trench gate array memory structure and preparation method thereof - Google Patents

Abstract

The invention provides a junctionless semiconductor trench gate array memory structure and a preparation method thereof, the structure comprising: a semiconductor substrate; an insulating layer located on the semiconductor substrate; a carbon nanotube grid located on the insulating layer array; a grid charge trapping structure located on the grid array of carbon nanotubes; a semiconductor channel using a two-dimensional semiconductor material located on the grid charge trapping structure; and located at both ends of the grid array of carbon nanotubes, and a source contact electrode and a drain contact electrode respectively connected to the semiconductor channel. The memory structure of the present invention replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, and uses a metal carbon nanotube grid array, which improves the gate charge trapping performance, simplifies the device structure, and can further increase the memory array density. .

Description

A junctionless semiconductor trench gate array memory structure and its preparation method

technical field

The invention relates to the technical field of integrated circuits, in particular to a junctionless semiconductor trench gate array memory structure and a preparation method thereof.

Background technique

For NAND memories with different architectures, they can be divided into three-dimensional floating gate memories and three-dimensional charge trap memories according to the material of the storage layer. For the former three-dimensional floating gate memory, because the polysilicon floating gate is used as the storage layer, the area of the storage unit is larger, and it is more difficult to realize the stacking of more layers of storage units. Therefore, the area is mainly realized by placing the peripheral circuit under the storage array. reduction. For the latter three-dimensional charge trap memory, it can be divided into vertical gate type and vertical channel type. The three-dimensional charge-trapping flash memory structure based on the vertical gate structure is more difficult in process than the vertical channel type, and mass production has not been announced. Vertical channel three-dimensional charge-trapping memory is the first flash memory product to be mass-produced. In August 2013, Samsung Electronics launched the first generation of 24-layer three-dimensional vertical channel charge-trapping three-dimensional memory. In July 2014, it launched The second-generation 32-layer 128Gb product was launched in 2015 with a 48-layer 256Gb product.

The vertical channel type three-dimensional charge-trapping flash memory launched by Samsung Electronics uses a vertical polysilicon cylinder as a channel, multi-layer gates surround the polysilicon cylinder, and each layer of gates serves as a layer of word lines, so that word lines become Horizontal layers, bitlines are connected on top of vertical polysilicon cylinders. The common source lines are drawn out one by one by making heavily doped regions on the substrate. The gate is stored in the way of charge trapping, and a tunneling layer, a charge trapping layer and a blocking layer are arranged between the polysilicon channel and the gate metal. For specific device structure descriptions, reference may be made to the patent document with the patent publication number CN104425511A.

The key technologies of this vertical channel type three-dimensional charge-trapping flash memory are ultra-deep hole etching and high-quality thin film process. The aspect ratio of the 32-layer ultra-deep hole is close to 30:1, and the diameter difference between the upper and lower holes is required to be less than 10-20nm. The gate dielectric multilayer film not only requires the thickness of the top layer and the bottom layer to be basically the same, but also puts forward high requirements for the uniformity of the composition. The channel material is generally a polysilicon thin film, which requires good crystallinity and large crystal grains, and also requires an interface with a low defect density with the gate dielectric. As a charge trap memory, there is almost no coupling effect between memory cells. Program and erase operations use FN tunneling of electrons and holes, respectively. In order to increase the erasing speed, the tunneling layer usually uses a stacked structure based on silicon oxide and silicon oxynitride materials. The storage layer is generally made of silicon nitride-based high trap density material. In order to reduce gate reverse implantation, materials such as silicon oxide or aluminum oxide are used for the barrier layer.

However, in the existing vertical channel type three-dimensional charge trapping memory, the device channel material adopts polysilicon film, which requires good crystallinity and large crystal grains, and at the same time requires the thickness of the polysilicon film channel to be as thin as possible. Difficult to balance, affecting product yield.

Contents of the invention

In view of the prior art described above, the object of the present invention is to provide a junctionless semiconductor trench gate array memory structure and a manufacturing method thereof, which are used to solve various problems in the prior art.

In order to achieve the above object and other related objects, the present invention provides a junctionless semiconductor trench gate array memory structure, including:

semiconductor substrate;

an insulating layer located on the semiconductor substrate;

A carbon nanotube grid array, located on the insulating layer, including a plurality of carbon nanotubes arranged in an array as grid electrodes;

The gate charge trapping structure is located on the grid array of carbon nanotubes, and includes a blocking layer, a charge trapping layer and a tunnel layer from bottom to top, wherein the blocking layer covers the surface of each carbon nanotube;

A semiconductor channel, located on the gate charge trapping structure, adopts a two-dimensional semiconductor material;

The source contact electrode and the drain contact electrode are respectively located at two ends of the carbon nanotube grid array, and are respectively connected to the semiconductor channel.

Optionally, the junctionless semiconductor trench gate array memory structure further includes a plurality of gate contact electrodes respectively leading out the plurality of carbon nanotubes.

Optionally, the semiconductor substrate is a silicon substrate.

Optionally, the insulating layer is silicon oxide.

Optionally, the carbon nanotube grid array adopts metallic carbon nanotubes, and each carbon nanotube has a diameter of 0.75-3 nm and a length of 100 nm-50 μm.

Optionally, in the gate charge trapping structure, the barrier layer is made of ZrO ₂ , and the tunnel layer is made of ZrO ₂ .

Optionally, in the gate charge trapping structure, the material of the charge trapping layer is nitride.

Optionally, the two-dimensional semiconductor material used in the semiconductor channel is MoS ₂ , WS ₂ , ReS ₂ or SnO.

Optionally, the surface of the semiconductor channel is covered with a passivation layer.

Optionally, the junctionless semiconductor trench grid array memory structure includes a plurality of semiconductor channels, each of which corresponds to a group of memory cell strings; the carbon nanotube grid array includes multiple groups of Multiple groups of carbon nanotubes in memory cell strings; the carbon nanotubes in each group of memory cell strings are arranged under the corresponding semiconductor channel, including a plurality of word line gate carbon nanotubes, string selection gate carbon nanotubes and ground selection Gate carbon nanotubes, wherein the string select gate carbon nanotubes and the ground select gate carbon nanotubes are respectively located at two ends of a plurality of word line gate carbon nanotubes.

In order to achieve the above object and other related objects, the present invention also provides a method for preparing a junctionless semiconductor trench gate array memory structure, comprising the following steps:

Provide semiconductor substrates;

forming an insulating layer on the semiconductor substrate;

A carbon nanotube grid array is formed on the insulating layer, and the carbon nanotube grid array includes a plurality of carbon nanotubes arranged in an array as grid electrodes;

Forming a gate charge trapping structure on the plurality of carbon nanotubes, the gate charge trapping structure sequentially includes a blocking layer, a charge trapping layer and a tunnel layer from bottom to top, wherein the blocking layer covers the surface of each carbon nanotube;

using a two-dimensional semiconductor material to form a semiconductor channel on the gate charge trapping structure;

covering the semiconductor channel with a passivation layer;

A source contact electrode and a drain contact electrode respectively located at both ends of the carbon nanotube grid array and connected to the semiconductor channel, and a plurality of gate contact electrodes respectively leading out the plurality of carbon nanotubes are formed.

Optionally, when two-dimensional semiconductor materials are used to form semiconductor channels on the gate charge trapping structure, multiple semiconductor channels are formed simultaneously.

Further optionally, when forming a plurality of carbon nanotubes of a carbon nanotube grid array, arrange multiple groups of carbon nanotubes according to the positions of the plurality of semiconductor channels, so that each group of carbon nanotubes is located between the corresponding semiconductor channels Down.

Optionally, the method for forming the source contact electrode and the drain contact electrode includes the steps of: respectively etching the surface passivation layer above the two ends of the carbon nanotube grid array to form an opening to expose the top of the semiconductor channel, and then A conductive material is filled in the opening to form a source contact electrode and a drain contact electrode.

Optionally, the method for forming a plurality of gate contact electrodes includes the steps of: forming a plurality of through holes by etching to respectively expose the plurality of carbon nanotubes, and then filling the through holes with a conductive material to form a plurality of gate contact electrodes .

As mentioned above, the junctionless semiconductor trench gate array memory structure and its preparation method of the present invention have the following beneficial effects:

In the junctionless semiconductor channel gate array memory structure of the present invention, the storage unit adopts the gate charge trapping method, and replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, which makes the charge easier to control and improves the gate charge trapping. performance, the metal carbon nanotube grid array is used, which significantly reduces the gate size. Compared with the existing vertical channel NAND structure, the present invention further improves the device performance, further simplifies the device structure, and improves the storage array density. be increased.

Description of drawings

FIG. 1 shows a schematic diagram of a junctionless semiconductor trench gate array memory structure provided by an embodiment of the present invention.

2a-2g are schematic diagrams showing the fabrication process of the junctionless semiconductor trench gate array memory structure provided by the embodiment of the present invention.

Component designation description

100 semiconductor substrate

200 insulation

300 carbon nanotube grid array

301 carbon nanotubes

302 Gate Contact Electrode

400 gate charge trapping structure

401 barrier

402 charge trapping layer

403 tunnel layer

500 semiconductor channel

501 passivation layer

600 source contact electrodes

700 Drain Contact Electrode

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic ideas of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

This embodiment will provide a storage structure and a preparation method that can be applied to a NAND flash memory. The storage structure of the NAND memory includes a storage array, and the storage array may be composed of multiple groups of storage cell strings. Each group of memory cell strings in this embodiment adopts a form in which a plurality of gate junction-less switching transistors share a horizontal channel. Transistors, a plurality of gate-controlled charge-trap memory cells whose gates are respectively connected to a plurality of word lines (WL), and string selection transistors whose gates are connected to string selection lines (SSL). The gate electrodes of these gate-less junction switching transistors are made of metal carbon nanotubes, which are arranged in a gate electrode array in the horizontal direction. The gate dielectric layer adopts a dielectric charge trapping structure, and the common horizontal channel is replaced by a two-dimensional semiconductor material. Traditional silicon doping materials, thereby improving the gate charge trapping performance and simplifying the device structure.

Please refer to FIG. 1, a junctionless semiconductor trench gate array memory structure provided in this embodiment specifically includes:

a semiconductor substrate 100;

an insulating layer 200 located on the semiconductor substrate 100;

A carbon nanotube grid array 300, located on the insulating layer 200, including a plurality of carbon nanotubes 301 as grid electrodes arranged in an array;

The gate charge trapping structure 400 is located on the carbon nanotube grid array 300, and includes a barrier layer 401, a charge trapping layer 402 and a tunnel layer 403 from bottom to top, wherein the barrier layer 401 covers the carbon nanotube 301 surface;

A semiconductor channel 500, located on the gate charge trapping structure 400, adopts a two-dimensional semiconductor material;

The source contact electrode 600 and the drain contact electrode 700 are respectively located at two ends of the carbon nanotube grid array 300 and connected to the semiconductor channel 500 respectively.

Specifically, the junctionless semiconductor trench gate array memory structure further includes a plurality of gate contact electrodes 302 leading out the plurality of carbon nanotubes 301 .

In this embodiment, the semiconductor substrate 100 may be a silicon substrate or other suitable semiconductor material substrates. The insulating layer 200 may be silicon oxide or other suitable insulating materials.

In this embodiment, the carbon nanotube grid array 300 uses metallic carbon nanotubes, and each carbon nanotube 301 has a diameter of 0.75-3 nm and a length of 100 nm-50 μm.

In this embodiment, the gate charge trapping structure 400 is made of insulating material. Wherein, the material of the blocking layer 401 may be ZrO ₂ , the material of the tunnel layer 403 may be ZrO ₂ , and the material of the charge trapping layer 402 may be nitride or other suitable charge trapping materials. Specifically, the thickness of the gate charge trapping structure 400 may be 2-50 nm.

In this embodiment, the two-dimensional semiconductor material used in the semiconductor channel 500 may be MoS ₂ , WS ₂ , ReS ₂ , SnO and other materials.

In this embodiment, the surface of the semiconductor channel 500 is covered with a passivation layer 501 . Specifically, the material of the passivation layer 501 may be an insulating material such as silicon oxide, silicon nitride or silicon oxynitride. The thickness of the passivation layer 501 can be designed according to actual needs, and should completely cover and cover the surface of the semiconductor channel 500 to realize the isolation of the semiconductor channel 500 from the surrounding environment.

In this embodiment, in order to form a memory array, there may be multiple semiconductor channels 500, and each semiconductor channel 500 corresponds to a group of memory cell strings; the carbon nanotube grid array 300 may include multiple groups of memory cells respectively A plurality of groups of carbon nanotubes 301 in a string; the carbon nanotubes 301 of each group of memory cell strings are arranged under the corresponding semiconductor channel 500, including a plurality of word line gate carbon nanotubes, string selection gate carbon nanotubes and ground The selection gate carbon nanotubes, wherein the string selection gate carbon nanotubes and the ground selection gate carbon nanotubes are respectively located at two ends of a plurality of word line gate carbon nanotubes. The width of each semiconductor channel 500 may be 2-50 nm. A dielectric material may be filled between the plurality of semiconductor channels 500 , such as using a passivation layer 501 to achieve isolation. The number of carbon nanotubes 301 in each group of memory cell strings can be designed according to actual needs, for example, one string select gate carbon nanotube and one ground select gate carbon nanotube, and the number of word line gate carbon nanotubes It can be 24, 32, 48, or even more.

The main difference between the junctionless semiconductor trench gate array memory structure provided in this embodiment and the vertical channel NAND structure in the prior art is that the memory structure of this embodiment adopts a horizontal channel, and the gate charge trapping structure serves as a gate at the same time. The dielectric layer is located above the horizontal channel, and the gate electrodes are arranged in an array in the horizontal direction. Such a device structure is simpler; since the memory cell adopts the gate charge trapping method, in order to improve the gate charge trapping performance of the device, a The two-dimensional semiconductor material replaces the traditional silicon-doped material as the channel, and uses carbon nanotubes as the gate electrode array, so that the conductivity of the channel is easier to control, which can reduce the size of the gate, increase the density of the storage array, and make the storage device Performance has been further improved. However, the prior art adopts a vertical channel structure, and the channel structure is relatively complex, usually including multi-layer thin films, and an insulating buried layer may be provided in the middle of the channel structure. The vertical channel usually adopts polysilicon thin film, which requires good crystallinity and large crystal grains. At the same time, the thickness of the polysilicon thin film channel is required to be as thin as possible, so it is difficult to balance the process. Therefore, compared with the existing vertical channel NAND, the junctionless semiconductor trench gate array memory structure provided by this embodiment has a simpler structure, and the performance of the device is also significantly improved.

The method for fabricating the junctionless semiconductor trench gate array memory structure provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings.

Please refer to FIGS. 2a-2g. This embodiment provides a method for fabricating a junctionless semiconductor trench gate array memory structure, including the following steps:

First, as shown in FIG. 2a, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be any suitable semiconductor material, for example, a silicon substrate may be used.

As shown in FIG. 2 b , an insulating layer 200 is formed on the semiconductor substrate 100 . The insulating layer 200 may be silicon oxide or other suitable insulating materials. For example, the insulating layer 200 may be formed by growing an oxide layer on a silicon substrate.

As shown in FIG. 2 c , a carbon nanotube grid array 300 is formed on the insulating layer 200 , and the carbon nanotube grid array 300 includes a plurality of carbon nanotubes 301 as grid electrodes arranged in an array. The diameter of each carbon nanotube 301 may range from 0.75 to 3 nm, and the length may range from 100 nm to 50 μm. Preferably, metallic carbon nanotubes are used. The method of forming the plurality of carbon nanotubes 301 may be arc method, laser evaporation method, chemical vapor deposition method, pyrolysis polymerization method and the like.

As shown in FIG. 2d, a gate charge trapping structure 400 is formed on the plurality of carbon nanotubes 301, and the gate charge trapping structure 400 includes a blocking layer 401, a charge trapping layer 402, and a tunnel layer 403 from bottom to top, wherein the The barrier layer 401 covers the surface of each carbon nanotube 301 . In this embodiment, the material of the blocking layer 401 may be ZrO ₂ , the material of the tunnel layer 403 may be ZrO ₂ , and the material of the charge trapping layer 402 may be nitride or other suitable charge trapping materials. The method for forming the gate charge trapping structure 400 may be selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE) One or more of them, or other suitable processes. The formed gate charge trapping structure 400 may have a thickness of 2-50 nm.

As shown in FIG. 2 e , a semiconductor channel 500 is formed on the gate charge trapping structure 400 using a two-dimensional semiconductor material. The two-dimensional semiconductor material used in the semiconductor channel 500 may be MoS ₂ , WS ₂ , ReS ₂ , SnO and other materials. The method for forming the semiconductor channel 500 may be deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable processes .

Then, as shown in FIG. 2 f , a passivation layer 501 is covered on the semiconductor channel 500 . Specifically, the material of the passivation layer 501 may be a dielectric material such as silicon oxide, silicon nitride or silicon oxynitride. The thickness of the passivation layer 501 can be designed according to actual needs. The passivation layer 501 should completely wrap and cover the surface of the semiconductor channel 500 to realize the isolation of the semiconductor channel 500 from the surrounding environment. The method for forming the passivation layer 501 may be selected from one or more of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, atomic layer deposition or other suitable processes.

Finally, as shown in FIG. 2g, a source contact electrode 600 and a drain contact electrode 700 respectively located at both ends of the carbon nanotube grid array 300 and connected to the semiconductor channel 500 are formed, and the plurality of carbon nanotubes are drawn out respectively. A plurality of gate contact electrodes 302 of 301 .

Specifically, the method for forming the source contact electrode 600 and the drain contact electrode 700 may include the step of: respectively etching the surface passivation layer 501 above the two ends of the carbon nanotube grid array 300 to form an opening to expose the semiconductor channel 500, and then fill the opening with a conductive material to form a source contact electrode 600 and a drain contact electrode 700. The method for forming a plurality of gate contact electrodes 302 may include the steps of: forming a plurality of through holes by etching to respectively expose the plurality of carbon nanotubes 301, and then filling the through holes with a conductive material to form a plurality of gate contact electrodes 302 . When the gate contact electrode 302 is drawn out, only the active region of the semiconductor channel needs to be avoided, and there is no need to avoid material layers such as charge trapping. The method for forming the via holes or openings may be dry etching, atomic layer etching (ALE) or other suitable methods. The gate contact electrode 302 , the source contact electrode 600 and the drain contact electrode 700 can be made of conductive materials such as Ti, Al, Ni, Au, or other suitable metal contact materials and structures.

In this embodiment, when two-dimensional semiconductor material is used to form the semiconductor channel 500 on the gate charge trapping structure 400, multiple semiconductor channels 500 can be formed simultaneously. A plurality of semiconductor channels 500 may be arranged in an array. The width of each semiconductor channel 500 may be 2-50 nm. A dielectric material, such as a passivation layer 501 , can be filled between the plurality of semiconductor channels 500 to realize isolation. When forming a plurality of carbon nanotubes 301 of the carbon nanotube grid array 300, multiple groups of carbon nanotubes 301 can be arranged in advance according to the positions of the plurality of semiconductor channels 500 to be formed, so that the carbon nanotubes 301 of each group of memory cell strings arranged under the corresponding semiconductor channel 500 . The number of carbon nanotubes 301 in each group of memory cell strings can be designed according to actual needs, for example, one string select gate carbon nanotube and one ground select gate carbon nanotube, and the number of word line gate carbon nanotubes It can be 24, 32, 48 or more.

In summary, in the junctionless semiconductor trench gate array memory structure of the present invention, the storage unit adopts the gate charge trapping method, and replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, which makes the charge easier to control and improves The gate charge trapping performance is improved, and the metal carbon nanotube grid array is used to significantly reduce the gate size. Compared with the existing vertical channel NAND structure, the invention further improves the device performance and the device structure. Simplification, storage array density can be increased. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (15)

1. A junctionless semiconductor trench gate array memory structure, characterized in that it comprises: semiconductor substrate; an insulating layer located on the semiconductor substrate; A carbon nanotube grid array, located on the insulating layer, including a plurality of carbon nanotubes arranged in an array as grid electrodes; The gate charge trapping structure is located on the grid array of carbon nanotubes, and includes a blocking layer, a charge trapping layer and a tunnel layer from bottom to top, wherein the blocking layer covers the surface of each carbon nanotube; A semiconductor channel, located on the gate charge trapping structure, adopts a two-dimensional semiconductor material; The source contact electrode and the drain contact electrode are respectively located at two ends of the carbon nanotube grid array, and are respectively connected to the semiconductor channel. 2 . The junctionless semiconductor trench gate array memory structure according to claim 1 , further comprising a plurality of gate contact electrodes respectively leading out the plurality of carbon nanotubes. 3 . 3. The junctionless semiconductor trench gate array memory structure according to claim 1, wherein the semiconductor substrate is a silicon substrate. 4. The junctionless semiconductor trench gate array memory structure according to claim 1, wherein the insulating layer is silicon oxide. 5. The junctionless semiconductor trench grid array memory structure according to claim 1, characterized in that: the carbon nanotube grid array adopts metallic carbon nanotubes, and the diameter of each carbon nanotube is 0.75-3nm. The length is 100 nm to 50 μm. 6. The junctionless semiconductor trench gate array memory structure according to claim 1, characterized in that: in the gate charge trapping structure, the material of the barrier layer is ZrO ₂ , and the material of the tunnel layer is ZrO ₂ . 7. The junctionless semiconductor trench gate array memory structure according to claim 1, characterized in that: in the gate charge trapping structure, the material of the charge trapping layer is nitride. 8 . The junctionless semiconductor trench gate array memory structure according to claim 1 , wherein the two-dimensional semiconductor material used in the semiconductor trench is MoS ₂ , WS ₂ , ReS ₂ or SnO. 9 . The junctionless semiconductor trench gate array memory structure according to claim 1 , wherein the surface of the semiconductor trench is covered with a passivation layer. 10. The junctionless semiconductor trench gate array memory structure according to claim 1, characterized in that: the junctionless semiconductor trench gate array memory structure comprises a plurality of semiconductor channels, each of which is Corresponding to a group of memory cell strings; the carbon nanotube grid array includes multiple groups of carbon nanotubes corresponding to multiple groups of memory cell strings; the carbon nanotubes of each group of memory cell strings are arranged under the corresponding semiconductor channel, including multiple word line grid carbon nanotubes, string selection grid carbon nanotubes and ground selection grid carbon nanotubes, wherein the string selection grid carbon nanotubes and ground selection grid carbon nanotubes are respectively located in a plurality of word line grids two ends of carbon nanotubes. 11. A method for preparing a junctionless semiconductor trench gate array memory structure, characterized in that the method comprises the following steps: Provide semiconductor substrates; forming an insulating layer on the semiconductor substrate; A carbon nanotube grid array is formed on the insulating layer, and the carbon nanotube grid array includes a plurality of carbon nanotubes arranged in an array as grid electrodes; Forming a gate charge trapping structure on the plurality of carbon nanotubes, the gate charge trapping structure sequentially includes a blocking layer, a charge trapping layer and a tunnel layer from bottom to top, wherein the blocking layer covers the surface of each carbon nanotube; using a two-dimensional semiconductor material to form a semiconductor channel on the gate charge trapping structure; covering the semiconductor channel with a passivation layer; A source contact electrode and a drain contact electrode respectively located at both ends of the carbon nanotube grid array and connected to the semiconductor channel, and a plurality of gate contact electrodes respectively leading out the plurality of carbon nanotubes are formed. 12. The method for fabricating a junctionless semiconductor channel gate array memory structure according to claim 11, characterized in that: when two-dimensional semiconductor materials are used to form semiconductor channels on the gate charge trapping structure, multiple semiconductor channels are simultaneously formed. ditch. 13. The method for preparing a junctionless semiconductor channel gate array memory structure according to claim 12, characterized in that: when forming a plurality of carbon nanotubes in the carbon nanotube grid array, according to the positions of the plurality of semiconductor channels Multiple groups of carbon nanotubes are arranged so that each group of carbon nanotubes is located under the corresponding semiconductor channel. 14. The method for preparing a junctionless semiconductor trench gate array memory structure according to claim 11, characterized in that: the method for forming the source contact electrode and the drain contact electrode comprises the steps of: respectively forming the carbon nanotube grid array Etching the surface passivation layer above the two ends to form an opening to expose the top of the semiconductor channel, and then filling the opening with a conductive material to form a source contact electrode and a drain contact electrode. 15. The method for fabricating a junctionless semiconductor trench gate array memory structure according to claim 11, characterized in that: the method for forming a plurality of gate contact electrodes comprises the step of: forming a plurality of through holes by etching to respectively expose the plurality of gate contact electrodes; carbon nanotubes, and then fill the via holes with conductive material to form a plurality of gate contact electrodes.