CN108257965A - Flash memory storage structure and its manufacturing method - Google Patents

Abstract

The invention relates to a flash storage structure and a manufacturing method thereof. The method includes: depositing a polysilicon layer on the substrate structure; using the polysilicon layer to form a floating gate and a field oxygen structure covering the floating gate; forming a protective spacer at the corner of the bottom of the floating gate; A tunnel oxide layer is formed on the structure and the floating gate; a control gate is formed on the tunnel oxide layer. In the above-mentioned flash memory storage structure and method, by forming protective sidewalls at the bottom corners of the floating gate, after the subsequent formation of the tunnel oxide layer, even if the bottom corners of the tunnel oxide layer are corroded through multiple times of wet etching, the Further corrosion will be prevented by the protective side walls. The control grid does not form sharp corners, which can effectively prevent electron anti-tunneling. Further, the protective sidewall is made of silicon nitride material which is not easily tunneled by electrons, which can also effectively prevent anti-tunneling of electrons. The formed semiconductor device is more stable in erasure.

Description

Flash storage structure and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor storage, in particular to a flash memory storage structure and a manufacturing method thereof.

Background technique

The basic unit of a semiconductor memory device is a semiconductor structure that can represent two states of 0 and 1. Generally, a common MOS structure of a semiconductor device is used. The basic structure of traditional flash memory (FLASH storage) mostly adds floating gates to store or release charges in the MOS structure to realize two states of 0 and 1.

FIG. 1 is a schematic diagram of a memory formed using a basic structure with a floating gate. As shown in Fig. 2a, it is a schematic diagram of the structure of this basic storage unit. The basic storage unit 10 includes a substrate structure 15, a polysilicon floating gate 11 disposed on the substrate 15, a field oxygen structure 12 formed on the floating gate 11, and a tunnel oxide covering the floating gate 11 and the field oxygen structure 12. layer 13, and a polysilicon control gate 14 overlying the tunnel oxide layer 13. Wherein, the floating gate 11 has a tip 111 .

When the basic memory cell 10 is erased, a high voltage is applied to the control gate 14 to discharge the tip of the floating gate 11 . The electrons stored in the floating gate 11 penetrate from the tunnel oxide layer 13 to the control gate 14 to change the storage state of the basic memory cell 10 to achieve the purpose of erasing. It can be understood that the thinner the tunneling oxide layer 13 is, the easier it is for electrons to tunnel.

However, in the manufacturing process of the basic memory cell 10 , after the floating gate 11 is formed, an intermediate structure covered with a tunnel oxide layer 13 is further formed. Thereafter, the intermediate structure undergoes multiple wet etching processes. Due to the instability of wet etching, the corners at the bottom of the tunnel oxide layer 13 will be etched more than other places, so in the subsequent process of forming the control gate 14, the control gate 14 forms sharp corners there. 141, as shown in Figure 2b. Electrons can easily tunnel from the control gate 14 into the floating gate 11 (this process is called anti-tunneling), resulting in unstable erasing.

Contents of the invention

Based on this, it is necessary to provide a method for manufacturing a flash memory storage structure, which can eliminate the over-etching at the bottom corner of the floating gate and improve the stability of erasing.

A method for manufacturing a flash storage structure, comprising:

Depositing a polysilicon layer on the substrate structure;

using the polysilicon layer to form a floating gate and a field oxygen structure covering the floating gate;

forming protective side walls at the corners of the bottom of the floating grid;

Form a tunnel oxide layer on the field oxygen structure and the floating gate;

A control gate is formed on the tunnel oxide layer.

In one of the embodiments, the step of forming protective sidewalls at the corners of the bottom of the floating gate includes:

Depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxygen structure; the isolation layer covers the field oxygen structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate;

Part of the isolation layer is removed and only the protective spacers at the corners at the bottom of the floating gate remain.

In one embodiment, dry etching and self-alignment are used to remove part of the isolation layer.

In one of the embodiments, the isolation layer is made of silicon nitride.

In one of the embodiments, the step of using the polysilicon layer to form a floating gate and a field oxygen structure covering the floating gate includes:

forming a mask layer on the polysilicon layer;

patterning the mask layer to form a floating gate window to expose part of the polysilicon layer;

performing oxidation growth in the floating gate window to form a field oxygen structure;

The mask layer is removed and the polysilicon layer outside the area covered by the field oxygen structure is etched to form a floating gate.

In one embodiment, the mask layer is removed and the polysilicon layer is dry etched to form a floating gate.

A flash storage structure comprising:

Substrate structure;

a floating gate formed on the substrate structure;

a field oxygen structure covering the floating gate;

Protective side walls, located at the corners of the bottom of the floating grid;

a tunnel oxide layer formed on the floating gate and field oxygen structures;

A control gate is formed on the tunnel oxide layer.

In one embodiment, the protective sidewall is made of a material that weakens electron tunneling.

In one of the embodiments, the protection spacer is made of silicon nitride material.

In one embodiment, the height of the part of the protective sidewall covering the sidewall of the floating gate is 1/5-1/2 of the height of the sidewall of the floating gate.

In the flash memory storage structure and method of the above embodiments, by forming protective sidewalls at the corners of the bottom of the floating gate, after subsequent formation of the tunneling oxide layer, even after multiple times of wet etching, the corners at the bottom of the tunneling oxide layer will be corroded , will also be protected from further corrosion by the side walls. The control grid does not form sharp corners, which can effectively prevent electron anti-tunneling. Further, the protective sidewall is made of a material that is not easily tunneled by electrons, which can also effectively prevent anti-tunneling of electrons. Therefore, the erase of the formed semiconductor device is more stable.

Description of drawings

1 is a schematic diagram of a memory formed using a basic structure with a floating gate;

Figure 2a is a schematic structural view of the basic storage unit in Figure 1;

Figure 2b is a schematic structural view of the basic memory cell in Figure 1 when wet etching defects occur;

Fig. 3 is a flow chart of a manufacturing method of a flash storage structure of an embodiment;

Figures 4a to 4e are schematic diagrams of the intermediate structure after each step in the process shown in Figure 3;

Fig. 5 is the flowchart of forming floating gate;

Figures 6a to 6c and Figure 4b are schematic diagrams of the intermediate structure after each step in the process shown in Figure 5;

FIG. 7 is a schematic diagram of a structure formed after depositing an isolation layer on the intermediate structure.

Detailed ways

Further description will be made below in conjunction with the accompanying drawings and specific embodiments.

FIG. 3 is a flowchart of a manufacturing method of a flash storage structure according to an embodiment. The method includes the following steps S110-S150. 4a to 4e are schematic diagrams of intermediate structures after each step of processing.

Step S110 : depositing a polysilicon layer 200 on the substrate structure 100 . The substrate structure 100 includes a substrate, a source region, a drain region and a channel region formed on the substrate, and there is a gate oxide layer above the channel region. For simplicity, these detailed structures are not shown in FIGS. 4a-4e It is explicitly shown that only the entire substrate structure 100 is represented. This step is a process after the substrate structure 100 is completed. The structure formed after this step is shown in Figure 4a.

Step S120 : using the polysilicon layer 200 to form a floating gate 210 and a field oxygen structure 220 covering the floating gate. The polysilicon layer 200 is processed to form a floating gate 210 and a field oxygen structure 220 . The structure formed after this step is shown in Figure 4b. Since the subsequent wet cleaning involves many steps of wet process, the subsequent bottom corners of the tunnel oxide layer 220 are concave, and even the bottom corners of the floating gate 210 are concave, so the following step S130 needs to be performed.

Step S130 : forming protective sidewalls 610 at corners of the bottom of the floating gate 210 . The structure formed after this step is shown in Figure 4c.

Step S140 : forming a tunnel oxide layer on the field oxygen structure 220 and the floating gate 210 . The tunnel oxide layer 300 is a silicon dioxide layer and can be formed by deposition. The structure formed after this step is shown in Figure 4d.

Step S150 : forming a control gate 400 on the tunnel oxide layer 300 . The structure formed after this step is shown in Figure 4e.

In the method of the above embodiment, by forming the protective spacer 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 220, even after multiple times of wet etching, the bottom corner of the tunnel oxide layer 220 is Corrosion is also prevented by the protective sidewall 610 from further corrosion. The control gate 400 does not form sharp corners, which can effectively prevent electron reverse tunneling. Further, the protective sidewall 610 is made of silicon nitride material which is not easily tunneled by electrons, which can also effectively prevent anti-tunneling of electrons. Therefore, the erase of the formed semiconductor device is more stable.

In one embodiment, as shown in FIG. 5 , the above step S120 may include the following sub-steps S121-S124. 6a to 6c and FIG. 4b are schematic diagrams of intermediate structures after each step of processing.

Sub-step S121 : forming a mask layer 500 on the polysilicon layer 200 . The mask layer 500 may be a silicon nitride (SiN) layer. The structure formed after this step is shown in Figure 6a.

Sub-step S122 : patterning the mask layer 500 to form a floating gate window 510 exposing part of the polysilicon layer. The structure formed after this step is shown in Figure 6b.

Sub-step S123: Perform oxidation growth in the floating gate window to form a field oxygen structure. In this step, the tip of the floating gate can be formed while growing the field oxygen structure. The structure formed after this step is shown in Figure 6c.

Sub-step S124: removing the mask layer and etching the polysilicon layer outside the area covered by the field oxygen structure to form a floating gate. The structure formed after this step is shown in Figure 4b.

In one embodiment, the above step S130 may include the following sub-steps S131-S132. The following description will be made in conjunction with Fig. 4b, Fig. 7 and Fig. 4c.

Step S131 : depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxygen structure. This intermediate structure is shown in Figure 4b. After this step, as shown in FIG. 7 , the isolation layer 600 covers the field oxygen structure 220 , the sidewall of the floating gate 210 and the substrate structure 100 not covering the floating gate 210 . The isolation layer 500 can be made of silicon nitride material. It can be understood that after depositing the isolation layer, there will be part of the isolation layer at the corners of the floating gate 210 .

Step S132 : removing part of the isolation layer and keeping only the isolation layer at the corner of the floating gate to form a protective spacer. The removed part of the isolation layer includes the part covering the surface of the field oxygen structure, the part covering the sidewall of the floating gate and the part covering the substrate structure. In this step, dry etching may be used. Self-aligned etching is used when etching the portion located on the sidewall of the floating gate. After this step, the formed structure is shown in Figure 4c.

It can be understood that other ways may also be used to form protective sidewalls at the corners of the floating gate, which are not limited to the above ways.

Based on the same inventive concept, a flash storage structure is provided. As shown in FIG. 4 e , the flash storage structure includes a substrate structure 100 , a floating gate 210 , a field oxide structure 220 , a tunnel oxide layer 300 and a control gate 400 stacked in sequence.

The substrate structure 100 includes a substrate, a source region, a drain region and a channel region formed on the substrate, and a gate oxide layer is located above the channel region, and the floating gate 210 is located on the gate oxide layer. For the sake of simplicity, these detailed structures are not explicitly shown in FIG. 4 e , but are only represented by the entire substrate structure 100 . A floating gate 210 is formed on the substrate structure 100 above the channel between the source region and the drain region. The floating gate 210 is polysilicon material. The floating gate 210 has a discharge tip 211 . The field oxygen structure 220 covers the floating gate 210, and the field oxygen structure 220 is silicon dioxide material. A tunnel oxide layer 300 is formed on the floating gate 210 and the field oxygen structure 220 , and the tunnel oxide layer 300 is made of silicon dioxide. Wherein, a protective spacer 610 is provided at a corner of the bottom of the floating gate 210, and the protective spacer 610 may be made of a material that weakens electron tunneling, such as silicon nitride. The tunnel oxide layer 300 covers the sidewalls of the floating gate 210 and the protection sidewalls 610 . A control gate 400 is formed on the tunnel oxide layer 300, and the control gate 400 is made of polysilicon material. The height of the protection sidewall 610 is 1/5˜1/2 of the height of the floating gate sidewall.

In the flash memory storage structure of the above embodiment, by forming the protective spacer 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 300, the bottom corner of the tunnel oxide layer 220 will remain intact even after multiple times of wet etching. Corrosion at the place will be prevented by the protective side wall 610 from further corrosion. The control gate 400 does not form sharp corners, which can effectively prevent electron reverse tunneling. Further, the protective sidewall 610 is made of silicon nitride material which is not easily tunneled by electrons, which can also effectively prevent anti-tunneling of electrons. The formed semiconductor device is more stable in erasure.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A method for manufacturing a flash storage structure, comprising: Depositing a polysilicon layer on the substrate structure; using the polysilicon layer to form a floating gate and a field oxygen structure covering the floating gate; forming protective side walls at the corners of the bottom of the floating grid; Form a tunnel oxide layer on the field oxygen structure and the floating gate; A control gate is formed on the tunnel oxide layer. 2. The method for manufacturing a flash memory storage structure according to claim 1, wherein the step of forming a protective spacer at the corner of the bottom of the floating gate comprises: Depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxygen structure; the isolation layer covers the field oxygen structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate; Part of the isolation layer is removed and only the protective spacers at the corners at the bottom of the floating gate remain. 3. The method for manufacturing a flash memory storage structure according to claim 2, wherein dry etching and self-alignment are used to remove part of the isolation layer. 4. The method for manufacturing a flash memory storage structure according to claim 2, wherein the isolation layer is made of silicon nitride. 5. The method for manufacturing a flash memory storage structure according to claim 1, wherein the step of using the polysilicon layer to form a floating gate and a field oxygen structure covering the floating gate comprises: forming a mask layer on the polysilicon layer; patterning the mask layer to form a floating gate window to expose part of the polysilicon layer; performing oxidation growth in the floating gate window to form a field oxygen structure; The mask layer is removed and the polysilicon layer outside the area covered by the field oxygen structure is etched to form a floating gate. 6. The method for manufacturing a flash memory storage structure according to claim 5, wherein the mask layer is removed and the polysilicon layer is dry etched to form a floating gate. 7. A flash storage structure, comprising: Substrate structure; a floating gate formed on the substrate structure; a field oxygen structure covering the floating gate; Protective side walls, located at the corners of the bottom of the floating grid; a tunnel oxide layer formed on the floating gate and field oxygen structures; A control gate is formed on the tunnel oxide layer. 8 . The flash memory storage structure according to claim 7 , wherein the protection spacer is a material that weakens electron tunneling. 9. The flash storage structure according to claim 7, wherein the protective spacer is made of silicon nitride. 10 . The flash memory storage structure according to claim 7 , wherein the height of the part of the protective sidewall covering the sidewall of the floating gate is 1/5˜1/2 of the height of the sidewall of the floating gate. 11 .