CN108257916A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same. The method includes: forming a base, the base includes a substrate, a gate structure on the substrate, source and drain doped regions in the base on both sides of the gate structure, and a base on the base and covering The interlayer dielectric layer on the top of the gate structure, the substrate includes a first region for forming a P-type device and a second region for forming an N-type device; an exposed source and drain are formed in the interlayer dielectric layer on both sides of the gate structure The first contact opening of the doped region; performing a P-type doping isolation Schottky doping process on the source and drain doped regions exposed by the first contact opening in the first region and the second region; forming a metal at the bottom of the first contact opening a silicide layer; forming a first contact hole plug in the first contact opening. In the present invention, by adjusting the doping concentration of the source-drain doping region in the second region, the use of a photomask can be avoided during the P-type doping isolation Schottky doping process, and the process cost can be reduced, and the N-type device can be improved. Less affected.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the continuous development of integrated circuit manufacturing technology, the critical dimensions of devices are getting smaller and smaller, and many problems have arisen accordingly. For example, the contact resistance between the contact hole plug and the source-drain doped region increases, which leads to a decrease in the response speed of the device, a delay in the signal, and a decrease in the driving current, thereby degrading the performance of the semiconductor device.

In order to reduce the contact resistance between the contact hole plug and the source-drain doped region, a metal silicide process is introduced. The metal silicide has a lower resistivity and can significantly reduce the contact resistance, thereby increasing the driving current.

With the continuous reduction of the key dimensions of the device, the contact resistance has been difficult to meet the process requirements after the metal silicide process is adopted, so the Dopant Segregated Schottky (DSS) implantation process has been introduced at present; by doping the source and drain The impurity region is implanted with DSS to reduce the Schottky barrier height (Schottky Barrier Height, SBH) of the source-drain doped region and the channel region, thereby reducing the contact resistance and increasing the driving current.

Although the DSS implantation process can effectively reduce the Schottky barrier height, the process cost is relatively high.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its forming method, which can reduce the process cost while effectively reducing the Schottky barrier height.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: forming a base, the base includes a substrate, a gate structure located on the substrate, and gate structures located in the base on both sides of the gate structure. A source-drain doped region, and an interlayer dielectric layer on the substrate and covering the top of the gate structure, the substrate includes a first region for forming a P-type device and a first region for forming an N-type device Two regions: forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layer on both sides of the gate structure; The source and drain doped regions are subjected to a P-type doping isolation Schottky doping process; after the P-type doping isolation Schottky treatment is completed, a metal silicide layer is formed at the bottom of the first contact opening; After the metal silicide layer is formed, a conductive material is filled into the first contact opening to form a first contact hole plug in the first contact opening.

Correspondingly, the present invention also provides a semiconductor structure, including: a base, the base includes a substrate, a gate structure located on the substrate, and source-drain doped regions located in the base on both sides of the gate structure , and an interlayer dielectric layer on the substrate and covering the top of the gate structure, the substrate includes a first region with a P-type device and a second region with an N-type device; a contact opening is located at the The doped source and drain regions are exposed in the interlayer dielectric layer on both sides of the gate structure, wherein the doped source and drain regions exposed by the contact openings in the first region and the second region have undergone P-type doping isolates the Schottky doping process.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the step of forming the substrate in the present invention, the substrate includes a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a and cover the interlayer dielectric layer on the top of the gate structure, the substrate includes a first region for forming a P-type device and a second region for forming an N-type device; on both sides of the gate structure After forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layer, performing P-type doping on the source-drain doped region exposed by the first contact opening in the first region and the second region Isolation Schottky doping process; that is to say, when performing the P-type doping isolation Schottky doping process, no pattern layer for protecting the second region is formed in the second region, and The P-type doping isolation Schottky doping process is performed on the source-drain doping regions of the first region and the second region at the same time, and the P-type doping isolation Schottky doping process is used to reduce the The height of the Schottky barrier between the source and drain doped regions of the first region and the channel region, and when the source and drain doped regions of the second region are formed, the Schottky doping can be isolated according to the P-type doping The parameters of the process adjust the doping ion concentration of the source and drain doping regions of the second region accordingly to reduce the impact on the electrical performance of the N-type device; therefore, through the scheme of the present invention, on the one hand, it can still reduce the The Schottky barrier height of the source-drain doped region and the channel region of the first region, thereby reducing the contact resistance of the first region, and then improving the drive current of the P-type device; on the other hand, compared to only The scheme of performing the P-type doping isolation Schottky doping process in the source-drain doping region of the first region, the scheme of the present invention can avoid the use of a photomask, realize the reduction of process cost, and is suitable for N-type devices has less impact.

In an optional solution, after forming the first contact opening and before forming the metal silicide layer, the forming method further includes: pre-discharging the source-drain doped regions in the first region and the second region. Crystallization treatment; through the pre-amorphization treatment, not only the Schottky barrier height of the source and drain doped regions and the channel region of the first region can be reduced, but also the source and drain doped regions of the second region can be reduced. The Schottky barrier height of impurity region and channel region, thereby helps to reduce the contact resistance of described first region and second region, improves the driving current of P-type device and N-type device; The amorphization treatment is also beneficial to improve the formation quality uniformity of the metal silicide layer.

The semiconductor structure of the present invention includes a contact opening, the contact opening is located in the interlayer dielectric layer on both sides of the gate structure and exposes the source-drain doped region, wherein the contact opening in the first region and the second region The exposed source and drain doped regions have undergone a P-type doping isolation Schottky doping process in the same step; therefore, by adjusting the doping concentration of the source and drain doped regions in the second region of the semiconductor structure to Reasonable value, then can avoid additionally adopting photomask to carry out described P-type doping isolation Schottky doping process, so the manufacturing cost of described semiconductor structure is lower, and the impact on N-type device is less; The Schottky barrier height of the source-drain doped region and the channel region of the first region is reduced, thereby reducing the contact resistance of the first region, thereby increasing the driving current of the P-type device.

Description of drawings

1 to 10 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention;

FIG. 11 is a schematic structural view of an embodiment of the semiconductor structure of the present invention.

Detailed ways

It can be known from the background art that although the Dopant Segregated Schottky (DSS) implantation process can effectively reduce the Schottky barrier height, the process cost is relatively high. Analyze the reasons for this:

During the DSS implantation process, the type of ions implanted in the source and drain doped regions of the N-type region is different from the ion type implanted in the source and drain doped regions of the P-type region. During DSS implantation, the implanted ion source used is P or As, and when the P-type DSS implantation is performed on the source-drain doped region of the P-type region, the implanted ion source used is B or BF ₂ , therefore, two optical cover to perform the N-type DSS injection and the P-type DSS injection respectively, and the process cost is relatively large.

In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure. In the step of forming the base, the base includes a substrate, a gate structure on the substrate, and a gate structure located on both sides of the gate structure. A source-drain doped region in the side substrate, and an interlayer dielectric layer located on the substrate and covering the top of the gate structure, the substrate includes a first region for forming a P-type device and a first region for forming an N The second region of the type device; after the first contact opening exposing the source-drain doped region is formed in the interlayer dielectric layer on both sides of the gate structure, the first region in the first region and the second region The source-drain doping region exposed by the contact opening is subjected to a P-type doping isolation Schottky doping process. That is to say, when performing the P-type doping isolation Schottky doping process, a pattern layer for protecting the second region is not formed in the second region, but the first region and the The source and drain doping regions of the second region are simultaneously subjected to the P-type doping isolation Schottky doping process, and the P-type doping isolation Schottky doping process is used to reduce the source and drain doping of the first region region and the Schottky barrier height of the channel region, and when forming the source and drain doped regions of the second region, according to the parameters of the P-type doping isolation Schottky doping process, the second The concentration of doping ions in the source and drain doped regions of the region is adjusted accordingly to reduce the impact on the electrical properties of the N-type device; therefore, through the solution of the present invention, on the one hand, the source and drain doping of the first region can still be reduced. region and the Schottky barrier height of the channel region, thereby reducing the contact resistance of the first region, and then improving the drive current of the P-type device; on the other hand, compared to only doping the source and drain of the first region The scheme of performing the P-type doping isolation Schottky doping process in the impurity region, the scheme of the present invention can avoid the use of a photomask, reduce the process cost, and have less impact on the N-type device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 10 are schematic diagrams of structures corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to Figures 1 to 5 in conjunction, Figure 1 is a perspective view (only two fins are shown), and Figure 2 is a schematic cross-sectional structural view of a secant line perpendicular to the extending direction of the fins (as shown by the AA1 secant line in Figure 1). 4 is a schematic cross-sectional structure diagram of a secant line along the extending direction of the fin (as shown by the BB1 secant line in FIG. ), a source-drain doped region (not marked) located in the substrate on both sides of the gate structure, and an interlayer dielectric layer 103 located on the substrate and covering the top of the gate structure (as shown in FIG. 5 ) , the substrate 100 includes a first region I for forming a P-type device and a second region II for forming an N-type device.

The steps of forming the base will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 and FIG. 2 together, the substrate 100 provides a process platform for subsequent formation of semiconductor devices.

In this embodiment, the base is used to form a FinFET, so the base further includes discrete fins (not shown) on the substrate 100 . In other embodiments, the substrate is used to form a planar transistor, and accordingly, the substrate is a planar substrate.

In this embodiment, the substrate 100 includes a first region I for forming a P-type device and a second region II for forming an N-type device. Correspondingly, the fins located on the substrate 100 in the first region I are the first fins 110 (as shown in FIG. 2 ), and the fins located on the substrate 100 in the second region II are the second fins. 120 (as shown in Figure 2). In other embodiments, the substrate may also be used only for forming P-type devices or only for forming N-type devices.

The first area I and the second area II may be adjacent areas or non-adjacent areas. In this embodiment, the first area I and the second area II are adjacent areas.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. substrate.

The material of the fin is the same as that of the substrate 100 . In this embodiment, the material of the fin is silicon, that is, the material of the first fin 110 and the second fin 120 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Specifically, the process steps of forming the substrate 100 and the fins include: providing an initial base; forming a patterned fin mask layer 200 (as shown in FIG. 2 ) on the surface of the initial base; The mask layer 200 is used as a mask to etch the initial base, the remaining initial base after etching is used as the substrate 100 , and the protrusions on the substrate 100 are used as fins.

In this embodiment, after the substrate 100 and the fins are formed, the fin mask layer 200 on the top of the fins remains. The material of the fin mask layer 200 is silicon nitride. When the subsequent planarization process is performed, the top surface of the fin mask layer 200 is used to define the stop position of the planarization process, and to protect the Describe the function of the top of the fin.

With reference to FIG. 3 , it should be noted that after forming the substrate 100 and the fins, the forming method further includes: forming an isolation structure 101 on the substrate 100 where the fins are exposed, and the isolation structure 101 covers Part of the sidewall of the fin, and the top of the isolation structure 101 is lower than the top of the fin.

The isolation structure 101 is used as an isolation structure of a semiconductor device for isolating adjacent devices and fins. In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Specifically, the process step of forming the isolation structure 101 includes: filling an isolation film on the substrate 100 where the fin is exposed, and the top of the isolation film is higher than the fin mask layer 200 (as shown in FIG. 2 ) top; grinding and removing the isolation film higher than the top of the fin mask layer 200; etching back part of the thickness of the remaining isolation film to form the isolation structure 101; removing the fin mask layer 200.

Referring to FIG. 4 , a gate structure (not shown) is formed on the substrate 100 .

In this embodiment, the base includes a substrate 100 and discrete fins located on the substrate 100, so the gate structure straddles the fins and covers part of the sidewall surface and the fins. top surface.

Specifically, the gate structure located in the first region I is a first gate structure 610 (as shown in FIG. 4 ), and the first gate structure 610 straddles the first fin 110 and covers all Part of the sidewall surface and the top surface of the first fin 110; the gate structure located in the second region II is the second gate structure 620 (as shown in FIG. 4 ), and the second gate structure 620 laterally across the second fin 120 and cover part of the sidewall surface and the top surface of the second fin 120 .

In this embodiment, the gate structure is formed by forming a high-k gate dielectric layer and then forming a gate electrode layer (high k last metal gatelast). Therefore, before forming the gate structure, the forming method further includes: Forming a dummy gate structure (dummy gate) across the fin and covering the top surface and sidewall surface of the fin portion; forming source and drain doped regions (not marked) in the fin on both sides of the dummy gate structure; forming After the source and drain doped regions, a bottom dielectric layer 102 (as shown in FIG. 4 ) is formed on the substrate exposed by the dummy gate structure, the bottom dielectric layer 102 covers the source and drain doped regions, and the The bottom dielectric layer 102 exposes the top of the dummy gate structure; after the bottom dielectric layer 102 is formed, the dummy gate structure is removed, and an opening (not shown) is formed in the bottom dielectric layer 102 .

The substrate 100 includes a first region I and a second region II, and correspondingly, the source and drain doped regions in the first fins 110 on both sides of the dummy gate structure in the first region I are the first source and drain doped regions. region (not shown), the source and drain doped regions in the second fins 120 on both sides of the dummy gate structure in the second region are the second source and drain doped regions (not shown); in the first region The openings in the I bottom dielectric layer 102 are first openings (not shown), and the openings in the second region II bottom dielectric layer 102 are second openings (not shown).

The dummy gate structure occupies a spatial position for forming the first gate structure 610 and the second gate structure 620 . The dummy gate structure is a single-layer structure or a stacked structure. The dummy gate structure includes a dummy gate layer; or the dummy gate structure includes a dummy oxide layer and a dummy gate layer on the dummy oxide layer. Wherein, the material of the dummy gate layer is polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon, and the material of the dummy oxide layer is silicon oxide or silicon oxynitride.

The first source-drain doped region is used as a source region or drain region of a subsequently formed P-type device, and the second source-drain doped region is used as a source region or drain region of a subsequently formed N-type device. In this embodiment, the first source-drain doped region and the second source-drain doped region are formed by selective epitaxy (EPI).

Specifically, the step of forming the first source-drain doped region includes: forming a first epitaxial layer 112 (as shown in FIG. 4 ) in the first fin portion 110 on both sides of the dummy gate structure in the first region I, And in the process of forming the first epitaxial layer 112 , in-situ self-doping with P-type ions to form the first source-drain doped region. The material of the first epitaxial layer 112 may be Si or SiGe, and the P-type ions include one or more of B, Ga and In. In this embodiment, the material of the first epitaxial layer 112 is Si; the P-type ions are Ge, that is, the doping ions in the first source-drain doped region are Ge ions. The doping concentration of Ge ions is determined according to actual process requirements. In this embodiment, the atomic percentage of Ge ions is 35% to 65%.

Specifically, the step of forming the second source-drain doped region includes: forming a second epitaxial layer 122 (as shown in FIG. 4 ) in the second fin portion 120 on both sides of the dummy gate structure in the second region II, And in the process of forming the second epitaxial layer 122, N-type ions are self-doped in situ to form the second source-drain doped region. The material of the second epitaxial layer 122 may be Si or SiC, and the N-type ions include one or both of P and As. In this embodiment, the material of the second epitaxial layer 122 is Si; the N-type ions are P, that is, the doping ions in the second source-drain doped region are P ions.

It should be noted that the subsequent steps include performing a P-type doping isolation Schottky (Dopant Segregated Schottky, DSS) doping process on the first source-drain doped region, and the doping ions in the doping process are P-type Ions, the doping process is used to reduce the Schottky barrier height (Schottky Barrier Height, SBH) of the first source-drain doped region and the P-type device channel region; in order to save the mask, the second source The drain doped region is exposed to the environment of the P-type doping isolation Schottky doping process, that is, the second source-drain doped region is affected by P-type ion doping, so in order to reduce the impact on the subsequent formed The influence of the electrical performance of the N-type device, according to the actual process requirements and the doping concentration of the subsequent P-type doping isolation Schottky doping process, increase the P ion doping concentration of the second source-drain doping region to a reasonable value . In this embodiment, the doping concentration of P ions is 1E21atom/cm ³ to 3E21atom/cm ³ .

It should also be noted that by increasing the P ion doping concentration of the second source-drain doped region, it is also beneficial to reduce the Schottky barrier height of the first source-drain doped region and the channel region, thereby It is beneficial to reduce the contact resistance of the second region II, thereby increasing the driving current of the N-type device.

In this embodiment, the first source-drain doped region and the second source-drain doped region are formed through a selective epitaxial process. In other embodiments, the first source-drain doped region and the second source-drain doped region can also be formed in the form of ion-doped non-epitaxial layers, that is, the first region can be directly dummy performing ion doping process on the first fins on both sides of the gate structure to form the first source-drain doped region, by directly performing ion doping process on the second fins on both sides of the dummy gate structure in the second region , to form the second source-drain doped region.

The material of the bottom dielectric layer 102 is insulating material. In this embodiment, the material of the bottom dielectric layer 102 is silicon oxide. In other embodiments, the material of the bottom dielectric layer may also be silicon nitride or silicon oxynitride.

It should be noted that, after forming the dummy gate structure and before forming the source-drain doped region, the forming method further includes: forming sidewalls 130 on the sidewalls of the dummy gate structure. The sidewalls 130 can be used to define the positions of the first source-drain doped region and the second source-drain doped region. The material of the side wall 130 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 130 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 130 is a single-layer structure, and the material of the sidewall 130 is silicon nitride.

In this embodiment, the first gate structure 610 is formed in the first opening (not shown), the second gate structure 620 is formed in the second opening (not shown), and The tops of the first gate structure 610 and the second gate structure 620 are flush with the top of the bottom dielectric layer 102 .

Specifically, the step of forming the first gate structure 610 and the second gate structure 620 includes: forming a gate dielectric layer 310 on the sidewall and bottom of the first opening, and on the sidewall and bottom of the second opening, so The gate dielectric layer 310 also covers the top of the bottom dielectric layer 102; a capping layer 410 is formed on the gate dielectric layer 310; a P-type work function layer 320 is formed on the capping layer 410; the second region II is removed P-type work function layer 320, exposing the cap layer 410; forming an N-type work function layer 330 on the P-type work function layer 320 of the first region I and the cap layer 410 of the second region II; A gate barrier layer 420 is formed on the N-type work function layer 330; a metal layer 510 filling the first opening and the second opening is formed on the gate barrier layer 420; metal layer 510, and remove the gate barrier layer 420, N-type work function layer 330, P-type work function layer 320, cap layer 410 and gate dielectric layer 310 higher than the bottom dielectric layer 102; wherein, the first The gate dielectric layer 310, the capping layer 410, the P-type work function layer 320, the N-type work function layer 330, the gate barrier layer 420 and the metal layer 510 in an opening are used to form the first gate structure 610, the The gate dielectric layer 310 , the capping layer 410 , the N-type work function layer 330 , the gate barrier layer 420 and the metal layer 510 in the second opening are used to form the second gate structure 620 .

Correspondingly, the first source-drain doped region is located in the first fin portion 110 on both sides of the first gate structure 610, and the second source-drain doped region is located on both sides of the second gate structure 620. Inside the second fin portion 120 on the side.

In this embodiment, the gate dielectric layer 310 includes an interfacial layer (IL, Interfacial Layer) (not marked) and a high-k gate dielectric layer (not marked) located on the surface of the interface layer.

The interface layer provides a good interface basis for forming the high-k gate dielectric layer, thereby improving the quality of the high-k gate dielectric layer and reducing the interface state density between the high-k gate dielectric layer and the fin, In addition, adverse effects caused by direct contact between the high-k gate dielectric layer and the fin are avoided. The material of the interface layer is silicon oxide or silicon oxynitride.

The material of the high-k gate dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

The capping layer 410 not only protects the gate dielectric layer 310, but also prevents the metal ions of the N-type work function layer 330 and the P-type work function layer 320 from diffusing into the gate dielectric layer 310; The layer 410 can also prevent oxygen ions in the gate dielectric layer 310 from diffusing into the N-type work function layer 330 and the P-type work function layer 320 , thereby avoiding the problem of increased oxygen vacancy content in the gate dielectric layer 310 . In this embodiment, the material of the capping layer 410 is TiN. In other embodiments, the material of the capping layer may also be TiSiN or TaN.

On the one hand, the gate barrier layer 420 is used to protect the N-type work function layer 330 and the P-type work function layer 320, preventing the easily diffusible ions in the metal layer 510 from diffusing to the N-type In the work function layer 330 and the P-type work function layer 320; form mass. In this embodiment, the material of the gate barrier layer 420 is TiN. In other embodiments, the material of the gate barrier layer may also be TiSiN.

The material of the P-type work function layer 320 is a P-type work function material, and the work function range of the P-type work function material is 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV. The material of the P-type work function layer 320 is one or more of Ta, TiN, TaN, TaSiN or TiSiN, and the P-type work function layer 320 can be formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. Function layer 320 .

The material of the N-type work function layer 330 is an N-type work function material, and the work function of the N-type work function material ranges from 3.9eV to 4.5eV, such as 4eV, 4.1eV or 4.3eV. The material of the N-type work function layer 330 can be one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN, and the material can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. N-type work function layer 330 .

In this embodiment, the material of the metal layer 510 is W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti.

Referring to FIG. 5 , an interlayer dielectric layer 103 is formed on the substrate, and the interlayer dielectric layer 103 covers the top of the gate structure (not shown) and the top of the bottom dielectric layer 102 .

Specifically, the step of forming the interlayer dielectric layer 103 includes: forming an interlayer dielectric film covering the top of the gate structure (not shown) and the top of the bottom dielectric layer 102; performing a planarization process on the interlayer dielectric film , forming an interlayer dielectric layer 103 and the top of the interlayer dielectric layer 103 is higher than the top of the gate structure.

The material of the interlayer dielectric layer 103 is insulating material. In this embodiment, in order to improve process compatibility, the material of the interlayer dielectric layer 103 is the same as that of the bottom dielectric layer 102, and the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.

In other embodiments, the gate structure may also be formed by forming a high-k gate dielectric layer first and then forming a gate electrode layer (high k firstmetal gate first). Correspondingly, the step of forming the base includes: providing an initial substrate; etching the initial substrate to form the substrate and discrete fins on the substrate, the substrate includes The first region of the first region and the second region for forming an N-type device; forming a gate structure across the fin and covering the top surface and sidewall surface of the fin portion; in the fin on both sides of the gate structure Forming a source-drain doped region; forming an interlayer dielectric layer on the exposed base of the gate structure, the top of the interlayer dielectric layer being higher than the top of the gate structure.

Referring to FIG. 6 , a first contact opening 155 exposing the source-drain doped region (not shown) is formed in the interlayer dielectric layer 103 on both sides of the gate structure (not shown).

The first contact opening 155 in the first region I exposes the first source-drain doped regions on both sides of the first gate structure 610, and the first contact opening 155 in the second region II exposes the second gate structure 610. The second source and drain doped regions on both sides of the pole structure 620 . In this embodiment, the first contact opening 155 in the first region I runs through the interlayer dielectric layer 103 and the bottom dielectric layer 102 in the first region I, and the first contact opening 155 in the second region II runs through all The interlayer dielectric layer 103 and the bottom dielectric layer 102 of the second region II are described above.

The first contact opening 155 provides a spatial location for subsequent formation of contact hole plugs in contact with the first source-drain doped region and the second source-drain doped region. Specifically, dry etching is used to remove the interlayer dielectric layer 103 and the bottom dielectric layer 102 above the first source-drain doped region and above the second source-drain doped region.

It should be noted that, in this embodiment, the first contact opening 155 is formed using a non-self-aligned process. Therefore, before etching the interlayer dielectric layer 103 and the bottom dielectric layer 102, a pattern layer is also formed on part of the interlayer dielectric layer 103; in the step of forming the first contact opening 155, with the pattern layer as a mask for etching. In other embodiments, the first contact opening may also be formed by a self-alignment process.

It should also be noted that, during the process of forming the first contact opening 155 , part of the thickness of the first epitaxial layer 112 and the second epitaxial layer 122 is also removed.

Referring to FIG. 7 , a P-type doping isolation Schottky doping process is performed on the source and drain doped regions (not shown) exposed by the first contact opening 155 in the first region I and the second region II.

The P-type doping isolation Schottky doping process is used to dope the first source-drain doped region with P-type ions; subsequently deposit a metal layer on the first source-drain doped region to form metal silicide When forming a silicide layer, the annealing process causes the metal layer and silicon to react to form a metal silicide layer, and the annealing process also drives the P-type ions to segregate in the formed metal silicide layer and silicon interface, so that the height of the Schottky barrier between the first source-drain doped region and the channel region can be reduced.

Therefore, in the step of performing the P-type doping isolation Schottky doping process, the doping ions include one or more of B, Al, Ga and In.

In this embodiment, the P-type doping isolation Schottky doping process is an ion implantation process, the doping ion of the P-type doping isolation Schottky doping process is B, and the parameters of the ion implantation process It depends on the actual process requirements. In this embodiment, the parameters of the ion implantation process include: when the implanted ion source is B, the implanted ion energy is 500eV to 3KeV, and the implanted ion dose is 1E14atom/cm ² to 5E15atom/cm ² ; the implanted ion source When it is BF ₂ , the implanted ion energy is 1KeV to 10KeV, and the implanted ion dose is 1E14atom/cm ² to 5E15atom/cm ² .

In this embodiment, in order to save a photomask, the P-type doping isolation Schottky doping process is performed in a maskless manner. Correspondingly, the P-type doping isolation Schottky doping process also The second source-drain doped region is doped.

It should be noted that, in order to reduce the Schottky barrier height of the first source-drain doped region and the channel region, and the Schottky barrier height of the second source-drain doped region and the channel region, After forming the first contact opening 155, the forming method further includes: performing a pre-amorphization (Pre-amorphization Implant, PAI) treatment on the source-drain doped regions in the first region I and the second region II , that is, perform the pre-amorphization treatment on the first source-drain doped region and the second source-drain doped region.

Through the pre-amorphization treatment, not only is it beneficial to reduce the height of the Schottky barrier; it can also convert the first epitaxial layer 112 and the second epitaxial layer 122 with the thickness of the bottom part of the first contact opening 155 into amorphous silicon layer 630, which is beneficial to improve the formation quality and quality uniformity of the subsequent metal silicide layer.

In this embodiment, the pre-amorphization treatment is an ion implantation process; the implanted ions in the ion implantation process are Ge ions, the implanted ion energy is 3KeV to 10KeV, and the implanted ion dose is 1E14atom/ ^cm2 to 3E15atom/cm2 cm ² .

It should also be noted that, in this embodiment, the pre-amorphization treatment is performed first, and then the P-type doping isolation Schottky doping process is performed. In other embodiments, the P-type doping isolation Schottky doping process may be performed first, and then the pre-amorphization treatment is performed.

In addition, referring to FIG. 8 , after completing the pre-amorphization treatment and the P-type doping isolation Schottky doping process, the forming method further includes: an interlayer above the gate structure (not shown) A second contact opening 156 exposing the top of the gate structure is formed in the dielectric layer 103 .

The second contact opening 156 provides a spatial location for the subsequent formation of a second contact hole plug electrically connected to the gate structure. Wherein, the second contact opening 156 located in the first region I penetrates through the interlayer dielectric layer 103 above the first gate structure 610 and exposes the top of the first gate structure 610, and is located in the second region II The second contact opening 156 penetrates through the interlayer dielectric layer 103 above the second gate structure 620 and exposes the top of the second gate structure 620 .

Specifically, a filling layer 210 is formed in the first contact opening 155 (as shown in FIG. 7 ), and the filling layer 210 also covers the top of the interlayer dielectric layer 103; A photoresist layer (not shown); using the photoresist layer as a mask, etch the filling layer 210 and the interlayer dielectric layer 103, the interlayer dielectric above the first gate structure 610 A second contact opening 156 is formed in the layer 103 and in the interlayer dielectric layer 103 above the second gate structure 620 ; after the second contact opening 156 is formed, the photoresist layer and the filling layer 210 are removed.

In this embodiment, the material of the filling layer 210 is organic dielectric material, bottom anti-reflection layer material, deep ultraviolet light absorbing silicon oxide material or amorphous carbon.

Referring to FIG. 9 , after the P-type doping isolation Schottky doping process is completed, a metal silicide layer 640 is formed at the bottom of the first contact opening 155 .

Subsequent steps include forming first contact hole plugs in the first contact openings 155 of the first region I and the second region II, and the first contact hole plugs are used to realize electrical connection with the source and drain doped regions. connection, the metal silicide layer 640 is used to reduce the contact resistance of the contact area.

In this embodiment, the step of forming the metal silicide layer 640 includes: conformally covering the surface of the first contact opening 155 with a metal layer (not shown); after forming the metal layer, annealing the substrate Treatment reacts the metal layer with the Si-containing substrate, converting the metal layer to a metal silicide layer 640 . Specifically, the metal layer reacts with the first epitaxial layer 112 and the second epitaxial layer 122 to form the metal silicide layer 640 .

In this embodiment, the material of the metal layer is Ti, and the material of the first epitaxial layer 112 and the second epitaxial layer 122 is Si, so during the annealing process, the Ti atoms in the metal layer Interdiffuse and react with Si atoms in the first epitaxial layer 112 and the second epitaxial layer 122 to form a metal silicide layer 640 made of TiSi. In other embodiments, the metal layer may also be Ni, and correspondingly, the material of the formed metal silicide layer is NiSi.

In this embodiment, the annealing treatment is laser annealing treatment, and the process pressure of the laser annealing treatment is a standard atmospheric pressure. In other embodiments, the annealing treatment may also be rapid thermal annealing treatment.

In order to ensure the effect of the metal layer reacting with the first epitaxial layer 112 and the second epitaxial layer 122, the thickness and quality of the formed metal silicide layer 640 meet the process requirements, and avoid damage to the existing The doping ions cause adverse effects. In this embodiment, the annealing temperature is 700°C to 1000°C.

It should also be noted that the thickness of the metal silicide layer 640 affects the contact resistance of the contact region; and when the thickness of the metal silicide layer 640 is too large, it is easy to cause the metal layer to The coverage of the surface of the contact opening 155 is poor, and void defects are prone to appear in the metal layer, thereby reducing the quality of the formed metal silicide layer 640 and further affecting the electrical performance of the formed semiconductor device. Therefore, in order to make the electrical performance of the formed semiconductor device meet the process requirements, in this embodiment, the thickness of the metal silicide layer 640 is to

In this embodiment, the metal layer is formed by a physical vapor deposition process, and the metal layer is also located on the sidewall of the first contact opening 155, and is also located on the bottom and sidewall of the second contact opening 156; wherein, In the step of forming the metal silicide layer 640 , the metal layer at the bottom of the first contact opening 155 reacts with silicon, and after the metal silicide layer 640 is formed, it remains on the side of the first contact opening 155 The metal layer of the wall, the bottom of the second contact opening 156 and the sidewall. In other embodiments, the process for forming the metal layer may also be a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, in order to improve the formation quality of the metal silicide layer 640, so that the metal silicide layer 640 and the source-drain doped region can be better electrically connected, before forming the metal layer, the The forming method further includes: performing a pre-cleaning process on the first contact opening 155 .

Through the pre-cleaning process, the native oxide layer (native oxide) in the first contact opening 155 can be removed to provide a good interface state for forming the metal layer. In this embodiment, the pre-cleaning process may be a SiCoNi process or a hydrofluoric acid vapor phase etching process.

In this embodiment, after forming the metal layer and before annealing the substrate, the forming method further includes: forming a barrier layer 800 on the metal layer.

The function of the barrier layer 800 is: on the one hand, it can prevent reactants used in the subsequent formation of the first contact hole plug in the first contact opening 155 from interacting with the first epitaxial layer 112 and the second epitaxial layer. 122 can also prevent the reactants used from reacting with the formed metal silicide layer 640; on the other hand, the barrier layer 800 is used to improve the conductive material in the subsequent formation of the first contact hole plug. Adhesion within the first contact opening 155, the barrier layer 800 may function as a contact hole liner. In this embodiment, the barrier layer 800 is made of TiN.

In addition, a second contact opening 156 is formed in the interlayer dielectric layer 103 above the first gate structure 610 and in the interlayer dielectric layer 103 above the second gate structure 620, so the first In the step of performing the pre-cleaning process on the contact opening 155, the pre-cleaning process is also performed on the second contact opening 156; in the step of forming the barrier layer 800, the metal layer in the second contact opening 156 is also The barrier layer 800 is formed thereon.

Referring to FIG. 10, after the metal silicide layer 640 is formed, a conductive material is filled into the first contact opening 155 (as shown in FIG. 9 ), and a first contact hole plug is formed in the first contact opening 155. 850.

The first contact hole plug 850 is electrically connected to the source-drain doped region, and is used to realize the electrical connection within the semiconductor device, and is also used to realize the electrical connection between devices.

Specifically, the step of forming the first contact hole plug 850 includes: filling the first contact opening 155 with a conductive material, and the conductive material is also located on the top of the interlayer dielectric layer 103; The material is planarized to remove the conductive material higher than the top of the interlayer dielectric layer 103 , and the first contact hole plug 850 is formed in the first contact opening 155 .

In this embodiment, the material of the first contact hole plug 850 is W, and the first contact hole plug 850 may be formed by a chemical vapor deposition process, a sputtering process or an electroplating process. In other embodiments, the material of the first contact hole plug may also be a metal material such as Al, Cu, Ag or Au.

It should be noted that, a second contact opening 156 is formed in the interlayer dielectric layer 103 above the first gate structure 610 and in the interlayer dielectric layer 103 above the second gate structure 620 (as shown in FIG. 9 shown), therefore in the step of filling the first contact opening 155 with a conductive material, also fill the second contact opening 156 with a conductive material, forming a second contact hole plug in the second contact opening 156 Plug 860.

The second contact hole plug 860 is electrically connected to the gate structure, and is used to realize the electrical connection within the semiconductor device, and is also used to realize the electrical connection between devices.

Referring to FIG. 11 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Correspondingly, the present invention also provides a semiconductor structure, including:

The base, the base includes a substrate 900, a gate structure (not shown) on the substrate 900, source and drain doped regions (not shown) in the base on both sides of the gate structure, and The dielectric layer 902 on the base and covering the top of the gate structure, the substrate 900 includes a first region I with a P-type device and a second region II with an N-type device; a contact opening 950 is located in the The source and drain doped regions are exposed in the dielectric layer 902 on both sides of the gate structure, wherein the source and drain doped regions exposed by the contact opening 950 in the first region I and the second region II are performed in the same step Experienced P-type doping isolation Schottky doping process.

In this embodiment, the semiconductor structure is a fin field effect transistor, so the base further includes discrete fins (not shown) on the substrate 900 . In other embodiments, the semiconductor structure is a planar transistor, and correspondingly, the substrate is a planar substrate.

In this embodiment, the substrate 900 includes a first region I having P-type devices and a second region II having N-type devices. Correspondingly, the fins located on the substrate 900 in the first region I are the first fins 910 , and the fins located on the substrate 900 in the second region II are the second fins 920 . In other embodiments, the substrate may also include only the first region with P-type devices or only the second region with N-type devices.

The first area I and the second area II may be adjacent areas or non-adjacent areas. In this embodiment, the first area I and the second area II are adjacent areas.

Therefore, the gate structure located in the first region I is the first gate structure 941, and the first gate structure 941 crosses the first fin 910 and covers a part of the first fin 910. Wall surface and top surface; the gate structure located in the second region II is a second gate structure 942, and the second gate structure 942 spans the second fin 920 and covers the second fin Part of the sidewall surface and the top surface of the portion 920.

Correspondingly, the doped source and drain regions in the first fins 910 on both sides of the first gate structure 941 are first doped source and drain regions (not shown in the figure), and are located on both sides of the second gate structure 942. The source-drain doped region in the second fin portion 920 is the second source-drain doped region (not shown); the contact opening 950 located in the first region I exposes the first source-drain doped region, located in The contact opening 950 of the second region II exposes the second source-drain doped region.

In this embodiment, the substrate 900 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. substrate.

The material of the fin is the same as that of the substrate 900 . In this embodiment, the material of the fin is silicon, that is, the material of the first fin 910 and the second fin 920 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, the semiconductor structure further includes: an isolation structure 901 located on the substrate 900 between adjacent fins, the isolation structure 901 covers part of the sidewalls of the fins, and the isolation structure 901 top is lower than the fin top.

The isolation structure 901 is used as an isolation structure of a semiconductor device for isolating adjacent devices and fins. In this embodiment, the material of the isolation structure 901 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

It should be noted that, in this embodiment, the semiconductor structure further includes: a first epitaxial layer 912 located in the first fins 910 on both sides of the first gate structure 941 , located in the second gate structure 942 The second epitaxial layer 922 in the second fin portion 920 on both sides; wherein, the first doped source and drain region is located in the first epitaxial layer 912, and the second doped source and drain region is located in the second In the epitaxial layer 922 .

The material of the first epitaxial layer 912 may be Si or SiGe, and the doping ions of the first source-drain doping region include one or more of B, Ga and In. In this embodiment, the material of the first epitaxial layer 912 is Si; the doping ions of the first source-drain doping region are Ge ions. The doping concentration of Ge ions is determined according to actual process requirements. In this embodiment, the atomic percentage of Ge ions is 35% to 65%.

The material of the second epitaxial layer 922 may be Si or SiC, and the doping ions of the second source-drain doping region include one or both of P and As. In this embodiment, the material of the second epitaxial layer 922 is Si; the doping ions of the second source-drain doping region are P ions.

In this embodiment, the source and drain doped regions exposed by the contact opening 950 in the first region I and the second region II have undergone P-type doping isolation Schottky (Dopant Segregated Schottky, DSS) in the same step. Doping process, that is, both the first source-drain doped region and the second source-drain doped region have undergone a P-type doping isolation Schottky doping process; the doping ions in the doping process are P-type ions , used to reduce the Schottky barrier height (Schottky Barrier Height, SBH) of the first source-drain doped region and the channel region of the P-type device, correspondingly, the second source-drain doped region is also subjected to P Type ion doping; therefore in order to reduce the impact on the electrical performance of the N-type device, compared to the second source and drain doped region is not affected by the P-type doping isolation Schottky doping process In this case, the doping concentration of P ions in the second source-drain doped region in this embodiment is higher.

Specifically, the P ion doping concentration of the second source-drain doping region is determined according to actual process requirements and the doping concentration of the P-type doping isolation Schottky doping process. In this embodiment, the doping concentration of P ions in the second source-drain doped region is 1E21atom/cm ³ to 3E21atom/cm ³ .

It should also be noted that by increasing the P ion doping concentration of the second source-drain doped region, it is also beneficial to reduce the Schottky barrier height of the first source-drain doped region and the channel region, thereby It is beneficial to reduce the contact resistance of the second region II, thereby increasing the driving current of the N-type device.

In other embodiments, there may not be a first epitaxial layer in the first fins on both sides of the first gate structure, and there may be no second epitaxial layer in the second fins on both sides of the second gate structure; therefore The first doped source and drain region may be located in the first fin, and the second doped source and drain region may be located in the second fin.

The P-type doping isolation Schottky doping process is used to make the first source-drain doped region have P-type ions. In the actual process, when depositing metal on the first source-drain doped region layer to form a metal silicide (silicide) layer, the annealing process makes the metal layer and silicon react to form a metal silicide layer, and the annealing process also drives the P-type ions to segregate on the formed metal At the interface between the silicide layer and the silicon, the height of the Schottky barrier between the first source-drain doped region and the channel region can be reduced. Therefore, the doping ions of the P-type doping isolation Schottky doping process include one or more of B, Al, Ga and In. In this embodiment, the doping ion of the P-type doping isolation Schottky doping process is B.

It should be noted that, the source and drain doped regions exposed by the contact opening 950 in the first region I and the second region II have also undergone a pre-amorphization (Pre-amorphization Implant, PAI) ion implantation process, that is, the Both the first source-drain doped region and the second source-drain doped region have undergone a pre-amorphization ion implantation process; therefore, the semiconductor structure further includes: an amorphous silicon layer 960 located at the bottom of the contact opening 950, and The amorphous silicon layer 960 in the first region I is transformed from the first epitaxial layer 912, and the amorphous silicon layer 960 in the second region II is transformed from the second epitaxial layer 922. The amorphous silicon layer 960 is beneficial to improve the formation quality and quality uniformity of the metal silicide layer. In this embodiment, the implanted ions in the pre-amorphization ion implantation process are Ge ions.

In this embodiment, the gate structure is a metal gate structure, that is, the first gate structure 941 and the second gate structure 942 are metal gate structures. The gate structure includes a gate dielectric layer (not shown) spanning the fin and covering part of the top surface and sidewall surfaces of the fin, and a metal layer (not shown) on the gate dielectric layer, And the gate structure is located in the dielectric layer 902 .

In this embodiment, the gate dielectric layer includes an interfacial layer (IL, Interfacial Layer) (not marked) and a high-k gate dielectric layer (not marked) located on the surface of the interface layer.

The interface layer provides a good interface basis for forming the high-k gate dielectric layer, thereby improving the quality of the high-k gate dielectric layer and reducing the interface state density between the high-k gate dielectric layer and the fin, In addition, adverse effects caused by direct contact between the high-k gate dielectric layer and the fin are avoided. The material of the interface layer is silicon oxide or silicon oxynitride.

The material of the high-k gate dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

In this embodiment, the material of the metal layer is W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti.

It should be noted that, the semiconductor structure further includes: a sidewall 930 located on the sidewall of the gate structure, and the sidewall 930 is used to define the position of the source-drain doped region. The material of the side wall 930 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 930 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 930 is a single-layer structure, and the material of the sidewall 930 is silicon nitride.

The material of the dielectric layer 902 is an insulating material, and the dielectric layer 902 provides a process platform for the formation process of the contact hole plug. In this embodiment, the material of the dielectric layer 902 is silicon oxide. In other embodiments, the material of the dielectric layer may also be silicon nitride or silicon oxynitride.

In this embodiment, the semiconductor structure includes a contact opening 950, which is located in the dielectric layer 902 on both sides of the gate structure and exposes the source-drain doped region (not shown), wherein the first The source and drain doped regions exposed by the contact opening 950 in the first region I and the second region II have experienced the P-type doping isolation Schottky doping process in the same step; therefore, by adjusting the second If the doping concentration of the source-drain doping region of the region II reaches a reasonable value, additional use of a photomask can be avoided to perform the P-type doping isolation Schottky doping process, so the manufacturing cost of the semiconductor structure is relatively low. And the impact on N-type devices is small; at the same time, the Schottky barrier height of the source-drain doped region and the channel region of the first region I can still be reduced, thereby reducing the contact resistance of the first region I, Increase the driving current of the P-type device.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

1. A method for forming a semiconductor structure, comprising: forming a base, the base includes a substrate, a gate structure located on the substrate, source and drain doped regions located in the base on both sides of the gate structure, and a gate structure located on the base and covering the gate an interlayer dielectric layer on top of the structure, the substrate includes a first region for forming a P-type device and a second region for forming an N-type device; forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layer on both sides of the gate structure; performing a P-type doping isolation Schottky doping process on the source and drain doped regions exposed by the first contact opening in the first region and the second region; After the P-type doping isolation Schottky doping process is completed, a metal silicide layer is formed at the bottom of the first contact opening; After the metal silicide layer is formed, a conductive material is filled into the first contact opening, and a first contact hole plug is formed in the first contact opening. 2. the formation method of semiconductor structure as claimed in claim 1 is characterized in that, in the step of carrying out described P-type doping isolation Schottky doping process, described P-type doping isolation Schottky doping process The dopant ions include one or more of B, Al, Ga and In. 3. The formation method of semiconductor structure as claimed in claim 1 or 2, is characterized in that, described P-type doping isolation Schottky doping process is an ion implantation process, and described P-type doping isolation Schottky doping process The dopant ion of impurity process is B; The parameters of the ion implantation process include: the implanted ion source is B, the implanted ion energy is 500eV to 3KeV, and the implanted ion dose is 1E14atom/cm ² to 5E15atom/cm ² ; or, the implanted ion source is BF ₂ , The implanted ion energy is 1KeV to 10KeV, and the implanted ion dose is 1E14atom/cm ² to 5E15atom/cm ² . 4. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming a substrate, the source-drain doped region located in the first region is a first source-drain doped region, and the source-drain doped region located in the first region The source-drain doped region of the second region is the second source-drain doped region; The doping ions in the first source-drain doping region include Ge ions, and the atomic percentage content of Ge ions is 35% to 65%; The doping ions in the second source-drain doping region include P ions, and the doping concentration of the P ions is 1E21atom/cm ³ to 3E21atom/cm ³ . 5. The method for forming a semiconductor structure according to claim 1, wherein after forming the first contact opening and before forming the metal silicide layer, the forming method further comprises: and the source and drain doped regions in the second region are subjected to pre-amorphization treatment. 6. The method for forming a semiconductor structure according to claim 5, wherein the pre-amorphization treatment is an ion implantation process; The implanted ions in the ion implantation process are Ge ions, the implanted ion energy is 3KeV to 10KeV, and the implanted ion dose is 1E14atom/cm ² to 3E15atom/cm ² . 7. The method for forming a semiconductor structure according to claim 1, wherein the substrate is a substrate containing Si, and the step of forming the metal silicide layer comprises: conformally covering the surface of the first contact opening with metal layer; after the metal layer is formed, the substrate is annealed to make the metal layer react with the Si-containing substrate, and convert the metal layer into a metal silicide layer. 8. The method for forming a semiconductor structure according to claim 7, wherein the annealing treatment is laser annealing treatment or rapid thermal annealing treatment. 9. The method for forming a semiconductor structure according to claim 8, wherein the annealing treatment is laser annealing treatment, and the parameters of the laser annealing treatment include: the annealing temperature is 700° C. to 1000° C., and the pressure is a standard atmospheric pressure. 10. the formation method of semiconductor structure as claimed in claim 1 is characterized in that, the thickness of described metal silicide layer is to 11. The method for forming a semiconductor structure according to claim 1, wherein, after completing the P-type doping isolation Schottky doping process, before forming a metal silicide layer at the bottom of the first contact opening , the forming method further includes: forming a second contact opening exposing the top of the gate structure in the interlayer dielectric layer above the gate structure; In the step of filling the first contact opening with a conductive material, the second contact opening is also filled with a conductive material to form a second contact hole plug in the second contact opening. 12. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming a base, the base further comprises discrete fins located on the substrate; The gate structure spans the fin and covers part of the sidewall surface and the top surface of the fin; The source-drain doped region is located in the fins on both sides of the gate structure. 13. The method for forming a semiconductor structure according to claim 1, wherein the step of forming a substrate comprises: providing an initial substrate; etching the initial substrate to form the substrate and the discrete substrates on the substrate Fin, the substrate includes a first region for forming a P-type device and a second region for forming an N-type device; forming a dummy that spans the fin and covers the top surface and the sidewall surface of the fin portion gate structure; forming source and drain doped regions in the fins on both sides of the dummy gate structure; forming a bottom dielectric layer on the substrate exposed by the dummy gate structure, and the bottom dielectric layer exposes the top of the dummy gate structure; removing For the dummy gate structure, an opening is formed in the bottom dielectric layer; a gate structure is formed in the opening, and the top of the gate structure is flush with the top of the bottom dielectric layer; a layer is formed on the substrate an interlayer dielectric layer covering the top of the gate structure and the top of the bottom dielectric layer; or, The step of forming the base includes: providing an initial substrate; etching the initial substrate to form a substrate and discrete fins on the substrate, the substrate including a first region for forming a P-type device and A second region for forming an N-type device; forming a gate structure spanning the fin and covering part of the top surface and sidewall surface of the fin; forming source-drain doping in the fins on both sides of the gate structure region; an interlayer dielectric layer is formed on the exposed base of the gate structure, and the top of the interlayer dielectric layer is higher than the top of the gate structure. 14. A semiconductor structure, characterized in that it comprises: A substrate, the substrate comprising a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a substrate located on the substrate and covering the gate structure a top interlayer dielectric layer, the substrate includes a first region with a P-type device and a second region with an N-type device; contact openings, located in the interlayer dielectric layer on both sides of the gate structure and exposing the doped source and drain regions, wherein the doped source and drain regions exposed by the contact openings in the first region and the second region Go through the P-type doping isolation Schottky doping process in the same step. 15. The semiconductor structure according to claim 14, wherein the doping ions of the P-type doping isolation Schottky doping process include one or more of B, Al, Ga and In. 16. The semiconductor structure according to claim 14, wherein the source-drain doped region located in the first region is a first source-drain doped region, and the source-drain doped region located in the second region is the second source-drain doped region; The doping ions in the first source-drain doping region include Ge ions, and the atomic percentage content of Ge ions is 35% to 65%; The doping ions in the second source-drain doping region include P ions, and the doping concentration of P ions is 1E21atom/cm ³ to 3E21atom/cm ³ . 17. The semiconductor structure according to claim 14, wherein the doped source and drain regions exposed by the first contact opening in the first region and the second region have also undergone a pre-amorphization ion implantation process, The implanted ions in the pre-amorphization ion implantation process are Ge ions. 18. The semiconductor structure of claim 14, wherein the base further comprises discrete fins on the substrate; The gate structure spans the fin and covers part of the sidewall surface and the top surface of the fin; The source-drain doped region is located in the fins on both sides of the gate structure.