CN108257915A - A kind of manufacturing method of semiconductor devices - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate on which a gate trench is formed; forming a high-k dielectric layer at the bottom of the gate trench; forming a sacrificial layer over the high-k dielectric layer; performing a first anneal in an oxygen-containing atmosphere; removing the sacrificial layer. According to the manufacturing method of the present invention, a sacrificial layer is formed on the high-k dielectric layer, and then annealed, in addition to reducing defects (such as oxygen holes) in the high-k dielectric layer, the sacrificial layer can also be used Prevent excessive oxygen from entering the high-k dielectric layer in the annealing process, because the defects in the high-k dielectric layer are significantly reduced, therefore, the method of the present invention improves the reliability of the device (for example, reliability such as PBTI and NBTI), and improves performance of the device.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device.

Background technique

With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits.

For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices can use Ge channels, while NMOS devices can use III-V compound semiconductors (such as InGaAs) as channels to increase carrier density. mobility. Due to the continuous shrinking of technology nodes, the application of high-k dielectric layer can increase the physical thickness of the gate dielectric film while keeping the gate capacitance unchanged, so as to reduce the leakage current of the gate dielectric layer and improve the reliability of the device. However, using the existing manufacturing process, the formed high-k dielectric layer often has many defects such as oxygen vacancy defects, the existence of these defects is critical to the reliability of the device, for example, to the time-dependent dielectric breakdown (Time Dependent Dielectric Breakdown, referred to as TDDB), negative bias temperature instability (Negative Bias Temperature Instability, referred to as NBTI), positive bias temperature instability (Positive Bias Temperature Instability, referred to as PBTI) and other negative effects.

Therefore, in order to solve the above technical problems, it is necessary to propose a new method for manufacturing semiconductor devices.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

Aiming at the deficiencies in the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate on which a gate trench is formed;

forming a high-k dielectric layer at the bottom of the gate trench;

forming a sacrificial layer over the high-k dielectric layer;

performing a first anneal under an oxygen-containing atmosphere;

The sacrificial layer is removed.

Exemplarily, the high-k dielectric layer is further formed on sidewalls of the gate trench, and the sacrificial layer is further formed above the high-k dielectric layer on the sidewalls.

Exemplarily, the semiconductor substrate includes an NMOS device region and a PMOS device region, wherein the gate trench, the high-k dielectric region are formed in the NMOS device region and the PMOS device region. layer and the sacrificial layer.

Exemplarily, the channel material under the gate trench in the NMOS device region includes III-V compound semiconductors, and the channel material under the gate trench in the PMOS device region includes elemental semiconductors.

Exemplarily, the III-V compound semiconductor is InGaAs, and the elemental semiconductor is Ge.

Exemplarily, before forming the high-k dielectric layer, a step of forming an interface layer at the bottom of the gate trench in the PMOS device region is further included.

Exemplarily, the first annealing temperature ranges from 800°C to 1000°C, and the oxygen-containing atmosphere includes one or more of ISSG, N ₂ O, NO, O ₂ and O ₃ .

Exemplarily, the material of the sacrificial layer is an amorphous semiconductor material.

Exemplarily, the amorphous semiconductor material includes amorphous silicon or amorphous germanium.

Exemplarily, before forming the sacrificial layer, after forming the high-k dielectric layer, the method further includes: performing a second annealing step.

Exemplarily, the second annealing is performed under H ₂ atmosphere.

Exemplarily, the second annealing is high temperature and high pressure annealing, the temperature range of the second annealing is 700° C. to 900° C., and the pressure range of the second annealing is 100 Torr˜3 atm.

Exemplarily, the first annealing temperature is higher than the second annealing temperature.

Exemplarily, after removing the sacrificial layer, the following steps are further included:

forming a first diffusion barrier layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region;

forming a P-type work function layer on the bottom and sidewalls of the gate trench in the PMOS device region, the P-type work function layer being located on the surface of the first diffusion barrier layer;

forming an N-type work function layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region;

forming a second diffusion barrier layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region;

A gate electrode layer is filled in the gate trenches in the NMOS device region and the PMOS device region.

According to the manufacturing method of the present invention, a sacrificial layer is formed on the high-k dielectric layer, and then the first annealing treatment is performed under an oxygen-containing atmosphere to reduce defects in the high-k dielectric layer. A sacrificial layer is formed on the k dielectric layer and then annealed. In addition to reducing the defects (such as oxygen holes) in the high-k dielectric layer, the sacrificial layer can also be used to prevent excessive oxygen from entering during the annealing process. For the high-k dielectric layer, since the defects in the high-k dielectric layer are obviously reduced, the method of the present invention improves the reliability of the device (for example, the reliability of PBTI and NBTI, etc.), and improves the performance of the device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1A to FIG. 1E show schematic structural diagrams of devices obtained in the relevant steps of the manufacturing method of a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, detailed steps will be provided in the following description, so as to explain the technical solution proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

In order to solve the foregoing technical problems and improve the performance of the device, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in FIG. 2 , the method mainly includes:

Step S1, providing a semiconductor substrate, on which a gate trench is formed;

Step S2, forming a high-k dielectric layer at the bottom of the gate trench;

Step S3, forming a sacrificial layer on the high-k dielectric layer;

Step S4, performing the first annealing in an oxygen-containing atmosphere;

Step S5, removing the sacrificial layer.

According to the manufacturing method of the present invention, a sacrificial layer is formed on the high-k dielectric layer, and then the first annealing treatment is performed under an oxygen-containing atmosphere to reduce defects in the high-k dielectric layer. A sacrificial layer is formed on the k dielectric layer and then annealed. In addition to reducing the defects (such as oxygen holes) in the high-k dielectric layer, the sacrificial layer can also be used to prevent excessive oxygen from entering during the annealing process. For the high-k dielectric layer, since the defects in the high-k dielectric layer are obviously reduced, the method of the present invention improves the reliability of the device (for example, the reliability of PBTI and NBTI, etc.), and improves the performance of the device.

Specifically, the method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to FIGS. Schematic diagram of the structure.

First, step 1 is performed to provide a semiconductor substrate on which gate trenches are formed.

Specifically, as shown in FIG. 1A, the semiconductor substrate 100 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), germanium-on-insulator Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

In one example, the semiconductor substrate includes an NMOS device region and a PMOS device region, wherein a gate trench 1021 is formed in the NMOS device region, and a gate trench 1022 is formed in the PMOS device region .

Exemplarily, the channel material under the gate trench in the NMOS device region may include group III-V compound semiconductors, for example, group III-V binary or ternary compound semiconductors. In this embodiment, the The III-V group compound semiconductor is InGaAs, and the channel material under the gate trench in the PMOS device region includes an elemental semiconductor, wherein the elemental semiconductor material can be any elemental semiconductor known to those skilled in the art, including but It is not limited to Ge or Si, or the channel material under the gate trench in the PMOS device region includes SiGe. In this embodiment, the elemental semiconductor is Ge, and a III-V compound semiconductor is used as the channel of the NMOS device. The use of elemental semiconductors as the channel of PMOS devices can improve carrier mobility.

It is worth mentioning that elemental semiconductors refer to semiconductors composed of a single element.

Exemplarily, the semiconductor device of the present invention is a FinFET device, and a first fin structure is formed on the semiconductor substrate in the NMOS device region, and a fin structure is formed on the semiconductor substrate in each of the PMOS device regions. In the second fin structure, the gate trench 1021 exposes part of the surface of the first fin structure, and the gate trench 1022 exposes part of the surface of the second fin structure.

In one example, taking a FinFET device as an example, in order to obtain the structure shown in Figure 1A, the following steps A1 to A5 can be performed:

In one example, to obtain the structure shown in Figure 1A, the following process steps may be performed:

First, step A1 is performed to form a plurality of fin structures on the semiconductor substrate, for example, a first fin structure and a second fin structure are respectively formed in the NMOS device region and the PMOS device region on the semiconductor substrate. For the two-fin structure, the widths of the fin structures are all the same, or the fins are divided into multiple fin structure groups with different widths, and the lengths of the fin structures may also be different.

Specifically, the forming method of the fin structure is not limited to a certain one, and an exemplary forming method is given below: forming a hard mask layer (not shown in the figure) on the semiconductor substrate, forming the The hard mask layer can adopt various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process, and the hard mask layer can be an oxide layer and a silicon nitride layer stacked from bottom to top; pattern The hard mask layer is formed to form a plurality of masks isolated from each other for etching the semiconductor substrate to form fins thereon. In one embodiment, the self-aligned double patterning (SADP) process is used to implement the Patterning process; etching a semiconductor substrate to form fin structures thereon.

Subsequently, step A2 may also be performed to deposit an isolation material layer to cover all the aforementioned fin structures.

Specifically, a layer of isolation material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be oxide, such as high aspect ratio process (HARP) oxide, specifically silicon oxide.

The isolation material layer is then etched back to a target height of the fin structure to form an isolation structure whose top surface is lower than the top surfaces of the first fin structure and the second fin structure. Specifically, the isolation material layer is etched back to expose part of the fin structure, thereby forming a fin structure with a specific height.

Next, step A3 is performed to form a first dummy gate structure across the first fin structure and a second dummy gate structure across the second fin structure, wherein the dummy gate structures both include dummy gate interlayers. Electrical layer and dummy gate material layer.

It should be pointed out that the term "straddling" used in the present invention, for example, straddling the dummy gate structure of the fin structure (such as the first fin structure, the second fin structure, etc.), refers to the A dummy gate structure is formed on both the upper surface and side surfaces of part of the semiconductor substrate, and the dummy gate structure is also formed on a part of the surface of the semiconductor substrate.

In one example, a dummy gate dielectric layer and a dummy gate material layer may be sequentially deposited on a semiconductor substrate first.

Wherein, the dummy gate dielectric layer can be a commonly used oxide, such as SiO ₂ , and the dummy gate material layer can be a semiconductor material commonly used in the field, such as polysilicon, etc., and is not limited to a certain kind. , will not be enumerated here,

The deposition method of the dummy gate material layer can be selected from methods such as chemical vapor deposition or atomic layer deposition.

Then pattern the dummy gate dielectric layer and the dummy gate material layer to form the first dummy gate structure and the second dummy gate structure. Specifically, a photoresist layer is formed on the dummy gate material layer, then exposed and developed to form an opening, and then the dummy gate material layer is etched using the photoresist layer as a mask, and finally the photoresist layer is removed. glue layer.

Afterwards, optionally, offset spacers are formed on the sidewalls of the first dummy gate structure and the second dummy gate structure.

Specifically, the offset sidewall may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the offset sidewall is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second silicon nitride layer on a semiconductor substrate. The silicon dioxide layer is then etched to form offset sidewalls. It is also possible to form a sidewall material layer on both the top surface and the sidewall of the dummy gate structure, and in a subsequent step, the sidewall material layer on the top surface is removed by a planarization method, such as chemical mechanical polishing, to form only Offset side walls on side walls.

Optionally, an LDD ion implantation step is performed on both sides of the first dummy gate structure and the second dummy gate structure and activated.

Optionally, a spacer is formed on the offset sidewall of the dummy gate structure.

Specifically, a spacer is formed on the formed offset side wall, and the spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second oxide layer on a semiconductor substrate. Silicon layer, and then use etching method to form spacers.

Next, perform step A4, perform source-drain implantation, and form the source/drain of the NMOS device in the first fin structure on both sides of the aforementioned first dummy gate structure, and form the source/drain of the second dummy gate structure on both sides The source/drain of the PMOS device is formed in the second fin structure.

It also includes the step of: growing a stress layer on the source/drain regions on both sides of the first dummy gate structure and the second dummy gate structure. In the CMOS transistor, a stress layer with tensile stress is usually formed on the NMOS transistor, and on the PMOS transistor A stress layer with compressive stress is formed, and the performance of the CMOS device can be improved by applying the tensile stress to the NMOS and the compressive stress to the PMOS. In the prior art, SiC is generally selected as the tensile stress layer in NMOS transistors, and SiGe is generally selected as the compressive stress layer in PMOS transistors.

Preferably, when the SiC is grown as a tensile stress layer, it can be epitaxially grown on the substrate, and the raised source and drain are formed after ion implantation. When the SiGe layer is formed, a recess is usually formed in the substrate grooves, and then deposit a SiGe layer in the grooves. More preferably, a "Σ" shaped groove is formed in the substrate.

Next, step A5 is performed to deposit and planarize the interlayer dielectric layer 101 to fill the gaps between the respective dummy gate structures.

Specifically, the interlayer dielectric layer 101 is deposited and planarized, and the pair of interlayer dielectric layers 101 is planarized to the top of the first dummy gate structure and the second dummy gate structure.

Wherein, the interlayer dielectric layer 101 can be selected from dielectric materials commonly used in this field, such as various oxides, etc. In this embodiment, the interlayer dielectric layer can be selected from SiO ₂ , and its thickness is not limited to a certain a value.

Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.

Afterwards, the first dummy gate structure and the second dummy gate structure are removed, including sequentially removing the dummy gate dielectric layer and the dummy gate material layer, so as to form a gate trench 1021 on the semiconductor substrate 100 in the NMOS device region , forming a gate trench 1022 on the semiconductor substrate 100 in the PMOS device region, the gate trench in the NMOS device region exposes part of the first fin structure in the extending direction of the first fin structure, The gate trench of the PMOS device region exposes part of the second fin structure in the extending direction of the second fin structure.

Next, step 2 is performed to form an interface layer at the bottom of the gate trench in the PMOS device region.

Specifically, as shown in FIG. 1B, an interfacial layer 103 is formed at the bottom of the gate trench 1022 in the PMOS device region, and the function of the interfacial layer (IL) 103 is to improve the contact between the high-k dielectric layer and the semiconductor. Interface properties between substrates.

The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer or other suitable thin film layers. The interfacial layer can be formed by suitable processes such as thermal oxidation, chemical oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

In this embodiment, the interface layer 103 may be a chemical oxide layer. For example, a chemical oxidation method using an ozone (Ozone) treatment solution may be used to form a chemical oxidation layer as the interface layer 103 . Specifically, the material of the interface layer 103 can be determined according to the channel material at the bottom of the gate trench 1022. In this embodiment, the channel of the PMOS device is Ge, and the interface layer 103 is an oxide of germanium, for example GeO ₂ .

The thickness of the interface layer 103 can be reasonably set according to actual process requirements, for example, the thickness of the interface layer 103 can range from 5 angstroms to 10 angstroms.

In this embodiment, the interface layer is only formed at the bottom of the gate trench in the PMOS device region, while no interface layer is formed at the bottom of the gate trench in the NMOS device region.

Among them, for PMOS devices, it uses such as Ge channel or SiGe channel, and IL is needed on the surface of the channel to improve the NBTI of PMOS devices, while the channel of NMOS is a III-V compound semiconductor such as InGaAs, and the channel It is very difficult to form oxides on the surface of the surface, for example, the oxide of InGaAs. Generally, the PBTI of NMOS itself is not a big problem, and it is easier to meet the needs of the device. Therefore, for NMOS, it is not necessary to make an interface layer on the surface of the trench. .

Next, step 3 is performed to form a high-k dielectric layer at the bottom of the gate trench.

Specifically, as shown in FIG. 1B, a high-k dielectric layer 104 is formed on the sidewalls and bottoms of the gate trench 1021 in the NMOS device region and the gate trench 1022 in the PMOS device region. Further, the high-k dielectric layer 104 The k-dielectric layer covers the surface of the interlayer dielectric layer 101 .

In one example, the high-k dielectric layer may also be formed only on the bottom of the gate trenches of the NMOS device region and the gate trenches of the PMOS device region.

The k value (dielectric constant) of the high-k dielectric layer 104 is usually above 3.9, and its constituent materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, and tantalum oxide , barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide or aluminum oxide. The high-k dielectric layer 104 can be formed by suitable processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

The thickness of the high-k dielectric layer 104 ranges from 10 angstroms to 30 angstroms, and other suitable thicknesses are also possible.

Next, step 4 is performed to perform annealing.

In one example, the annealing is performed under _H2 atmosphere. The annealing may adopt an annealing process such as furnace tube annealing, rapid annealing, spike anneal (spike anneal) or laser annealing.

Optionally, the annealing is high temperature and high pressure annealing, the annealing temperature ranges from 700°C to 900°C, and the annealing pressure ranges from 100 Torr to 3 atm (standard atmospheric pressure).

Among them, annealing under a hydrogen atmosphere can passivate the interface layer and the dangling bonds on the surface of the semiconductor substrate at the junction with the high-k dielectric layer, for example, passivate the surface of the trench under the high-k dielectric layer in the NMOS device region dangling bonds (for example, dangling bonds on the surface of InGaAs), further improving the interface state between the high-k dielectric layer and the semiconductor substrate.

Next, step five is performed, forming a sacrificial layer on the high-k dielectric layer.

Specifically, as shown in FIG. 1D, a sacrificial layer 105 is formed on the sidewall and bottom of the gate trench 1021 in the NMOS device region and the gate trench 1022 in the PMOS device region, and the sacrificial layer 105 is located in the on the surface of the high-k dielectric layer 104 .

Further, the material of the sacrificial layer 105 is an amorphous semiconductor material. Wherein, the amorphous semiconductor material includes amorphous silicon (a-Si) or amorphous germanium (a-Ge), and may also be other suitable amorphous semiconductor materials.

The method of forming the sacrificial layer includes chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and Generally similar methods such as sputtering and physical vapor deposition (PVD) can be used.

Wherein, the thickness of the formed sacrificial layer 105 ranges from 10 angstroms to 50 angstroms, and may also be other suitable thicknesses.

Afterwards, step six is performed, annealing is performed in an oxygen-containing atmosphere to reduce defects in the high-k dielectric layer.

Exemplarily, the annealing temperature ranges from 800°C to 1000°C, and the oxygen-containing atmosphere includes one or more of in-situ water vapor (ISSG), N ₂ O, NO, O ₂ and O ₃ , Other suitable gases containing oxygen can also be used as the annealing atmosphere.

The annealing may adopt an annealing process such as furnace tube annealing, rapid annealing, spike anneal (spike anneal) or laser annealing.

Wherein, the annealing temperature in this step is preferably higher than the annealing temperature in the aforementioned step 4.

The function of the annealing in this step is to reduce the defects in the high-k dielectric layer 104, especially the oxygen vacancy defects, and since a sacrificial layer is formed on the high-k dielectric layer, further annealing can reduce the high-k dielectric layer 104. In addition to the effect of defects (such as oxygen holes) in the electrical layer, the sacrificial layer can also be used to prevent excessive oxygen from entering the high-k dielectric layer during annealing.

In this step, at least part of the sacrificial layer is oxidized to form an oxide.

Subsequently, step seven is performed to remove the sacrificial layer.

The sacrificial layer can be removed by any suitable etching method known to those skilled in the art, such as dry etching or wet etching, preferably, the sacrificial layer is removed by wet etching.

According to the specific material used for the sacrificial layer, a suitable wet etching method is selected, for example, a wet etchant including HF is selected for wet etching.

Finally, a conventional metal gate structure process is performed. In one example, as shown in FIG. 1E , process steps B1 to B5 are performed:

Step B1, forming a first diffusion barrier layer 106 on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region;

Specifically, the first diffusion barrier layer 106 can also be selectively provided, and the material of the first diffusion barrier layer 106 can be selected as but not limited to TaN, Ta, TaAl or other suitable thin film layers. In this embodiment, the material of the first diffusion barrier layer 106 is TaN. The first diffusion barrier layer 106 can be formed by a suitable process such as CVD, ALD or PVD. The thickness of the first diffusion barrier layer 106 ranges from 0 angstroms to 20 angstroms.

In one example, before forming the first diffusion barrier layer 106, a capping layer (not shown) may be optionally formed on the high-k dielectric layer, and the material of the capping layer may be La ₂ O3, Al ₂ O ₃ , Ga ₂ O ₃ , In ₂ O ₃ , MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN, TixN1-x or other suitable thin film layers.

Step B2, forming a P-type work function layer 107 on the bottom and side walls of the gate trench in the PMOS device region, and the P-type work function layer 107 is located on the surface of the first diffusion barrier layer 106 ;

Specifically, the material of the P-type work function layer 107 may be selected from but not limited to TixN1-x, TaC, MoN, TaN or a combination thereof or other suitable thin film layers. In this embodiment, TiN is selected as the P-type work function layer 107 . The P-type work function layer 107 can be formed by suitable processes such as CVD, ALD or PVD. The thickness of the P-type work function layer ranges from 10 angstroms to 580 angstroms, but is not limited to this range.

Step B3, forming an N-type work function layer 108 on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region, wherein the N-type work function layer 108 in the NMOS device region Layer 108 is located on the surface of the first diffusion barrier layer 106, and the N-type work function layer 108 is located on the surface of the P-type work function layer 107 in the PMOS device region;

The material of the N-type work function layer 108 can be selected as but not limited to TaAlC, TaC, Ti, Al, TixAl1-x or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The N-type work function layer can be formed by suitable processes such as CVD, ALD or PVD. The thickness of the N-type work function layer may range from 10 angstroms to 80 angstroms.

Step B4, forming a second diffusion barrier layer 109 on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region, the second diffusion barrier layer 109 is located on the N-type on the surface of the work function layer 108;

The second diffusion barrier layer 109 can also be selectively provided, and the material of the second diffusion barrier layer 109 can be selected as but not limited to TaN, Ta, TaAl or other suitable thin film layers.

After forming the above film layers, a planarization process, such as chemical mechanical polishing, can also be performed on the surface of the interlayer dielectric layer 101 to remove excess film layers on the surface of the interlayer dielectric layer 101 .

Step B5, filling the gate electrode layer 110 in the gate trenches in the NMOS device region and the PMOS device region, so as to finally form metal gate structures in both the NMOS device region and the PMOS device region.

The gate electrode layer 110 fills the gate trench, and the material of the gate electrode layer 110 can be selected as but not limited to Al, W or other suitable thin film layers. The gate electrode layer 110 may be formed by suitable processes such as CVD, ALD or PVD.

In one example, a gate electrode layer may be deposited first to fill the gate trench and cover the surface of the interlayer dielectric layer, and then perform a planarization process, such as chemical mechanical polishing, to stop on the surface of the interlayer dielectric layer.

So far, the detailed description of the manufacturing method of the semiconductor device of the present invention has been completed, and other process steps may be required for the manufacture of a complete device, which will not be repeated here.

In summary, according to the manufacturing method of the present invention, a sacrificial layer is formed on the high-k dielectric layer, and then annealed in an oxygen-containing atmosphere to reduce defects in the high-k dielectric layer. Forming a sacrificial layer on the high-k dielectric layer and performing annealing, in addition to reducing the defects (such as oxygen holes) in the high-k dielectric layer, the sacrificial layer can also be used to prevent excessive Oxygen enters the high-k dielectric layer.

In addition, after the formation of the high-k dielectric layer and before the formation of the sacrificial layer, a one-step annealing process is performed. Annealing in a hydrogen atmosphere can passivate the interface layer and the dangling bonds on the surface of the semiconductor substrate at the junction with the high-k dielectric layer. For example, passivating the dangling bonds on the surface of the trench under the high-k dielectric layer in the NMOS device region (for example, the dangling bonds on the surface of InGaAs), further improving the interface state between the high-k dielectric layer and the semiconductor substrate.

Therefore, the method of the present invention improves the reliability of the device (for example, the reliability of PBTI and NBTI, etc.), and improves the performance of the device.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (14)

1. A method for manufacturing a semiconductor device, characterized in that the method comprises: providing a semiconductor substrate on which a gate trench is formed; forming a high-k dielectric layer at the bottom of the gate trench; forming a sacrificial layer over the high-k dielectric layer; performing a first anneal under an oxygen-containing atmosphere; The sacrificial layer is removed. 2. The manufacturing method according to claim 1, wherein the high-k dielectric layer is also formed on the sidewall of the gate trench, and the sacrificial layer is also formed on the sidewall of the gate trench. above the high-k dielectric layer. 3. The manufacturing method according to claim 1 or 2, wherein the semiconductor substrate comprises an NMOS device region and a PMOS device region, wherein both the NMOS device region and the PMOS device region are formed There is the gate trench, the high-k dielectric layer and the sacrificial layer. 4. The manufacturing method according to claim 3, wherein the channel material under the gate trench in the NMOS device region comprises III-V compound semiconductors, and the gate in the PMOS device region The channel material below the trench includes an elemental semiconductor. 5. The manufacturing method according to claim 4, wherein the III-V compound semiconductor is InGaAs, and the elemental semiconductor is Ge. 6. The manufacturing method according to claim 1 or 2, further comprising the step of forming an interface layer at the bottom of the gate trench in the PMOS device region before forming the high-k dielectric layer . 7. The manufacturing method according to claim 1, wherein the temperature range of the first annealing is 800°C to 1000°C, and the oxygen-containing atmosphere includes ISSG, N ₂ O, NO, O ₂ and O ₃ one or more of them. 8. The manufacturing method according to claim 1, wherein the material of the sacrificial layer is an amorphous semiconductor material. 9. The manufacturing method according to claim 8, wherein the amorphous semiconductor material comprises amorphous silicon or amorphous germanium. 10 . The manufacturing method according to claim 1 , further comprising: performing a second annealing step after forming the high-k dielectric layer before forming the sacrificial layer. 11 . 11. The manufacturing method according to claim 10, wherein the second annealing is performed in an _H2 atmosphere. 12. The manufacturing method according to claim 10, wherein the second annealing is high temperature and high pressure annealing, the temperature range of the second annealing is 700°C-900°C, and the pressure range of the second annealing is 100Torr～3atm. 13. The manufacturing method according to claim 10, wherein the temperature of the first annealing is higher than the temperature of the second annealing. 14. The manufacturing method according to claim 3, further comprising the following steps after removing the sacrificial layer: forming a first diffusion barrier layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region; forming a P-type work function layer on the bottom and sidewalls of the gate trench in the PMOS device region, the P-type work function layer being located on the surface of the first diffusion barrier layer; forming an N-type work function layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region; forming a second diffusion barrier layer on the bottom and sidewalls of the gate trench in the NMOS device region and the PMOS device region; A gate electrode layer is filled in the gate trenches in the NMOS device region and the PMOS device region.