CN108255516A - Sequence synchronization multiline procedure processor and its instruction execution control method, device - Google Patents
Sequence synchronization multiline procedure processor and its instruction execution control method, device Download PDFInfo
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- CN108255516A CN108255516A CN201611245642.3A CN201611245642A CN108255516A CN 108255516 A CN108255516 A CN 108255516A CN 201611245642 A CN201611245642 A CN 201611245642A CN 108255516 A CN108255516 A CN 108255516A
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- 238000011084 recovery Methods 0.000 claims description 4
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- 238000012986 modification Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/3009—Thread control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
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- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
A kind of sequence synchronization multiline procedure processor and its instruction execution control method, device, the sequence synchronization multiline procedure processor includes decoder, the decoder includes multiple decoding units, and each decoding unit is used to correspond to the Instruction decoding of thread, the method includes：When identifying the WFE instruction or WFI instructions that decoding obtains, control targe thread decoding unit stops sending the instruction of corresponding thread, and other decoding units in the decoder is controlled to continue to decode and send the instruction of respectively corresponding thread, wherein, thread corresponding decoding unit of the subject thread decoding unit to decode out WFE instruction or WFI instructions in the decoder；When identifying the corresponding event of the WFE instruction or identifying that the WFI instructs corresponding interruption, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.Said program can promote the hardware resource utilization of processor.
Description
Technical field
The present invention relates to processor architecture technical field, more particularly to a kind of sequence synchronization multiline procedure processor and its instruction
Perform control method, device.
Background technology
Synchronizing multiple threads (SMT) are a kind of the instruction from multiple threads to be able to carry out within the clock cycle of single cpu
Hardware multithread technology.Substantially, synchronizing multiple threads are that a kind of be converted into the Thread-Level Parallelism processing based on multi -CPU is based on
The method of the instruction level parallel processing of same CPU.Synchronizing multiple threads technology can realize single physical processor from multiple hardware
Thread context while dispatched instructions.Herein referred synchronous multiline procedure processor is the processing using synchronizing multiple threads technology
Device.
WFI (Wait for Interrupt) is instructed and WFE (Wait for Event) instructions are two and allow arm processor
Into the instruction of low-power consumption mode.In the prior art, the synchronous multiline procedure processor that sequence performs is in processing WFI instructions or WFE
There are problems that hardware resource waste during instruction.
Invention content
Present invention solves the technical problem that it is the resource utilization for improving sequence synchronization multiline procedure processor execute instruction.
It is performed in order to solve the above technical problems, the embodiment of the present invention provides a kind of instruction of sequence synchronization multiline procedure processor
Control method, the sequence synchronization multiline procedure processor include decoder, and the decoder includes multiple decoding units, Mei Yiyi
Code unit is used to correspond to the Instruction decoding of thread, the sequence synchronization multiline procedure processor, and described instruction performs control method packet
It includes：
When identifying the WFE instruction or WFI instructions that decoding obtains, control targe thread decoding unit, which stops sending, to be corresponded to
The instruction of thread, and other decoding units in the decoder is controlled to continue to decode and send the instruction of respectively corresponding thread,
Wherein, thread corresponding decoding of the subject thread decoding unit to decode out WFE instruction or WFI instructions in the decoder
Unit；
When identifying the corresponding event of the WFE instruction or identifying that the WFI instructs corresponding interruption, institute is controlled
Subject thread decoding unit is stated to restore to send the instruction of corresponding thread.
Optionally, the instruction execution control method of the sequence synchronization multiline procedure processor, further includes：
When the subject thread decoding unit is controlled to stop sending the instruction of corresponding thread, stop together to the thread
Instruction carries out fetching.
Optionally, the instruction execution control method of the sequence synchronization multiline procedure processor, further includes：
Before restoring to send the instruction of corresponding thread in the subject thread decoding unit, the subject thread is rinsed in control
Data in decoding unit and the corresponding Fetch unit of the subject thread decoding unit.
Optionally, the execution stream that the WFE instruction or WFI instructions reach write back stage and be not take up when waiting in assembly line
Water unit.
Optionally, the quantity of the thread is 2.
The embodiment of the present invention also provides a kind of instruction execution controller of sequence synchronization multiline procedure processor, the sequence
Synchronous multiline procedure processor includes decoder, and the decoder includes multiple decoding units, and each decoding unit is used to correspond to line
The Instruction decoding of journey, described device include：
First control unit, suitable for when identifying the WFE instruction or WFI instructions that decoding obtains, control targe thread is translated
Code unit stops sending the instruction of corresponding thread, and other decoding units in the decoder is controlled to continue to decode and send each
From the instruction of corresponding thread, wherein, the subject thread decoding unit is to decode out WFE instruction in the decoder or WFI refers to
The corresponding decoding unit of thread of order；
Recovery unit, suitable for that ought identify the corresponding event of the WFE instruction or identify that the WFI instructions are corresponding
During interruption, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.
Optionally, the instruction execution controller of the sequence synchronization multiline procedure processor, further includes：
Second control unit, suitable for when the subject thread decoding unit is controlled to stop sending the instruction of corresponding thread,
Stop the instruction to the thread together and carry out fetching.
Optionally, the instruction execution controller of the sequence synchronization multiline procedure processor, further includes：
Rinsing unit, suitable for before restoring to send the instruction of corresponding thread in the subject thread decoding unit, control is rushed
Wash the data in the subject thread decoding unit and the corresponding Fetch unit of the subject thread decoding unit.
Optionally, the execution stream that the WFE instruction or WFI instructions reach write back stage and be not take up when waiting in assembly line
Water unit.
Optionally, the quantity of the thread is 2.
The embodiment of the present invention also provides a kind of sequence synchronization multiline procedure processor, the sequence synchronization multiline procedure processor,
Including：The instruction of multiple Fetch units, decoder, execution unit and said sequence synchronous multiline procedure processor performs control
Device, wherein, the decoder includes multiple decoding units, and each decoding unit is used to correspond to the Instruction decoding of thread.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
During the present invention is implemented, when identifying the WFE instruction or WFI instructions that decoding obtains, the decoding of control targe thread is single
Member stops sending the instruction of corresponding thread, and control other decoding units in the decoder continue to decode and sends it is respective right
The instruction of thread is answered, wherein, the subject thread decoding unit is that WFE instruction or WFI instructions are decoded out in the decoder
The corresponding decoding unit of thread；In identifying the corresponding event of the WFE instruction or identifying that the WFI instructions are corresponding
When disconnected, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.In the prior art, when decoding obtains WFE
When instruction or WFI are instructed, all decoding units, which all stop sending to execution unit, to be instructed, however, holding in the technical program
Row unit still can continue to execute the instruction that other decoding units are decoded and sent, so as to improve the utilization of resources of processor
Rate.
Description of the drawings
Fig. 1 is a kind of flow of the instruction execution control method of sequence synchronization multiline procedure processor in the embodiment of the present invention
Figure；
Fig. 2 is a kind of structure diagram of sequence synchronization multiline procedure processor of instruction execution control method in application drawing 1；
Fig. 3 is a kind of structure of the instruction execution controller of sequence synchronization multiline procedure processor in the embodiment of the present invention
Schematic diagram.
Specific embodiment
As described in the background art, in the prior art, synchronous multiline procedure processor is in processing WFI instructions or the mistake of WFE instruction
There are problems that hardware resource waste in journey.This is because when decoding obtains WFE instruction or WFI is instructed, WFE instruction or WFI
Instruction reach perform flowing water write back stage and waiting, and all decoding units that different threads are corresponded in decoder all stop to
Execution unit sends instruction, until the corresponding event of WFE instruction arrive or WFI instructions it is corresponding interrupt to arrive just restore to holding
Row unit sends instruction, so as to cause the free time of the hardware resource of execution unit and waste.
During the present invention is implemented, when identifying the WFE instruction or WFI instructions that decoding obtains, the decoding of control targe thread is single
Member stops sending the instruction of corresponding thread, and control other decoding units in the decoder continue to decode and sends it is respective right
Answer the instruction of thread.Wherein, the subject thread decoding unit is that WFE instruction or WFI instructions are decoded out in the decoder
The corresponding decoding unit of thread；In identifying the corresponding event of the WFE instruction or identifying that the WFI instructions are corresponding
When disconnected, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.In the prior art, when decoding obtains WFE
When instruction or WFI are instructed, all decoding units, which all stop sending to execution unit, to be instructed, however, holding in the technical program
Row unit still can continue to execute the instruction that other decoding units are decoded and sent, so as to improve the utilization of resources of processor
Rate.
It is understandable for above-mentioned purpose, feature and advantageous effect of the invention is enable to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 1 is a kind of flow of the instruction execution control method of sequence synchronization multiline procedure processor in the embodiment of the present invention
Figure.It is illustrated with reference to Fig. 1 and Fig. 2.
Step S101：When identifying the WFE instruction or WFI instructions that decoding obtains, control targe thread decoding unit stops
The instruction of corresponding thread is only sent, and other decoding units in the decoder is controlled to continue to decode and send respectively corresponding line
The instruction of journey, wherein, the subject thread decoding unit is the thread that WFE instruction or WFI instructions are decoded out in the decoder
Corresponding decoding unit.
WFE instruction and WFI instructions are the instruction in arm processor instruction set, enter low-power consumption mould for control processor
Formula, until occurring corresponding to the event of WFE instruction or occurring corresponding to the interruption of WFI instructions.
It is more that sequence synchronization multiline procedure processor described in the embodiment of the present invention refers to that sequence performs synchronizing for (in order)
Thread processor.With reference to Fig. 2, sequence synchronization multiline procedure processor can include decoder 20 and execution unit 21.The decoding
Device 20 includes decoding unit 201 and decoding unit 202.Each decoding unit for a thread instruction into row decoding.For example,
Decoding unit 201 for T0 threads instruction into row decoding, decoding unit 202 for T1 threads instruction into row decoding.
Decoding unit in the decoder 20 come from the fetching of Fetch unit (not shown) into the instruction of row decoding
(fetch) and transmission, the instruction translated can be WFE instruction, WFI instructions or other instructions.In the present embodiment, it will decode
The decoding unit for going out WFE instruction or WFI instructions is known as subject thread decoding unit.If for example, as shown in Fig. 2, decoding unit
202 decode out WFE instruction, then decoding unit 202 is known as subject thread decoding unit in embodiments of the present invention.
It should be pointed out that for convenience of explanation, only with 2 decoding units as an example, in fact according to synchronization in Fig. 2
Other different designs of multiline procedure processor, decoder can also include greater number of decoding unit.
The decoding unit 201 or decoding unit 202 that the execution unit 21 is adapted for carrying out in decoder 20 are decoded and are sent
(dispatch) instruction, such as performed in a manner of flowing water (pipeline).Still further, the execution unit
21 flowing water perform process can include launching phase (issue stage), first perform the stage (execute stage 1),
Second performs stage (execute stage 2) and write back stage (write back stage).The execution unit 21 can be with
Including multiple execution flowing water units, above-mentioned each flowing water stage can be completed by performing flowing water unit accordingly.It is described to perform list
Execution flowing water unit (execution pipes) in member 21 can be shared by multiple threads.
It should be noted that the execution unit 21 may be designed in other appropriate pipeline modes, it is described to perform list
The specific different designs of the pipeline mode of member 21 do not form the limitation to this programme.
Please continue to refer to Fig. 2, if decoding unit 201 is directed to the instruction of thread T0 into row decoding, decoding unit 202 is directed to
The instruction of thread T1 is into row decoding, then when identifying that the decoding of the decoding unit 202 in decoder 20 obtains WFE instruction or WFI
During instruction, control targe unit (i.e. decoding unit 202) stops sending the instruction of T1 threads to execution unit 21, and described in control
Other decoding units (i.e. decoding unit 201) in decoder 20 continue to decode and send the instruction of its corresponding thread T0.
In the prior art, when the decoding of decoder 20 obtains WFE instruction or WFI is instructed, WFE instruction or WFI instructions reach
The write back stage of flowing water and waiting are performed, and all decoding units in decoder 20 all stop referring to the transmission of execution unit 21
It enables, until the corresponding event of WFE instruction arrives or the corresponding interruption of WFI instructions arrives and just restores to refer to the transmission of execution unit 21
It enables, so as to cause the free time of the hardware resource of execution unit 21 and waste.
The prior art is compared, since the decoding unit 201 continues to decode and sends the instruction extremely execution of T0 threads
Unit 21, so all flowing water units in execution unit 21 will all be filled up by the instruction of T0 threads.In other words, execution unit 21
In all flowing water units do not block because subject thread decoding unit is translated when WFE instruction or WFI are instructed.Therefore, execution unit
21 hardware resource is fully used, so that the hardware resource utilization of processor is promoted.
In specific implementation, when the subject thread decoding unit is controlled to stop sending the instruction of corresponding thread, together
Stop the instruction to the thread and carry out fetching.To should refer to upper example, it can control and stopping Fetch unit together for T1 threads
Instruction carries out fetching.
In specific implementation, the WFE instruction or WFI instructions reach write back stage and are not take up in assembly line when waiting for
Perform flowing water unit.
Step S102：When identifying the corresponding event of the WFE instruction or identify that the WFI instructs corresponding interruption
When, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.
With reference to Fig. 2, when identifying that the corresponding event of the WFE instruction (Event) arrives or identify the WFI instructions
When corresponding interruption (Interrupt) is arrived, the subject thread decoding unit (decoding unit 202) is controlled to restore to send T1 lines
The instruction of journey.
It should be noted that the WFE instruction or WFI that are identified in step S101 are instructed with being identified in step S102
Event and interruption have correspondence.Furthermore, if step S101 identify WFE instruction carry out respective handling after, step
Rapid S102, which needs to correspond to, identifies that the corresponding event of the WFE instruction just controls the subject thread decoding unit to restore transmission and corresponds to
The instruction of thread.Similarly, if after step S101 identifies that WFI instructions carry out respective handling, step S102 needs corresponding to know
Do not go out the WFI and instruct corresponding interruption, the subject thread decoding unit is just controlled to restore to send the instruction of corresponding thread.
In specific implementation, it before the subject thread decoding unit restores to send the instruction of corresponding thread, can control
System rinses the number in (flush) described subject thread decoding unit and the corresponding Fetch unit of the subject thread decoding unit
According to.With reference to Fig. 2, before the instruction for sending T1 threads is replied in decoding unit 202, control rinse decoding unit 202 and to this
Decoding unit 202 sends the data in the Fetch unit of instruction.
Fig. 3 is a kind of structure of the instruction execution controller of sequence synchronization multiline procedure processor in the embodiment of the present invention
Schematic diagram.It is single that the instruction execution controller 30 of sequence synchronization multiline procedure processor as shown in Figure 3 can include the first control
Member 301 and recovery unit 302.
Wherein, the first control unit 301 is suitable for when identifying the WFE instruction or WFI instructions that decoding obtains, control targe
Thread decoding unit stops sending the instruction of corresponding thread, and control other decoding units in the decoder continue decoding and
Send the instruction of respectively corresponding thread, wherein, the subject thread decoding unit be decoded out in the decoder WFE instruction or
The corresponding decoding unit of thread of WFI instructions；
Recovery unit 302, which is suitable for working as, to be identified the corresponding event of the WFE instruction or identifies that the WFI instructions correspond to
Interruption when, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.
In specific implementation, the instruction execution controller 30 of the sequence synchronization multiline procedure processor can also include the
Two control units 303.
Wherein, the second control unit 303 is suitable for the subject thread decoding unit is being controlled to stop sending corresponding thread
During instruction, stop the instruction to the thread together and carry out fetching.
In specific implementation, the instruction execution controller 30 of the sequence synchronization multiline procedure processor, can also include
Rinsing unit 304.
Rinsing unit 304 is suitable for before the subject thread decoding unit restores to send the instruction of corresponding thread, control
Rinse the data in the subject thread decoding unit and the corresponding Fetch unit of the subject thread decoding unit.
In specific implementation, the WFE instruction or WFI instructions reach write back stage and are not take up in assembly line when waiting for
Execution unit.
In specific implementation, the quantity of the thread can be 2.
In specific implementation, the instruction execution controller 30 of the sequence synchronization multiline procedure processor can be taken suitably
Circuit realize above-mentioned control logic.
In the prior art, when decoding, which obtains WFE instruction or WFI, to be instructed, all decoding units all stop to performing list
Member sends instruction, decodes and sends however, the execution unit in the technical program still can continue to execute other decoding units
Instruction, so as to improve the resource utilization of processor.
The embodiment of the present invention also provides a kind of sequence synchronization multiline procedure processor, and the sequence synchronization multiline procedure processor can
Control is performed with the instruction for including multiple Fetch units, decoder, execution unit and said sequence synchronous multiline procedure processor
Device 30.Wherein, the decoder includes multiple decoding units, and the instruction that each decoding unit is used to correspond to thread is translated
Code.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
It is completed with instructing relevant hardware by program, which can be stored in computer readable storage medium, and storage is situated between
Matter can include：ROM, RAM, disk or CD etc..
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of instruction execution control method of sequence synchronization multiline procedure processor, the sequence synchronization multiline procedure processor include
Decoder, the decoder include multiple decoding units, and each decoding unit is used to correspond to the Instruction decoding of thread, and feature exists
In, including：
When identifying the WFE instruction or WFI instructions that decoding obtains, control targe thread decoding unit stops sending corresponding thread
Instruction, and other decoding units in the decoder is controlled to continue to decode and send the instruction of respectively corresponding thread, wherein,
The subject thread decoding unit is the corresponding decoding unit of thread that WFE instruction or WFI instructions are decoded out in the decoder；
When identifying the corresponding event of the WFE instruction or identifying that the WFI instructs corresponding interruption, the mesh is controlled
Graticule journey decoding unit restores to send the instruction of corresponding thread.
2. the instruction execution control method of sequence synchronization multiline procedure processor according to claim 1, which is characterized in that also
Including：
When the subject thread decoding unit is controlled to stop sending the instruction of corresponding thread, stop the instruction to the thread together
Carry out fetching.
3. the instruction execution control method of sequence synchronization multiline procedure processor according to claim 1, which is characterized in that also
Including：
Before restoring to send the instruction of corresponding thread in the subject thread decoding unit, the subject thread decoding is rinsed in control
Data in unit and the corresponding Fetch unit of the subject thread decoding unit.
4. the instruction execution control method of sequence synchronization multiline procedure processor according to claim 1, which is characterized in that institute
The execution flowing water unit stated WFE instruction or WFI instructions arrival write back stage and be not take up when waiting in assembly line.
5. the instruction execution control method of sequence synchronization multiline procedure processor according to claim 1, which is characterized in that institute
The quantity for stating thread is 2.
6. a kind of instruction execution controller of sequence synchronization multiline procedure processor, the sequence synchronization multiline procedure processor include
Decoder, the decoder include multiple decoding units, and each decoding unit is used to correspond to the Instruction decoding of thread, and feature exists
In, including：
First control unit, suitable for when identifying the WFE instruction or WFI instructions that decoding obtains, the decoding of control targe thread is single
Member stops sending the instruction of corresponding thread, and control other decoding units in the decoder continue to decode and sends it is respective right
The instruction of thread is answered, wherein, the subject thread decoding unit is that WFE instruction or WFI instructions are decoded out in the decoder
The corresponding decoding unit of thread；Recovery unit, suitable for that ought identify the corresponding event of the WFE instruction or identify the WFI
When instructing corresponding interruption, the subject thread decoding unit is controlled to restore to send the instruction of corresponding thread.
7. the instruction execution controller of sequence synchronization multiline procedure processor according to claim 6, which is characterized in that also
Including：
Second control unit, suitable for when the subject thread decoding unit is controlled to stop sending the instruction of corresponding thread, together
Stop the instruction to the thread and carry out fetching.
8. the instruction execution controller of sequence synchronization multiline procedure processor according to claim 6, which is characterized in that also
Including：
Rinsing unit, suitable for before restoring to send the instruction of corresponding thread in the subject thread decoding unit, institute is rinsed in control
State the data in subject thread decoding unit and the corresponding Fetch unit of the subject thread decoding unit.
9. the instruction execution controller of sequence synchronization multiline procedure processor according to claim 6, which is characterized in that institute
The execution flowing water unit stated WFE instruction or WFI instructions arrival write back stage and be not take up when waiting in assembly line.
10. the instruction execution controller of sequence synchronization multiline procedure processor according to claim 6, which is characterized in that
The quantity of the thread is 2.
11. a kind of sequence synchronization multiline procedure processor, which is characterized in that including：Fetch unit, decoder, execution unit and
Such as the instruction execution controller of claim 6-10 any one of them sequence synchronization multiline procedure processors, wherein, it is described to translate
Code device includes multiple decoding units, and each decoding unit is used to correspond to the Instruction decoding of thread.
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| CN201611245642.3A CN108255516A (en) | 2016-12-29 | 2016-12-29 | Sequence synchronization multiline procedure processor and its instruction execution control method, device |
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