CN108242973B - Data error correction method and device - Google Patents

Abstract

Embodiments of the present invention provide a data error correction method and device, which are applied to a device including a sending module and a receiving module. The method includes: performing mesh logic coding on the N-bit data to be transmitted for the sending module of the device, Obtain coded data; send the coded data to the receiving module of the device; for the receiving module of the device, split the received coded data according to the combination rule to obtain each of the N bits of data Bit data and the check digit data corresponding to the at least two bits of data in each group; according to the N-bit data and the check digit data corresponding to the at least two bits of data in each group, use logical operations to determine the number of bits in the encoded data. Error-occurring data; when the error-occurring data includes at least one bit of the transmitted N-bit data, perform error correction on at least one bit of the N-bit data. By using the embodiments of the present invention, the reliability of the device is improved.

Description

A data error correction method and device

technical field

The present invention relates to the field of communication technologies, and in particular, to a data error correction method and device.

Background technique

In the development process of the entire aerospace and nuclear power fields, FPGA (Field Programmable Gate Array) based on SRAM (Static Random Access Memory) has high functional integration, rich resources and flexible design. advantages, but there are also certain risks. For example, in the aerospace field, in the harsh radiation environment of outer space, it is easily affected by high-level charged particles, and will be exposed to various kinds of radiation from the complex space environment, resulting in the occurrence of single-particle flipping, multi-particle flipping and other phenomena. A functional error of communication data occurs in the FPGA device, so corresponding communication data reinforcement needs to be carried out for the above phenomenon. Among them, the single event flip mainly refers to the 0/1 flip of one bit in the communication data, and the multi-event flip mainly refers to the 0/1 flip of two or more bits in the communication data. Among them, three occur in the aerospace field. The probability of bit and above data flipping errors is very low.

At present, in FPGAs of aerospace or nuclear power plants, the commonly used redundancy technologies for data reinforcement are TMR (Triple Modular Redundancy), partial TMR, Duplication With Compare (DWC, Duplication WithCompare), and reduced redundancy precision (RPR, reduced precision redundancy) and so on. Among them, the TMR technology directly copies the input original data in two copies, combines the two copies of the copied data with the original data to obtain encoded data, and selects three copies of the encoded data through a majority voter at the output port, such as the original data. is 000, the encoded data is 000000000, a single-bit flip occurs during the transmission process, the encoded data becomes 000000100, and the majority voter at the output port will output 000 in the encoded data as the decoded data. However, when a multi-bit error occurs during transmission, for example, the encoded data error becomes 010010000, and the wrong decoded data 010 will be output at the output port. It can be seen that TMR cannot solve data flipping errors of two bits and above. It can only perform data reinforcement for single-event flipping on FPGA, but cannot handle multi-particle flipping errors, resulting in low reliability of FPGA devices.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present invention is to provide a data error correction method and device, so as to achieve the purpose of improving device reliability.

In order to achieve the above object, an embodiment of the present invention provides a data error correction method, which is applied to a device including a sending module and a receiving module, and the method includes:

For the device's transmit module, do the following:

Perform mesh logic coding on the N-bit data to be transmitted to obtain coded data;

Wherein, the step of performing mesh logic coding includes: for M-bit data in the N-bit data to be transmitted, performing logical operations on each group of at least two bits of data in the M-bit data, respectively, to obtain a Set the check digit data corresponding to at least two bits of data; according to the preset combination rule, combine the N-bit data and the check digit data to obtain encoded data, wherein M is less than or equal to N, and N is not less than 4, The logical operation is an exclusive-OR operation, an exclusive-OR operation, an AND operation, an OR operation, a NOT operation, a NAND operation, a NOR operation, or an AND-NOR operation;

sending the encoded data to a receiving module of the device;

For the receiving module of the device, do the following:

Splitting the received encoded data according to the combination rule to obtain check digit data corresponding to each bit of the N-bit data and the at least two bits of data in each group;

According to the N-bit data and the parity bit data corresponding to the at least two bits of data in each group, use a logical operation to determine the erroneous data in the encoded data;

When the erroneous data includes at least one bit of the transmitted N-bit data, error correction is performed on at least one bit of the N-bit data.

Preferably, according to the N-bit data and the parity bit data corresponding to each group of at least two bits of data, using a logical operation to determine the erroneous data in the encoded data, including:

For each group of at least two bits of data in the N-bit data and its corresponding check digit data, perform logical operations to obtain the result of the operation; according to the result of the operation, the logical operation number K of the specified value, and the result of the operation is the specified value The number of common data bits included in the K logic operations of the value, to determine the data in which the error occurs in the encoded data, wherein the common data bits are included in at least two logic operations in the K logic operations For the same data bits, K is less than or equal to the number of logical operations corresponding to all operation results.

Preferably, performing error correction on at least one bit of the N-bit data includes:

When the determined erroneous data includes one bit of erroneous data in the N-bit data, the determined one-bit data is inverted.

Preferably, performing error correction on at least one bit of the N-bit data includes:

When the determined error data includes at least two bits of error data in the N-bit data, at least two bits of the determined N-bit data are respectively inverted.

Preferably, the device including the sending module and the receiving module is a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

In order to achieve the above purpose, an embodiment of the present invention provides a data error correction device, the device includes:

The mesh logic coding unit is used for the sending module of the device to perform mesh logic coding on the N-bit data to be transmitted to obtain encoded data; wherein, the process of performing mesh logic coding includes: for the N bits of data to be transmitted For the M-bit data in the bit data, logical operations are respectively performed on each group of at least two bits of data in the M-bit data to obtain the check digit data corresponding to each group of at least two bits of data; according to the preset combination rule, the The N-bit data is combined with the check bit data to obtain encoded data, wherein M is less than or equal to N, and N is not less than 4, and the logical operation is an exclusive-OR operation, an exclusive-OR operation, an AND operation, an OR operation, NOT, AND NOT, OR NOT, OR AND OR NOT;

a sending unit for sending the encoded data to a receiving module of the device;

The splitting unit is used for the receiving module of the device, and splits the received encoded data according to the combination rule, and obtains the data corresponding to each bit of the N-bit data and the at least two bits of each group of data. check digit data;

an arithmetic unit, configured to determine, according to the N-bit data and the parity bit data corresponding to each group of at least two bits of data, the data in which the error occurs in the encoded data by using a logical operation;

An error correction unit, configured to perform error correction on at least one bit of the N-bit data when the data in which the error occurs includes at least one bit of the transmitted N-bit data.

Preferably, the computing unit specifically includes:

a logical operation subunit for performing logical operations on each group of at least two bits of data in the N-bit data and its corresponding parity bit data to obtain an operation result;

The error bit search subunit is used to determine that an error occurs in the encoded data according to the number K of logical operations whose operation result is a specified value, and the number of common data bits included in the K logical operations whose operation result is a specified value , wherein the common data bits are the same data bits included in at least two of the K logical operations, and K is less than or equal to the number of logical operations corresponding to all the operation results.

Preferably, the error correction unit specifically includes:

The first inversion subunit is configured to invert the determined one-bit data when the determined erroneous data includes one-bit data in the N-bit data.

Preferably, the error correction unit further specifically includes:

The second inversion subunit is configured to respectively invert at least two bits of the determined N-bit data when the determined erroneous data includes at least two bits of the N-bit data.

Preferably, the device is: a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

The data error correction method and device provided by the embodiments of the present invention can use mesh logic coding to encode N-bit data to be transmitted to obtain encoded data, and the receiving module can obtain encoded data according to the parity bit data in the transmitted encoded data and the N-bit data. Bit data, using logical operations to perform error detection and error correction on N-bit data. Not only for single-particle flipping, but also for multi-particle flipping, the purpose of error detection and correction can be achieved, so as to better reinforce the communication data in the device and improve the stability and reliability of the device. Further, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM, or ram-based to perform data error detection and error correction inside the device. Of course, it is not necessary for any product or method to implement the present invention to simultaneously achieve all of the advantages described above.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

1 is a schematic flowchart of a data error correction method provided by an embodiment of the present invention;

2 is a schematic diagram of the relationship between 5-bit data to be transmitted and parity bit data provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a data error correction apparatus provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

A data error correction method provided by an embodiment of the present invention is first described in detail below.

It should be noted that the embodiments of the present invention are preferably applicable to a device including a sending module and a receiving module. Specifically, in practical applications, the device can be: a field programmable logic gate array device or a FIFO (First InputFirst Output, first-in first-out), DDR (Double Data Rate, double-rate synchronous dynamic random access memory), DRAM ( Dynamic Random Access Memory) or ram-based devices, such as FPGA devices in aerospace systems or nuclear power plants, etc.

Referring to FIG. 1, FIG. 1 is a schematic flowchart of a data error correction method provided by an embodiment of the present invention, which may include the following steps:

For the device's transmit module, do the following:

S101, performing mesh logic coding on the N-bit data to be transmitted to obtain coded data;

Specifically, the step of performing mesh logic coding includes: for M-bit data in the N-bit data to be transmitted, performing logical operations on each group of at least two bits of data in the M-bit data, respectively, to obtain the Check digit data corresponding to at least two bits of data in each group; according to preset combination rules, combine the N-bit data with the check digit data to obtain encoded data, where M is less than or equal to N, and N is not less than 4 , the logical operation is an exclusive-OR operation, an exclusive-OR operation, an AND operation, an OR operation, a NOT operation, a NAND operation, a NOR operation, or an AND-NOR operation;

Exemplarily, a data error correction method provided by an embodiment of the present invention will be described in detail below by taking the logical operation being an exclusive OR operation as an example.

Exemplarily, the preset combination rule may be: the original data bits are in the low bits, and the check bits are in the high bits. When N is equal to 5 and M is equal to 5, for the 5-bit original data to be transmitted b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , perform an exclusive OR operation on each group of 2-bit data in the original data, respectively, The XOR operation process can be shown in Table 1.

Table 1

It can be seen from Table 1 that after the XOR operation, the check bits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq ₁₅ , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq corresponding to each group of 2-bit data can be obtained ₃₅ and eq ₄₅ , wherein the relationship between the 5-bit original data and the obtained check digit is shown in Figure 2; The original data is combined with the check digit to obtain the encoded data eq ₁₂ eq ₁₃ eq ₁₄ eq ₁₅ eq ₂₃ eq ₂₄ eq ₂₅ eq ₃₄ eq ₃₅ eq ₄₅ b ₁ b ₂ b ₃ b ₄ b ₅ (eg 000000000011111).

b₁、b₂、b₃、b₄间进行异或运算得到校验位

b₁、b₂、b₃、b₄、b₅间进行异或运算得到校验位

从而得到了更多的校验位数据。Exemplarily, in practical applications, when M is less than 5, mesh logic coding may also be performed for some data bits of the 5-bit original data (eg, 4-bit data bits b ₁ , b ₂ , b ₃ , b ₄ ). , so that the design complexity of the mesh logic coding can be reduced. Among them, in the encoding process, not only the XOR operation can be performed between two data bits, but also the XOR operation can be performed between 3 bits, 4 bits or 5 bits, such as the XOR operation between b ₁ , b ₂ , and b ₃ Operation to get the check digit

Perform an exclusive OR operation among b ₁ , b ₂ , b ₃ , and b ₄ to obtain the check digit

Perform an exclusive OR operation among b ₁ , b ₂ , b ₃ , b ₄ , and b ₅ to obtain the check digit

Thus, more check digit data is obtained.

S102, sending the encoded data to a receiving module of the device;

For sending the encoded data to the receiving module, one possible situation is to perform real data transmission, and another possible situation is to simulate the data transmission environment and perform real data transmission.

In the data transmission of the aerospace system, FIFO, DDR, DRAM or other storage devices are generally selected to store the encoded data, and then the stored encoded data is sent to the receiving module of the device. In this embodiment, to simulate the data transmission environment and actually perform data transmission, a FIFO can be selected as a storage device, one end of which is connected to the coded data output of the sending module, and the other end is connected to the data input of the receiving module.

For the receiving module of the device, do the following:

S103, splitting the received encoded data according to the combination rule to obtain check digit data corresponding to each bit of the N-bit data and the at least two bits of each group of data;

Specifically, in practical applications, the bit widths at both ends can be assumed to be the same during data transmission (ie, bit width = data bit width + parity bit width). Yes, for example, for the 5-bit original data bit 11111 and the 10-bit check bit 0000000000, according to the aforementioned combination rule that the original data bit is in the low bit and the check bit is in the high bit, for the combined encoded data 000000000011111, the bit width can be 15 bits. The receiving module only needs to use the low 5 bits 11111 of the received encoded data as the data bits and the high 10 bits 0000000000 as the check bits. Among them, when the number of bits of the encoded data is large, the number of data bits for each transmission can be agreed before the sending module and the receiving module transmit data. Just do the merge operation. For example, the number of coded data is 50 bits, the fixed frame length can be set to 10 bits, and it is sent 5 times. The receiving module performs the merging operation when it receives 5 times, and then obtains the data bits and the corresponding data from the combined complete coded data. check digit data.

S104, according to the N-bit data and the corresponding check digit data of each group of at least two bits of data, use logical operation to determine the data that has an error in the encoded data;

Specifically, a logical operation can be performed on each group of at least two bits of data in the N-bit data and the corresponding check digit data to obtain an operation result; the number K of logical operations with a specified value according to the operation result, and The operation result is the number of common data bits included in the K logical operations of the specified value, and the data in which the error occurs in the encoded data is determined, wherein the common data bits are at least two logical operations in the K logical operations. For the same data bits included in the operation, K is less than or equal to the number of logical operations corresponding to all operation results. Among them, the logic operation can also be called an error detection check formula. When the logical operation is an XOR operation, the specified value can be 1, which means that an error occurs in the XOR operation due to data errors.

Exemplarily, the number of required XOR operations may be determined according to the number of data bits in which errors actually occur in the application scenario of the embodiment of the present invention.

Still referring to the embodiment shown in FIG. 2 , in conjunction with the exclusive OR operation in Table 1, for each group of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b ₄ , b ₁ b ₅ , b ₂ of the 5-bit original data b ₃ , b ₂ b ₄ , b ₂ b ₅ , b ₃ b ₄ , b ₃ b ₅ , b ₄ b ₅ and their corresponding check digits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq ₁₅ , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ , XOR operation, the following results will be obtained:

The error detection basis for the embodiment shown in FIG. 2 is that the operation results of the 10 error detection check formulas are all 0 when no error occurs, that is, the operation result is 1 only when a data error occurs. In the aerospace system, when a data error occurs, 99.9999% of the errors that occur are 1-bit data errors or 2-bit data errors. In this case, only 1-bit or 2-bit data errors can be considered for mesh logic coding, and the decision The number of subsequent error detection check formulas required.

Assume for each set of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b ₄ , b ₁ b ₅ , b ₂ b ₃ , b ₂ b ₄ , b ₂ b ₅ , b ₃ b for each set of 5-bit raw data ₄ , b ₃ b ₅ , b ₄ b ₅ and their corresponding check bits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq ₁₅ , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ , XOR The operation results are as follows:

According to the above error checking basis, the 6 XOR operations whose operation result is 1 represent 6 error detection check formulas, and the 6 error detection check formulas include 3 common data bits b ₁ , b ₂ 3 , 2 b ₃ , 2 b ₄ , and 2 b ₅ . Since b ₁ and b ₂ appear the most times, the data bits that have errors are determined to be b ₁ and b ₂ .

The above embodiment does not consider the situation that 3 or more bits of data have errors, and the number of error detection check formulas can be increased when necessary to meet the error detection and error correction requirements of specific application scenarios. In practical applications, when 3-bit and more bit flips need to be considered, when performing mesh logic coding, on the basis of XOR operation between 2-bit original data, 3-bit original data, 4-bit original data can be performed. The XOR operation between the original data or the 5-bit original data can obtain more check digits. For example, for the above 5-bit original data, after obtaining 10 check digits of each group of 2 data, continue between the 3-bit data. Perform XOR operation to obtain eq ₁₂₃ , eq ₁₂₄ , eq ₁₂₅ , eq ₁₃₄ , eq ₁₃₅ , eq ₁₄₅ , eq ₂₃₄ , eq ₂₃₅ , eq ₂₄₅ , eq ₃₄₅ , and perform XOR operation between 5-bit data to obtain eq ₁₂₃₄₅ , and then in In the process of determining the erroneous data that has flipped, the number of error detection check formulas that can be obtained is 10+10+1=21, and the number K of the operation results of these error detection check formulas is 1, and K error detection formulas are used. The number of common data bits included in the check formula is used to determine which original data bits or check bits are in error. When the operation result is the specified value of 1, it means that the error detection check formula has an error, and this When K is not greater than 21.

S105: Perform error correction on at least one bit of the N-bit data.

Specifically, when the data in which the error occurs includes at least one bit of the transmitted N-bit data, error correction is performed on at least one bit of the N-bit data. In practical applications, when the erroneous data is the check digit data, since the error of the check digit data will not affect the transmitted original N-bit data, there is no need to correct the error of the check digit data.

Specifically, when the determined erroneous data includes one bit of erroneous data in the N-bit data, the determined one-bit data is inverted.

Specifically, when the determined error data includes at least two bits of error data in the N-bit data, at least two bits of the determined N-bit data are respectively inverted.

在a₁、a₂、a₃、a₄、a₅、a₆、a₇、a₈、a₉、a₁₀中，当其中1个运算结果为1时，便可定位到1位校验位数据错误，如仅a₁为1，说明eq₁₂发生错误，此时不需要纠错；当其中4个运算结果为1时，便可定位到1位原始数据错误，如a₁、a₂、a₃、a₄为1，其他为0，说明该4个错误检错校验式包含的同一数据位b₁发生错误，对b₁取反纠错；当其中2个运算结果为1时，便可定位到2位校验位数据错误，如a₁、a₂为1，其他为0，说明原始数据位没有发生错误，故而检验位eq₁₂、eq₁₃发生错误，此时不需要纠错；当其中3个运算结果为1时，便可定位到1位原始数据和与该原始数据相关的1位检验位数据发生错误，如a₁、a₂、a₃为1，其他为0，根据该3个错误检错校验式包含的同一数据位b₁，定位出b₁发生错误，又因为与b₁相关的检错校验式的运算结果a₄为0，定位出校验位eq₁₅发生错误，此时只需要对b₁取反纠错；当其中5个运算结果为1时，便可定位到1位原始数据和与该位原始数据不相关的1位检验位数据发生错误，如a₁、a₂、a₃、a₄、a₅为1，其他为0，根据其中4个错误检错校验式包含的同一数据位b₁，定位出b₁发生错误，又因为a₅发生错误而b₂或b₃不可能发生错误，说明eq₂₃发生错误，此时只需要对b₁取反纠错；当其中6个运算结果为1时，便可定位到2位原始数据发生错误，如a₂、a₃、a₄、a₅、a₆、a₇为1，其他为0，其中3个检错校验式包含公共数据位b₁3个、b₂3个、b₃2个、b₄2个、b₅2个，说明2位数据b₁、b₂发生错误，分别对b₁、b₂取反纠错即可。另外，在实际应用中，在根据实际需要，要求对3位及更多位数据进行检错和纠错时，可以如前面的步骤中所述，增加更多的检错校验式，具体以实现检测出多位数据错误并进行纠错为准。Exemplarily, for each group of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b ₄ , b ₁ b ₅ , b ₂ b ₃ , b ₂ b ₄ , b for each set of 5-bit raw data as described above ₂ b ₅ , b ₃ b ₄ , b ₃ b ₅ , b ₄ b ₅ and their corresponding check digits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq ₁₅ , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ , perform XOR operation to obtain the operation result, among which,

In a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , a ₇ , a ₈ , a ₉ , a ₁₀ , when one of the operation results is 1, the 1-bit check can be located Bit data error, if only a ₁ is 1, it means that an error occurs in eq ₁₂ , and no error correction is required at this time; when 4 of the operation results are 1, 1-bit original data error can be located, such as a ₁ , a ₂ , a ₃ , a ₄ are 1, and the others are 0, indicating that the same data bit b ₁ contained in the four error detection check formulas has an error, and b ₁ is inverted for error correction; when two of the operation results are 1 , the 2-bit check bit data error can be located. For example, a ₁ and a ₂ are 1, and the others are 0, indicating that the original data bits are not wrong, so the check bits eq ₁₂ and eq ₁₃ have errors, and no correction is required at this time. Wrong; when 3 of the operation results are 1, it is possible to locate the 1-bit original data and the 1-bit check bit data related to the original data. Errors occur, such as a ₁ , a ₂ , a ₃ are 1, others are 0 , according to the same data bit b ₁ contained in the three error detection and check formulas, locate an error in b ₁ , and because the operation result a ₄ of the error detection and check formula related to b ₁ is 0, locate the check When an error occurs in bit eq ₁₅ , it is only necessary to invert b ₁ for error correction; when 5 of the operation results are 1, 1-bit original data and 1-bit check bit data unrelated to the original data can be located. An error occurs, such as a ₁ , a ₂ , a ₃ , a ₄ , and a ₅ are 1, and the others are 0. According to the same data bit b ₁ contained in the four error detection check formulas, locate the error in b ₁ , And because a ₅ has an error, b ₂ or b ₃ cannot have an error, indicating that an error has occurred in eq _23. At this time, only b ₁ needs to be inverted for error correction; when 6 of the operation results are 1, 2 can be located. Bit original data error, such as a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , a ₇ are 1, others are 0, and the 3 error detection check formulas include common data bits b ₁ 3, b ₂ 3, 2 b ₃ , 2 b ₄ , and ₂ b ₅ , indicating that an error occurs in the ₂ -bit data b ₁ and b ₂ . In addition, in practical applications, when it is required to perform error detection and error correction on 3-bit or more bits of data according to actual needs, more error detection and check formulas can be added as described in the previous steps. The realization of multi-bit data error detection and error correction shall prevail.

The method shown in Figure 1 can be applied to FPGA devices, and can also be applied to devices containing FIFO, DDR, DRAM or ram-based.

It can be seen that the N-bit data to be transmitted is encoded by using mesh logic coding to obtain encoded data, and the receiving module can use logical operations to perform error detection and summation on the N-bit data according to the parity bit data and N-bit data in the transmitted encoded data. error correction. Not only for single-particle flipping, but also for multi-particle flipping, the purpose of error detection and correction can be achieved, so as to better reinforce the communication data in the device and improve the stability and reliability of the device. Further, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM, or ram-based to perform data error detection and error correction inside the device.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram of a data error correction apparatus according to an embodiment of the present invention. Corresponding to the process shown in FIG. 1 , the error correction apparatus may include: a mesh logic coding unit 301 and a sending unit 302 , a splitting unit 303 , an arithmetic unit 304 , and an error correction unit 305 .

The mesh logic encoding unit 301 is used for the sending module of the device to perform mesh logic encoding on the N-bit data to be transmitted to obtain encoded data; wherein, the process of performing mesh logic encoding includes: for the to-be-transmitted N-bit data For M-bit data in the N-bit data, logical operations are respectively performed on each group of at least two bits of data in the M-bit data to obtain check digit data corresponding to each group of at least two bits of data; according to the preset combination rule, The N-bit data is combined with the check bit data to obtain encoded data, wherein M is less than or equal to N, and N is not less than 4, and the logical operation is an exclusive-OR operation, an exclusive-OR operation, an AND operation, or an OR operation , NOT, AND NOT, OR NOT, OR AND OR NOT;

a sending unit 302, configured to send the encoded data to a receiving module of the device;

The splitting unit 303, used for the receiving module of the device, splits the received encoded data according to the combination rule, and obtains that each bit of the N-bit data corresponds to the at least two bits of data in each group the check digit data;

an arithmetic unit 304, configured to determine the data with errors in the encoded data according to the N-bit data and the parity bit data corresponding to the at least two bits of data in each group, using logical operations;

The error correction unit 305 is configured to perform error correction on at least one bit of the N-bit data when the erroneous data includes at least one bit of the transmitted N-bit data.

Specifically, the operation unit may specifically include: a logic operation subunit, an error bit search subunit (not shown in the figure);

a logical operation subunit for performing logical operations on each group of at least two bits of data in the N-bit data and its corresponding parity bit data to obtain an operation result;

The error bit search subunit is used to determine that an error occurs in the encoded data according to the number K of logical operations whose operation result is a specified value, and the number of common data bits included in the K logical operations whose operation result is a specified value , wherein the common data bits are the same data bits included in at least two of the K logical operations, and K is less than or equal to the number of logical operations corresponding to all the operation results.

Specifically, the error correction unit may specifically include:

The first inversion subunit is configured to invert the determined one-bit data when the determined erroneous data includes one-bit data in the N-bit data.

Specifically, the error correction unit may further include:

The second inversion subunit is configured to respectively invert at least two bits of the determined N-bit data when the determined erroneous data includes at least two bits of the N-bit data.

Specifically, the device may be: a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

It can be seen that the N-bit data to be transmitted is encoded by using mesh logic coding to obtain encoded data, and the receiving module can use logical operations to perform error detection and summation on the N-bit data according to the parity bit data and N-bit data in the transmitted encoded data. error correction. Not only for single-particle flipping, but also for multi-particle flipping, the purpose of error detection and correction can be achieved, so as to better reinforce the communication data in the device and improve the stability and reliability of the device. Further, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM, or ram-based to perform data error detection and error correction inside the device.

It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to the partial descriptions of the method embodiments.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (8)

1. A method for correcting data errors in a device comprising a transmitting module and a receiving module, the method comprising:

for a transmit module of the device, performing the following:

performing mesh logic encoding on N bit data to be transmitted to obtain encoded data;

wherein the step of performing mesh logic encoding comprises: respectively carrying out logic operation on at least two bits of data in each group in the M bit data aiming at the M bit data in the N bit data to be transmitted to obtain check bit data corresponding to the at least two bits of data in each group; combining the N bit data and the check bit data according to a preset combination rule to obtain coded data, wherein M is less than or equal to N, N is not less than 4, and the logical operation is exclusive-or operation, exclusive-nor operation, AND operation, OR operation, NOT operation, or AND NOT operation; the preset combination rule is as follows: the original data bit is at the low position, and the check bit is at the high position;

sending the encoded data to a receiving module of the device;

for a receive module of the device, performing the following:

splitting the received coded data according to the combination rule to obtain check bit data corresponding to each bit of data of the N bits of data and each group of at least two bits of data;

determining data with errors in the coded data by using logical operation according to the N-bit data and check bit data corresponding to each group of at least two-bit data;

when the data with errors contains at least one bit of data in the transmitted N bits of data, correcting the error of the at least one bit of data in the N bits of data;

determining data with errors in the encoded data by using logical operation according to the N-bit data and the check bit data corresponding to each group of at least two bits of data, including:

respectively carrying out logic operation on each group of at least two bit data in the N bit data and the check bit data corresponding to the at least two bit data to obtain an operation result; and determining the data with errors in the coded data according to the number K of logical operations with the operation result being the specified value and the number of common data bits contained in the K logical operations with the operation result being the specified value, wherein the common data bits are the same data bits contained in at least two of the K logical operations, and K is less than or equal to the number of the logical operations corresponding to all the operation results.

2. The method of claim 1, wherein said error correcting at least one of said N bits of data comprises:

when the determined error data includes one bit of error data of the N-bit data, inverting the determined one bit of data.

3. The method of claim 1, wherein said error correcting at least one of said N bits of data comprises:

and when the determined error data comprises at least two bit error data in the N bit data, respectively negating at least two bit data in the determined N bit data.

4. The method of claim 1, wherein the device comprising the sending module and the receiving module is: a field programmable gate array device or a device containing a FIFO, DDR, DRAM or ram-based.

5. A data error correction apparatus, applied to a device including a transmitting module and a receiving module, the apparatus comprising:

the mesh logic coding unit is used for a sending module of the device and carrying out mesh logic coding on the N-bit data to be transmitted to obtain coded data; wherein the process of performing mesh logic encoding comprises: respectively carrying out logic operation on at least two bits of data in each group in the M bit data aiming at the M bit data in the N bit data to be transmitted to obtain check bit data corresponding to the at least two bits of data in each group; combining the N bit data and the check bit data according to a preset combination rule to obtain coded data, wherein M is less than or equal to N, N is not less than 4, and the logical operation is exclusive-or operation, exclusive-nor operation, AND operation, OR operation, NOT operation, or AND NOT operation; the preset combination rule is as follows: the original data bit is at the low position, and the check bit is at the high position;

a transmitting unit for transmitting the encoded data to a receiving module of the device;

the splitting unit is used for a receiving module of the device to split the received coded data according to the combination rule to obtain check bit data corresponding to each bit of data of the N bits of data and each group of at least two bits of data;

the arithmetic unit is used for determining data with errors in the coded data by using logical operation according to the N-bit data and the check bit data corresponding to each group of at least two-bit data;

an error correction unit for correcting error of at least one bit data of the N bit data when the data in which the error occurs contains at least one bit data of the transmitted N bit data;

the operation unit specifically includes:

the logical operation subunit is used for respectively carrying out logical operation on each group of at least two bit data in the N bit data and the check bit data corresponding to the at least two bit data to obtain an operation result;

and the error bit searching subunit is used for determining data with errors in the encoded data according to the number K of logical operations of which the operation result is the specified value and the number of common data bits included in the K logical operations of which the operation result is the specified value, wherein the common data bits are the same data bits included in at least two of the K logical operations, and K is less than or equal to the number of the logical operations corresponding to all the operation results.

6. The apparatus according to claim 5, wherein the error correction unit specifically comprises:

a first negation subunit, configured to negate the determined one bit of data when the determined error data includes one bit of data of the N-bit of data.

7. The apparatus according to claim 6, wherein the error correction unit further comprises:

and the second negation subunit is used for respectively negating the determined at least two bits of data in the N bits of data when the determined error data comprises at least two bits of data in the N bits of data.

8. The apparatus of claim 5, wherein the apparatus is: a field programmable gate array device or a device containing a FIFO, DDR, DRAM or ram-based.

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