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CN108242918A - 动态放大器及芯片 - Google Patents

动态放大器及芯片 Download PDF

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CN108242918A
CN108242918A CN201711339660.2A CN201711339660A CN108242918A CN 108242918 A CN108242918 A CN 108242918A CN 201711339660 A CN201711339660 A CN 201711339660A CN 108242918 A CN108242918 A CN 108242918A
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dynamic amplifier
terminal
bypass
amplification
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CN108242918B (zh
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刘纯成
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MediaTek Inc
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Abstract

本发明实施例公开了一种动态放大器及芯片。其中该动态放大器包括:输入对,接收一对差分输入Vip与Vin,并且提供第一端、第二端以及第三端;负载电路,耦合至共模端,用于提供一对差分输出Vop和Von;驱动器,用于对所述动态放大器的信号放大提供驱动能力;以及旁路电路,可被操作以降低该负载电路的电流;其中:该驱动器在放大阶段耦合至该第一端,该负载电路在该放大阶段耦合至该第二端及该第三端以及该旁路电路在该放大阶段中的旁路期间内耦合至该第二端与该第三端。其中该动态放大器借助于旁路设计,能够提高增益,从而在低电压操作下也能够有宽的信号摆幅。

Description

动态放大器及芯片
技术领域
本发明涉及电子器件领域,尤其涉及一种动态放大器及芯片。
背景技术
在模拟电子产品中,放大器一般用来增加信号功率。为了最小化功率消耗,引入了可动态地操作的动态放大器。在不需要放大时,动态放大器不会消耗静态功率。但是,动态放大器的关键限制包括:当低电压操作时窄的信号摆幅。因此,需要一种具有宽的信号摆幅的动态放大器。
发明内容
有鉴于此,本发明实施例提供了一种动态放大器及芯片,能够提高放大器的增益。
本发明实施例提供了一种动态放大器,包括:输入对,接收一对差分输入Vip与Vin,并且提供第一端、第二端以及第三端;负载电路,耦合至共模端,用于提供一对差分输出Vop和Von;驱动器,用于对所述动态放大器的信号放大提供驱动能力;以及旁路电路,可被操作以降低该负载电路的电流;其中:该驱动器在放大阶段耦合至该第一端;该负载电路在该放大阶段耦合至该第二端及该第三端;以及该旁路电路在该放大阶段中的旁路期间内耦合至该第二端与该第三端。
其中,该负载电路包括:一对负载电容;该对负载电容提供该对差分输出Vop和Von,并且该对负载电容在该共模端处彼此连接;以及在该放大阶段,该对负载电容分别耦合至该第二端与第三端。
其中,该旁路电路包括:一对旁路电流源,可被操作以降低该对负载电容的电流;其中,在该放大阶段中的该旁路期间内,该对旁路电流源分别耦合至该第二端与该第三端。
其中,该对旁路电流源提供可变的旁路电流。
其中,该驱动器为电流源,并且该电流源在该放大阶段耦合至该第一端。
其中,该旁路期间占据该放大阶段的全部或者一部分。
其中,该旁路期间当该放大阶段持续一段时间之后开始。
其中,该输入对为晶体管输入对,并且该晶体管输入对中的晶体管的源极连接至该第一端,该晶体管输入对中的晶体管的漏极分别被视为该第二端与该第三端以及该晶体管输入对中的晶体管的栅极接收该对差分输入Vip与Vin。
其中,当该对差分输出Vop与Von的共模电压达到预定的共模电压差ΔVcm时,该放大阶段结束。
其中,该输入对为晶体管输入对,该驱动器为电流源,该旁路电路包括:一对旁路电流源;该动态放大器提供的增益为:gm·ΔVcm/(I1-I2·Tb/T_A);其中,gm为该晶体管输入对中每个晶体管的跨导,该电流源提供的电流为2I1,该对旁路电流源中每一个提供的电流为I2,T_A为该放大阶段所持续的时长,Tb为该旁路期间所持续的时长。
其中,该对负载电容在重置阶段放电,在该放大阶段中充电,其中该重置阶段在该放大阶段之前。
其中,该共模端为地;该对差分输出Vop与Von在该重置阶段均被下拉至地,以及在该放大阶段升高。
其中,该共模端为电源端;该对差分输出Vop与Von在该重置阶段连接至该电源端,以及在该放大阶段中下降。
其中,该对负载电容在重置阶段预充电,在该放大阶段中放电,其中该重置阶段在该放大阶段之前。
其中,该共模端为地;该对差分输出Vop与Von在该重置阶段均连接至电源端;该对差分输出Vop与Von在该放大阶段下降。
其中,在对差分输出Vop与Von在取样阶段被取样,其中该取样阶段在该放大阶段之后。
本发明实施例提供了一种芯片,包括:前级电路,后级电路;以及动态放大器,其中该动态放大器为权利要求1~16中任一项所述的动态放大器;其中,该前级电路用于将该对差分输入Vip与Vin传送至该动态放大器,该后级电路用于从该动态放大器接收该对差分输出Vop与Von。
其中,进一步包括:第一寄存器,用于设置该旁路电路在该负载电路上引起的电流下降量;和/或第二寄存器,用于设置该旁路期间。
本发明实施例的有益效果是:
本发明实施例的动态放大器,通过旁路电路在放大阶段中对负载电路进行旁路处理,因此能够提高动态放大器的增益,从而使得动态放大器在低电压操作时也能够具有宽的信号摆幅。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例,可以更全面地理解本发明。其中:
图1为根据本发明实施例的动态放大器100的结构示意图;
图2示出了控制信号CS_R,CS_A和CSb的波形以及差分输出Vop与Von的变化;
图3为根据本发明另一实施例的动态放大器300的结构示意图;
图4示出了控制信号CS_R,CS_A和CSb的波形以及动态放大器300的差分输出Vop与Von的变化;
图5为根据本发明另一实施例的动态放大器500的结构示意图;
图6示出了控制信号CS_R/CLK,CS_A和CSb的波形以及动态放大器500的差分输出Vop与Von的变化;以及
图7为根据本发明实施例的包含动态放大器72的芯片700的结构示意图。
具体实施方式
在本申请说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解,硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异作为区分组件的方式,而是以组件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语,故应解释成“包括(含)但不限定于”。另外,“耦接”一词在此为包括任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表该第一装置可直接电气连接至该第二装置,或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述示出了实现本发明的典型实施例。该描述仅是出于说明本发明的一般原理的目的,并且不意味着限制。本发明的范围最好通过参考所附的权利要求书来确定。
图1为根据本发明实施例的动态放大器100的结构示意图。其中该动态放大器100包括:晶体管输入对102(简称输入对102),以及一对负载电容C1和C2。一对差分输入Vin与Vip通过晶体管输入对102耦合至动态放大器100。连接在共模端(此示例中的GND)处的负载电容C1和C2用来将放大的信号呈现在一对差分输出Vop与Von上。
动态放大器100操作于三个阶段中,包括:重置阶段、放大阶段和取样阶段。在重置阶段中,差分输出Vop与Von均重置为预定电平(在此示例中短路至地GND)。动态放大器100使用电流源104来为放大阶段提供电流2I1。电流源104经由输入对102(该输入对102受差分输入Vin和Vip控制)耦合至负载电容C1和C2。输入对102包括:三个(连接)端n1,n2和n3。如所示,形成输入对102的两个晶体管的源极在连接端n1处彼此连接,形成输入对102的两个晶体管的漏极分别被视为连接端n2和n3,形成输入对102的两个晶体管的栅极分别用来接收差分输入Vin和Vip。在放大阶段,连接端n1耦合至电流源104,同时连接端n2耦合至负载电容C1以及连接端n3耦合至负载电容C2。如此,差分输出Vop和Von的电压电平变化。当差分输出Vop和Von的共模电压达到预定的共模电压差(以下表示为ΔVcm)时,放大阶段结束。在放大阶段之后提供取样阶段来对差分输出Vop和Von进行取样。
如所示,特别地提供了一对旁路电流源106和108。旁路电流源106和108可操作地提供旁路电流I2。在放大阶段中的旁路期间内,连接端n2和n3分别耦合至旁路电流源106和108,并且流过负载电容C1/C2的电流为(I1-I2)。为了通过减少电流来得到预定的共模电压差ΔVcm,延长放大阶段以及在差分输出Vop与Von之间形成更大的差。如此,由于旁路设计可以提供更大的增益。动态放大器100甚至在低电压操作中也具有宽的信号摆幅。
在图1中,受控制信号CS_R控制的开关在重置阶段闭合,受控制信号CS_A控制的开关在放大阶段闭合,以及受控制信号CSb控制的开关在放大阶段内的旁路期间闭合。取样阶段设置在控制信号CS_A的使能状态之后。图2示出了控制信号CS_R,CS_A以及CSb的波形以及差分输出Vop与Von的变化。通过在重置阶段T_R使能控制信号CS_R,负载电容C1和C2放电并且差分输出Vop和Von均重置为地电平。在放大阶段T_A,提供充电电流来对负载电容C1和C2进行充电,并且差分输出Vop和Von的电压电平升高。在旁路期间Tb之前,每个负载电容(C1或C2)的充电电流均为I1。在旁路期间Tb内,每个负载电容(C1或C2)的充电电流降低至(I1-I2)。当差分输出Vop和Von的共模电压达到预定的共模电压差ΔVcm时,放大阶段T_A结束。取样阶段T_S设置在放大阶段T_A之后。此处没有示出用于对差分输出Vop和Von进行取样的取样电路,但是任何的信号取样设计均可以用来实现该取样电路。动态放大器100的增益G为gm·ΔVcm/(I1-I2·Tb/T_A),其中gm为输入对102中每个晶体管的跨导。相比于没有旁路设计的提供增益gm·ΔVcm/I1的传统动态放大器,动态放大器100通过简单的旁路设计提供了更高的增益。
在一些典型实施例中,电流源106和108为可变电流源,均提供可变旁路电流I2。在一些典型实施例中,如果设计者接受负载电容C1和C2的慢的充电速度,那么旁路期间Tb覆盖整个放大阶段T_A。当旁路期间Tb覆盖整个放大阶段T_A时,动态放大器100具有增益gm·ΔVcm/(I1-I2),该增益大于传统动态放大器提供的有限的增益gm·ΔVcm/I1
图3为根据本发明另一实施例的动态放大器300的结构。相比于图1的动态放大器100,图3中连接负载电容C1和C2的共模端为电源端VDD。图4示出了控制信号CS_R,CS_A和CSb的波形以及动态放大器300的差分输出Vop和Von的变化。通过使控制信号CS_R在重置阶段T_R使能,差分输出Vop和Von均连接至电源电平(也标记为VDD)。在放大阶段T_A,流过负载电容C1和C2的电流对负载电容C1和C2充电,并且差分输出Vop和Von的电压电平被拉下来。在放大阶段T_A,旁路期间Tb之前流过每个负载电容(C1或C2)的电流为I1。在旁路期间Tb内,流过每个负载电容(C1或C2)的电流均降低至(I1-I2)。当差分输出Vop和Von的共模电压达到预定的共模电压差ΔVcm时,放大阶段结束。取样阶段T_S设置在放大阶段T_A之后。通过旁路设计(参考旁路电流I2)来有效地改善动态放大器300的增益G。
图5为根据本发明另一实施例的动态放大器500的结构。取代放电,连接在共模端GND的负载电容C1和C2在重置阶段被预充电并且在放大阶段放电。图6示出了控制信号CS_R,CS_A和CSb的波形以及动态放大器500的差分输出Vop与Von的变化。通过在重置阶段T_R使控制信号CS_R使能,负载电容C1和C2预充电并且差分输出Vop与Von均连接至电源电平VDD。在放大阶段T_A,提供放电电流以使负载电容C1和C2放电并且差分输出Vop与Von的电压电平下降。在旁路期间Tb之前,每个负载电容(C1或C2)的放电电流均为I1。在旁路期间Tb,每个负载电容(C1或C2)的充电电流均降低至(I1-I2)。当差分输出Vop与Von的共模电压达到预定的共模电压差ΔVcm时,放大阶段T_A结束。取样阶段T_S设置在放大阶段T_A之后。通过旁路设计(参考旁路电流I2)来有效地改善动态放大器500的增益G。
任何在放大阶段对一对负载电容使用旁路设计的动态放大器均考虑在本发明的范围内。
本发明的动态放大器使用开关元件以及连接共模连接端至VDD或GND以移除不需要的静态电流。
负载电路中形成的负载电容对C1和C2可以由其他电路来取代。任何耦合至共模端且能够提供一对差分输出Vop和Von的电路均可以用来替换该对负载电容C1和C2以形成负载电路。
形成驱动器的用于放大的电流源(如104)可以由其他能够对信号放大提供驱动能力的电路来替换。
形成旁路电路的一对旁路电流源106和108可以由其他电路替代。任何能有效地降低负载电路的电流的电路均可以用来替换该对旁路电流源106和108,以形成旁路电路。
图7为根据本发明实施例的包含动态放大器702的芯片700的结构示意图。动态放大器702使用本公开的旁路设计。芯片700进一步包括:前级电路704和后级电路706。前级电路704传送差分输入Vip和Vin至动态放大器702。后级电路706从动态放大器702接收差分输出Vop和Von。
芯片700进一步包括:寄存器R_I2,用于设置由动态放大器702的旁路电流源提供的可变的旁路电流I2。芯片700进一步包括:寄存器R_Tb,用于设置动态放大器702中安排的旁路期间Tb。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。

Claims (18)

1.一种动态放大器,其特征在于,包括:
输入对,接收一对差分输入Vip与Vin,并且提供第一端、第二端以及第三端;
负载电路,耦合至共模端,用于提供一对差分输出Vop和Von;
驱动器,用于对所述动态放大器的信号放大提供驱动能力;以及
旁路电路,可被操作以降低该负载电路的电流;
其中:
该驱动器在放大阶段耦合至该第一端;
该负载电路在该放大阶段耦合至该第二端及该第三端;以及
该旁路电路在该放大阶段中的旁路期间内耦合至该第二端与该第三端。
2.如权利要求1所述的动态放大器,其特征在于,
该负载电路包括:一对负载电容;
该对负载电容提供该对差分输出Vop和Von,并且该对负载电容在该共模端处彼此连接;以及
在该放大阶段,该对负载电容分别耦合至该第二端与该第三端。
3.如权利要求1所述的动态放大器,其特征在于,
该旁路电路包括:一对旁路电流源,可被操作以降低该对负载电容的电流;
其中,在该放大阶段中的该旁路期间内,该对旁路电流源分别耦合至该第二端与该第三端。
4.如权利要求3所述的动态放大器,其特征在于,该对旁路电流源提供可变的旁路电流。
5.如权利要求1所述的动态放大器,其特征在于,该驱动器为电流源,并且该电流源在该放大阶段耦合至该第一端。
6.如权利要求1所述的动态放大器,其特征在于,该旁路期间占据该放大阶段的全部或者一部分。
7.如权利要求1所述的动态放大器,其特征在于,该旁路期间在该放大阶段持续一段时间之后开始。
8.如权利要求1所述的动态放大器,其特征在于,该输入对为晶体管输入对,并且该晶体管输入对中的晶体管的源极连接至该第一端,该晶体管输入对中的晶体管的漏极分别被视为该第二端与该第三端以及该晶体管输入对中的晶体管的栅极接收该对差分输入Vip与Vin。
9.如权利要求1所述的动态放大器,其特征在于,当该对差分输出Vop与Von的共模电压达到预定的共模电压差ΔVcm时,该放大阶段结束。
10.如权利要求9所述的动态放大器,其特征在于,该输入对为晶体管输入对,该驱动器为电流源,该旁路电路包括:一对旁路电流源;
该动态放大器提供的增益为:gm·ΔVcm/(I1-I2·Tb/T_A);
其中,gm为该晶体管输入对中每个晶体管的跨导,该电流源提供的电流为2I1,该对旁路电流源中每一个提供的电流为I2,T_A为该放大阶段所持续的时长,Tb为该旁路期间所持续的时长。
11.如权利要求2所述的动态放大器,其特征在于,该对负载电容在重置阶段放电,在该放大阶段中充电,其中该重置阶段在该放大阶段之前。
12.如权利要求11所述的动态放大器,其特征在于,
该共模端为地;
该对差分输出Vop与Von在该重置阶段均被下拉至地,以及在该放大阶段升高。
13.如权利要求11所述的动态放大器,其特征在于,
该共模端为电源端;
该对差分输出Vop与Von在该重置阶段连接至该电源端,以及在该放大阶段中下降。
14.如权利要求2所述的动态放大器,其特征在于,该对负载电容在重置阶段预充电,在该放大阶段中放电,其中该重置阶段在该放大阶段之前。
15.如权利要求14所述的动态放大器,其特征在于,
该共模端为地;
该对差分输出Vop与Von在该重置阶段均连接至电源端;
该对差分输出Vop与Von在该放大阶段下降。
16.如权利要求1所述的动态放大器,其特征在于,在对差分输出Vop与Von在取样阶段被取样,其中该取样阶段在该放大阶段之后。
17.一种芯片,其特征在于,包括:
前级电路,
后级电路;以及
动态放大器,其中该动态放大器为权利要求1~16中任一项所述的动态放大器;
其中,该前级电路用于将该对差分输入Vip与Vin传送至该动态放大器,该后级电路用于从该动态放大器接收该对差分输出Vop与Von。
18.如权利要求17所述的芯片,其特征在于,进一步包括:
第一寄存器,用于设置该旁路电路在该负载电路上引起的电流下降量;和/或
第二寄存器,用于设置该旁路期间。
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