CN108231860B - Display screen manufacturing method and AMOLED display screen - Google Patents
Display screen manufacturing method and AMOLED display screen Download PDFInfo
- Publication number
- CN108231860B CN108231860B CN201810083885.4A CN201810083885A CN108231860B CN 108231860 B CN108231860 B CN 108231860B CN 201810083885 A CN201810083885 A CN 201810083885A CN 108231860 B CN108231860 B CN 108231860B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal layer
- source
- drain metal
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention discloses a display screen manufacturing method and an AMOLED display screen. The manufacturing method of the display screen comprises the following steps: forming a buffer layer and a polysilicon layer on a substrate; respectively forming a grid metal layer, a storage capacitor metal layer, a first source and drain metal layer, a second source and drain metal layer, a planarization layer, an anode layer and a plurality of interlayer insulating layers; the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer; the second source and drain metal layer is a metal layer covered on the whole surface and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole. The scheme provided by the invention can improve the brightness uniformity of the display screen and improve the display effect of the AMOLED display screen.
Description
Technical Field
The invention relates to the technical field of flat panel display, in particular to a display screen manufacturing method and an AMOLED display screen.
Background
With the development of display technology, OLED (Organic Light Emitting Diode) display screens gradually appear in various display fields. An AMOLED (Active Matrix Organic Light emitting diode) is a new generation of display panel, belongs to a self-luminous type, and has the advantages of fast response speed, no need of a backlight source, higher contrast, Light and thin overall structure, wide viewing angle, low power consumption, flexibility and the like, compared with a general liquid crystal panel, and has a wider application prospect.
In the AMOLED, a TFT (Thin Film Transistor) is generally usedTransistor) to drive the OLED to emit light. However, since the circuit generally has trace impedance, IR _ Drop (voltage Drop) is a problem due to the influence of the trace impedance. The impedance is generally the sum of a resistor and a reactance in a vector, and when an alternating current passes through the impedance, the voltage across the impedance is called the voltage drop of the impedance, that is, the impedance divides a part of the voltage. Therefore, due to the IR _ Drop problem, V of the pixel points at the input near end and the input far end of the display area of the AMOLED display screen may be causedDDThe voltage value difference of (high voltage of power supply) is large due to VDDThe voltage difference will generate different currents in each pixel circuit, resulting in the problem of non-uniform brightness of the OLED, thereby affecting the display effect of the AMOLED display screen.
Disclosure of Invention
In view of this, the present invention provides a display screen manufacturing method and an AMOLED display screen, which can improve the brightness uniformity of the display screen and improve the display effect of the AMOLED display screen.
According to an aspect of the present invention, there is provided a display screen manufacturing method, including:
forming a buffer layer and a polysilicon layer on a substrate;
respectively forming a grid metal layer, a storage capacitor metal layer, a first source and drain metal layer, a second source and drain metal layer, a planarization layer, an anode layer and a plurality of interlayer insulating layers;
the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer;
the second source and drain metal layer is a metal layer covered on the whole surface and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole.
Optionally, the second source drain metal layer is a metal layer without a pattern, and/or,
the second source electrode drain electrode metal layer is made of a titanium-aluminum-titanium-composite structure.
Optionally, the second source drain metal layer is formed on the interlayer insulating layer on the first source drain metal layer;
and forming the interlayer insulating layer on the second source/drain metal layer.
Optionally, the method further includes:
and etching the interlayer insulating layer on the upper layer of the first source/drain metal layer to form at least two through holes, and connecting the second source/drain metal layer with the first source/drain metal layer, the polysilicon layer and the storage capacitor metal layer through the at least two through holes.
Optionally, the forming a gate metal layer, a storage capacitor metal layer, a first source/drain metal layer, a second source/drain metal layer, a planarization layer, an anode layer, and a plurality of interlayer insulating layers respectively includes:
forming a first insulating layer on the polysilicon layer;
forming a gate metal layer on the first insulating layer;
forming a second insulating layer on the gate metal layer;
forming a storage capacitor metal layer on the second insulating layer;
forming a third insulating layer on the storage capacitor metal layer;
forming a first source drain metal layer on the third insulating layer;
forming a fourth insulating layer on the first source/drain metal layer;
forming a second source drain metal layer on the fourth insulating layer;
forming a fifth insulating layer on the second source/drain metal layer;
forming a planarization layer on the fifth insulating layer;
an anode layer is formed on the planarization layer.
Optionally, the method further includes:
etching the third insulating layer to form a first through hole, a second through hole and a third through hole, wherein the first through hole is connected with the polycrystalline silicon layer, the second through hole is connected with the grid metal layer, and the third through hole is connected with the storage capacitor metal layer;
etching the fourth insulating layer to form a fourth through hole and a fifth through hole, wherein the fourth through hole is connected with the first source/drain metal layer corresponding to the first through hole, and the fifth through hole is connected with the first source/drain metal layer corresponding to the third through hole;
and etching the planarization layer to form a sixth through hole and a seventh through hole, wherein the sixth through hole and the seventh through hole enable the first source/drain metal layer to be connected with the anode layer.
According to another aspect of the invention, there is provided an AMOLED display screen:
the buffer layer and the polycrystalline silicon layer are formed on the substrate;
the storage capacitor comprises a storage capacitor metal layer, a grid metal layer, a first source electrode drain electrode metal layer, a second source electrode drain electrode metal layer, a planarization layer, an anode layer and a plurality of interlayer insulating layers;
the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer;
the second source and drain metal layer is a metal layer covered on the whole surface, and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole.
Optionally, the second source drain metal layer is a metal layer without a pattern, and/or,
the second source electrode drain electrode metal layer is a metal layer made of a titanium-aluminum-titanium-composite structure.
Optionally, at least two through holes formed by etching are formed in the interlayer insulating layer on the upper layer of the first source/drain metal layer, and the second source/drain metal layer is connected with the first source/drain metal layer, the polysilicon layer and the storage capacitor metal layer through the at least two through holes.
Optionally, a first insulating layer of the plurality of interlayer insulating layers is located on the polysilicon layer;
the grid metal layer is positioned on the first insulating layer;
a second insulating layer of the plurality of interlayer insulating layers is located on the gate metal layer;
the storage capacitor metal layer is positioned on the second insulating layer;
a third insulating layer of the plurality of interlayer insulating layers is located on the storage capacitor metal layer;
the first source/drain metal layer is positioned on the third insulating layer;
a fourth insulating layer of the plurality of interlayer insulating layers is positioned on the first source drain metal layer;
the second source/drain metal layer is positioned on the fourth insulating layer;
a fifth insulating layer of the plurality of interlayer insulating layers is located on the second source drain metal layer;
the planarization layer is positioned on the fifth insulating layer;
the anode layer is on the planarization layer.
It can be found that in the technical solution of the embodiment of the present invention, after the buffer layer and the polysilicon layer are formed on the substrate, the gate metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer, the planarization layer, the anode layer, and the plurality of interlayer insulating layers are formed respectively; the second source drain metal layer is a metal layer added in the embodiment of the invention, and the second source drain metal layer is a metal layer covered on the whole surface and is connected with the first source drain metal layer, the polysilicon layer and the storage capacitor metal layer through the through hole. Because the whole SD1 metal layer is added, which is equivalent to VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage drop of the trace from the input near end to the far endThe problem of uneven brightness of the display area caused by the IR _ Drop can be effectively solved, and the display effect of the AMOLED display screen is improved.
Further, the second source-drain metal layer according to the embodiment of the present invention may be a metal layer without a pattern, and/or the second source-drain metal layer may be made of TiAlTi (titanium-aluminum-titanium-composite structure).
Further, in the embodiment of the present invention, the second source/drain metal layer is formed on the insulating layer above the first source/drain metal layer; and an insulating layer is formed on the second source/drain metal layer.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in greater detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
FIG. 1 is a schematic flow chart of a display screen manufacturing method according to an embodiment of the present invention;
FIG. 2 is another schematic flow chart diagram of a method of making a display screen according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present invention, according to a 2T1C configuration;
FIG. 4 is a schematic structural diagram of an AMOLED display screen according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The invention provides a display screen manufacturing method which can improve the brightness uniformity of a display screen and improve the display effect of an AMOLED display screen.
The technical solutions of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of a display screen manufacturing method according to an embodiment of the invention.
Referring to fig. 1, the method includes:
in step 101, a buffer layer and a polysilicon layer are formed on a substrate.
In this step, a buffer layer and an amorphous silicon layer may be formed on a substrate, and then the amorphous silicon layer may be converted into a polycrystalline silicon layer.
The substrate may be a glass substrate, a flexible substrate, or the like, and the flexible substrate may be a flexible polymer substrate, or the like.
The step may be to form the amorphous silicon layer into a polycrystalline silicon layer by means of a laser annealing process or the like. The amorphous silicon layer may be formed into a polycrystalline silicon layer in other manners, and the present invention is not limited thereto.
In step 102, a gate metal layer, a storage capacitor metal layer, a first source/drain metal layer, a second source/drain metal layer, a planarization layer, an anode layer, and a plurality of interlayer insulating layers are formed; the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer; the second source and drain metal layer is a metal layer covered on the whole surface and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole.
The first source drain metal layer is also referred to as an SD metal layer, and the second source drain metal layer is also referred to as an SD1 metal layer.
The second source-drain metal layer may be a metal layer containing no pattern, and/or the second source-drain metal layer may be made of TiAlTi (titanium-aluminum-titanium-composite structure).
The second source drain metal layer is formed on the insulating layer on the first source drain metal layer; and an insulating layer is formed on the second source/drain metal layer.
At least two through holes can be formed on the insulating layer on the upper layer of the first source/drain metal layer in an etching mode, and the second source/drain metal layer is connected with the first source/drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the at least two through holes.
It can be found that in the technical solution of the embodiment of the present invention, after the buffer layer and the polysilicon layer are formed on the substrate, the gate metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer, the planarization layer, the anode layer, and the plurality of interlayer insulating layers are formed respectively; the second source drain metal layer is a metal layer added in the embodiment of the invention, and the second source drain metal layer is a metal layer covered on the whole surface and is connected with the first source drain metal layer, the polysilicon layer and the storage capacitor metal layer through the through hole. Because the whole SD1 metal layer is added, which is equivalent to VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop generated by the wiring from the input near end to the far end can effectively solve the problem of uneven brightness of a display area caused by IR _ Drop, and the display effect of the AMOLED display screen is improved.
Fig. 2 is another schematic flow chart of a display screen manufacturing method according to an embodiment of the invention. The method of FIG. 2 describes the method of making a display screen of the present invention in more detail with respect to FIG. 1.
V in the prior art due to pressure dropDDThe voltage difference causes different currents in each pixel circuit of the display panel, which results in uneven brightness of the display panel. The scheme provided by the embodiment of the invention changes VDDThe impedance design of the trace can improve the V from the input near end to the far endDDBrightness unevenness due to voltage differenceIn addition, the service life and the luminous efficiency of the OLED can be improved.
Illustrated is a pixel circuit of the 2T1C configuration of fig. 3. FIG. 3 includes 1 driving TFF (Driving TFT), 1 switching TFT (switching TFT), 1 storage capacitor Cst, and 1 OLED, where VDDIs a power high voltage, Vss is a power low voltage, Data is a Data signal, and Scan is a Scan signal. After the switching TFT is turned on, the data signal reaches the gate of the driving TFT, so that the current of the driving TFT is controlled, and the brightness of the OLED is controlled.
When the driving TFT is operated in the saturation region mode, the operating current I of the driving TFTdComprises the following steps:
where μ is the electron mobility of the channel, CoxW is the channel capacitance per unit area of the drive transistor, W is the channel width of the drive transistor, L is the channel length of the drive transistor, VsgIs the voltage between the source and the gate of the drive transistor, VthTo drive the threshold voltage (also called the turn-on voltage), V, of the transistorDDFor high voltage of the power supply, VgIs the gate voltage of the drive transistor.
From the above formula, it can be found that the pixel driving currents and V of different display areas of the display screenDDThere is a positive correlation in voltage magnitude. Due to the existence of V in the design schemes of the prior artDDThe problem of large impedance of the trace leads to V at the input near end and the input far endDDThe voltage value difference is large, and the OLED brightness and the input current IdIn proportion, the difference in current generated when the difference in voltage is large is also large, so if the V of the whole display area can be madeDDThe voltage is maintained at a relatively uniform level, namely the voltage difference is small, so that the difference of current values generated in each pixel circuit is reduced, and the brightness of the OLED display screen is improvedNon-uniformity problem.
Therefore, the present invention provides a method for manufacturing a display screen with improved display effect by improving IR Drop according to the above analysis, and mainly adds a layer of whole surface V in the design of the back plateDDA routing layer, i.e., a source drain metal layer (SD1 metal layer) is added, and is connected to each pixel through a via. Because the whole SD1 metal layer is added, which is equivalent to VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop generated by the routing from the input near end to the far end, namely the voltage difference is reduced, so that the current value difference in each pixel circuit is reduced, and the problem of uneven light emitting brightness caused by IR _ Drop in the display area can be effectively solved.
The technical solution of the embodiment of the present invention is described in detail below with reference to fig. 2, and the method in fig. 2 includes:
in step 201, a buffer layer and an amorphous silicon layer are formed on a glass substrate, and the amorphous silicon layer is converted into a polycrystalline silicon layer.
The step is exemplified by, but not limited to, using the substrate as a glass substrate, and the buffer layer and the amorphous silicon layer may be formed on other types of substrates such as a flexible substrate.
The step may be to form the amorphous silicon layer into a polycrystalline silicon layer by means of a laser annealing process or the like. The amorphous silicon layer may be formed into a polycrystalline silicon layer in other manners, and the present invention is not limited thereto.
In step 202, a first insulating layer is formed on the polysilicon layer.
The insulating layer in the embodiment of the present invention is made of insulating material, and the insulating material may be, for example, SiNx(silicon nitride), SiO2(silica) or TiO2(titanium dioxide) and the like, but not limited thereto.
In step 203, a gate metal layer is formed on the first insulating layer.
In step 204, a second insulating layer is formed on the gate metal layer.
In step 205, a Cst metal layer (storage capacitor metal layer) is formed on the second insulating layer.
In step 206, a third insulating layer is formed on the Cst metal layer.
And etching the third insulating layer to form a first through hole, a second through hole and a third through hole, wherein the first through hole is connected with the polysilicon layer, the second through hole is connected with the gate metal layer, and the third through hole is connected with the Cst metal layer.
It should be noted that the through hole may be formed by etching, or may be formed in other manners, and the present invention is not limited thereto.
In step 207, an SD metal layer (first source drain metal layer) is formed on the third insulating layer.
In the embodiment of the invention, the SD metal layer may be made of TiAlTi (titanium-aluminum-titanium-composite structure). The SD metal layer typically requires a MASK (MASK) to etch the pattern, which may include more than one. V on the SD metal layerDDThe routing may vary from manufacturer to manufacturer.
In step 208, a fourth insulating layer is formed on the SD metal layer.
And etching the fourth insulating layer to form a fourth through hole and a fifth through hole, wherein the fourth through hole is connected with the first through hole at a position corresponding to the SD metal layer, and the fifth through hole is connected with the third through hole at a position corresponding to the SD metal layer.
The SD metal layer of the embodiment of the invention can play a lapping role, so that the newly arranged VDDThe routing layer, i.e., the SD1 metal layer, can be connected to the underlying polysilicon layer and Cst metal layer.
In step 209, an SD1 metal layer (second source drain metal layer) is formed on the fourth insulating layer.
In the embodiment of the invention, a layer of whole V is addedDDAnd a routing layer, namely, an SD1 metal layer is added on the insulating layer. The SD1 metal layer may be made of TiAlTi (titanium-aluminum-titanium-composite structure).
The SD1 metal layer of the embodiment of the invention does not need to be patterned, and only needs to be arrangedA layer of metal is sufficient. The SD1 metal layer may be provided as a full-surface overlay metal so that the corresponding location of each sub-pixel may be connected through a via. Because the whole SD1 metal layer is added, which is equivalent to VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop generated by the wiring from the input near end to the far end can effectively improve the problem of uneven brightness of the display area caused by the IR _ Drop.
The detailed analysis is as follows:
generally, a resistor having a uniform cross section has a resistance value of
In the above formula, ρ is the resistivity (ohm · cm) of the resistive material, L is the length (cm) of the resistive element, and a is the cross-sectional area (square cm) of the resistive element.
In the case of the thin film resistor, the thickness d is small and is generally difficult to measure, and ρ varies with the thickness d of the thin film resistor, so that a constant related to a thin film material is generally referred to as a film resistance, which is actually a resistance of a square thin film and is also called a sheet resistance Rs (ohm/square). The Rs value is usually within a limited range, and too large Rs affects the stability of the resistor performance. In the embodiment of the invention, the SD1 metal layer is a uniform film, is also used as a resistor body, and belongs to a planar resistor body.
The relationship between the resistance R and the sheet resistance Rs of the SD1 metal layer is as follows:
w in the above formula is the width (cm) of the film.
It can be found that a layer of SD1 metal layer is added in the embodiment of the invention, and the SD1 metal layer is also a uniform film, so that V is formedDDThe trace impedance is designed to be uniformly covered on the whole surface of the SD1 metal layer, namely, the impedance in the formula is increasedThe film width W, the resistance R of the SD1 metal layer becomes smaller, i.e. VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop of the wiring from the input near end to the far end can reduce the current value difference in each pixel circuit, thereby effectively improving the problem of uneven brightness of the display area caused by IR _ Drop and improving the display effect of the display screen.
In step 210, a fifth insulating layer is formed on the SD1 metal layer.
In step 211, a PLN layer (planarization layer) is formed on the fifth insulating layer.
And etching the PLN layer to form a sixth through hole and a seventh through hole, wherein the seventh through hole and the sixth through hole are connected with the SD metal layer and the ANODE layer.
In step 212, an ANODE layer (ANODE layer) is formed on the PLN layer.
It can be found that the technical solution of the embodiment of the present invention reduces V by one kindDDThe wiring impedance mode solves the problem of uneven brightness caused by IR _ Drop voltage Drop commonly existing in the current OLED. Specifically, the entire surface of the SD1 metal layer is increased, which corresponds to the addition of VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop generated by the routing from the input near end to the far end, namely the voltage difference is reduced, so that the current value difference in each pixel circuit is reduced, and the problem of uneven light emitting brightness caused by IR _ Drop in the display area can be effectively solved. In addition, the problem of service life difference of different areas caused by different consumption of light-emitting materials in pixels when the OLED is in a condition of large brightness difference for a long time can be solved.
The above describes the method for manufacturing the display screen in detail, and the structure of the corresponding AMOLED display screen is described below.
FIG. 4 is a schematic structural diagram of an AMOLED display screen according to an embodiment of the present invention.
The structure of the AMOLED display screen is illustrated in a conventional 2T1C pixel structure cross-section in fig. 4, where the reference numerals in fig. 4 include: the semiconductor device includes a substrate 1, a buffer layer 2, a polysilicon layer 3, a first insulating layer 4, a gate metal layer 5, a second insulating layer 6, a Cst metal layer 7, a third insulating layer 8, an SD metal layer 9, a fourth insulating layer 10, an SD1 metal layer 11, a fifth insulating layer 12, a PLN layer 13, an ANODE layer 14, a first via 21, a second via 22, a third via 23, a fourth via 24, a fifth via 25, a sixth via 26, and a seventh via 27.
Referring to fig. 4, an example of the present invention provides an AMOLED display screen:
the AMOLED display screen comprises a substrate 1, a buffer layer 2 and a polycrystalline silicon layer 3, wherein the buffer layer 2 and the polycrystalline silicon layer are formed on the substrate 1;
further comprising a gate metal layer 5, a storage capacitor metal layer (Cst metal layer) 7, a first source drain metal layer (SD metal layer) 9, a second source drain metal layer (SD1 metal layer) 11, a planarization layer (PLN layer) 13, an anode layer 14, and a plurality of interlayer insulating layers (first insulating layer 4, second insulating layer 6, third insulating layer 8, fourth insulating layer 10, fifth insulating layer 12);
the plurality of interlayer insulating layers are respectively positioned among the polycrystalline silicon layer 3, the gate metal layer 5, the storage capacitor metal layer 7, the first source drain metal layer 9, the second source drain metal layer 11 and the planarization layer 13, and the anode layer 14 is positioned on the planarization layer 13;
the second source/drain metal layer 11 is a metal layer covered on the whole surface, and the second source/drain metal layer 11 is connected with the first source/drain metal layer 9, the polysilicon layer 3 and the storage capacitor metal layer 7 through a through hole.
The substrate 1 may be a glass substrate, a flexible substrate, or the like, and the flexible substrate may be a flexible polymer substrate, or the like.
The SD1 metal layer 11 may be a metal layer containing no pattern, and/or the SD1 metal layer 11 may be a metal layer made of TiAlTi (titanium-aluminum-titanium-composite structure).
The SD metal layer 9 is a metal layer including a pattern, and/or the SD metal layer 9 may be a metal layer made of TiAlTi (titanium-aluminum-titanium-composite structure).
At least two through holes formed by etching are formed in the insulating layer on the upper layer of the SD metal layer 9, and the SD1 metal layer 11 is connected with the SD metal layer 9, the polysilicon layer 3 and the Cst metal layer 7 through the at least two through holes.
Wherein a first insulating layer 4 of the plurality of interlayer insulating layers is located on the polysilicon layer 3;
the gate metal layer 5 is located on the first insulating layer 4;
a second insulating layer 6 of the plurality of interlayer insulating layers is located on the gate metal layer 5;
the Cst metal layer 7 is located on the second insulating layer 6;
a third insulating layer 8 of the plurality of interlayer insulating layers is positioned on the Cst metal layer 7;
the SD metal layer 9 is located on the third insulating layer 8;
a fourth insulating layer 10 of the plurality of interlayer insulating layers is located on the SD metal layer 9;
the SD1 metal layer 11 is located on the fourth insulating layer 10;
a fifth insulating layer 12 of the plurality of interlayer insulating layers is located on the SD1 metal layer 11;
the PLN layer 13 is located on the fifth insulating layer 12;
the ANODE layer 14 is located on the PLN layer 13.
Etching the third insulating layer 8 to form a first through hole 21, a second through hole 22 and a third through hole 23, wherein the first through hole 21 is connected with the polysilicon layer 3, the second through hole 22 is connected with the gate metal layer 5, and the third through hole 23 is connected with the Cst metal layer 7;
etching a fourth through hole 24 and a fifth through hole 25 in the fourth insulating layer 10, wherein the fourth through hole 24 is connected with the SD metal layer 9 corresponding to the first through hole 21, and the fifth through hole 25 is connected with the SD metal layer 9 corresponding to the third through hole 23;
and etching a sixth through hole 26 and a seventh through hole 27 in the PLN layer 13, wherein the sixth through hole 26 and the seventh through hole 27 enable the SD metal layer 9 to be connected with the ANODE layer 14.
The utility model also provides a display device has used the structure that above-mentioned figure 4 shows. The display device may be: the liquid crystal display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet personal computer and the like.
In summary, according to the technical solution of the embodiment of the present invention, after the buffer layer and the polysilicon layer are formed on the substrate, the gate metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer, the planarization layer, the anode layer, and the plurality of interlayer insulating layers are respectively formed; the second source drain metal layer is a metal layer added in the embodiment of the invention, and the second source drain metal layer is a metal layer covered on the whole surface and is connected with the first source drain metal layer, the polysilicon layer and the storage capacitor metal layer through the through hole. Because the whole SD1 metal layer is added, which is equivalent to VDDThe impedance of the wiring is designed to be uniformly covered on the whole surface, so VDDThe impedance of the wiring will be reduced, thereby reducing VDDThe voltage Drop generated by the wiring from the input near end to the far end can effectively solve the problem of uneven brightness of a display area caused by IR _ Drop, and the display effect of the AMOLED display screen is improved. In addition, the service life and the luminous efficiency of the OLED can be improved.
The technical solution according to the present invention has been described in detail above with reference to the accompanying drawings.
Those of ordinary skill in the art will understand that: the invention is not to be considered as limited to the specific embodiments thereof, but is to be understood as being modified in all respects, all changes and equivalents that come within the spirit and scope of the invention.
Claims (10)
1. A display screen manufacturing method is characterized by comprising the following steps:
forming a buffer layer and a polysilicon layer on a substrate;
respectively forming a grid metal layer, a storage capacitor metal layer, a first source and drain metal layer, a second source and drain metal layer, a planarization layer, an anode layer and a plurality of interlayer insulating layers;
the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer;
the second source and drain metal layer is a metal layer covered on the whole surface and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole.
2. The method of claim 1, wherein:
the second source drain metal layer is a metal layer without a pattern, and/or,
the second source electrode drain electrode metal layer is made of a titanium-aluminum-titanium-composite structure.
3. The method of claim 1, wherein:
the second source drain metal layer is formed on the interlayer insulating layer on the first source drain metal layer;
and forming the interlayer insulating layer on the second source/drain metal layer.
4. The method of claim 3, further comprising:
and etching the interlayer insulating layer on the upper layer of the first source/drain metal layer to form at least two through holes, and connecting the second source/drain metal layer with the first source/drain metal layer, the polysilicon layer and the storage capacitor metal layer through the at least two through holes.
5. The method of any of claims 1 to 4, wherein the separately forming the gate metal layer, the storage capacitor metal layer, the first source drain metal layer, the second source drain metal layer, the planarization layer, the anode layer, and the plurality of interlayer insulating layers comprises:
forming a first insulating layer on the polysilicon layer;
forming a gate metal layer on the first insulating layer;
forming a second insulating layer on the gate metal layer;
forming a storage capacitor metal layer on the second insulating layer;
forming a third insulating layer on the storage capacitor metal layer;
forming a first source drain metal layer on the third insulating layer;
forming a fourth insulating layer on the first source/drain metal layer;
forming a second source drain metal layer on the fourth insulating layer;
forming a fifth insulating layer on the second source/drain metal layer;
forming a planarization layer on the fifth insulating layer;
an anode layer is formed on the planarization layer.
6. The method of claim 5, further comprising:
etching the third insulating layer to form a first through hole, a second through hole and a third through hole, wherein the first through hole is connected with the polycrystalline silicon layer, the second through hole is connected with the grid metal layer, and the third through hole is connected with the storage capacitor metal layer;
etching the fourth insulating layer to form a fourth through hole and a fifth through hole, wherein the fourth through hole is connected with the first source/drain metal layer corresponding to the first through hole, and the fifth through hole is connected with the first source/drain metal layer corresponding to the third through hole;
and etching the planarization layer to form a sixth through hole and a seventh through hole, wherein the sixth through hole and the seventh through hole enable the first source/drain metal layer to be connected with the anode layer.
7. An AMOLED display screen, which characterized in that:
the buffer layer and the polycrystalline silicon layer are formed on the substrate;
the storage capacitor comprises a storage capacitor metal layer, a grid metal layer, a first source electrode drain electrode metal layer, a second source electrode drain electrode metal layer, a planarization layer, an anode layer and a plurality of interlayer insulating layers;
the interlayer insulating layers are respectively positioned among the polycrystalline silicon layer, the grid metal layer, the storage capacitor metal layer, the first source/drain metal layer, the second source/drain metal layer and the planarization layer, and the anode layer is positioned on the planarization layer;
the second source and drain metal layer is a metal layer covered on the whole surface, and is connected with the first source and drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the through hole.
8. The AMOLED display screen of claim 7, wherein:
the second source drain metal layer is a metal layer without a pattern, and/or,
the second source electrode drain electrode metal layer is a metal layer made of a titanium-aluminum-titanium-composite structure.
9. The AMOLED display screen of claim 7, wherein:
at least two through holes formed by etching are formed in the interlayer insulating layer on the upper layer of the first source/drain metal layer, and the second source/drain metal layer is connected with the first source/drain metal layer, the polycrystalline silicon layer and the storage capacitor metal layer through the at least two through holes.
10. The AMOLED display screen of any one of claims 7 to 9, wherein:
a first insulating layer of the plurality of interlayer insulating layers is positioned on the polysilicon layer;
the grid metal layer is positioned on the first insulating layer;
a second insulating layer of the plurality of interlayer insulating layers is located on the gate metal layer;
the storage capacitor metal layer is positioned on the second insulating layer;
a third insulating layer of the plurality of interlayer insulating layers is located on the storage capacitor metal layer;
the first source/drain metal layer is positioned on the third insulating layer;
a fourth insulating layer of the plurality of interlayer insulating layers is positioned on the first source drain metal layer;
the second source/drain metal layer is positioned on the fourth insulating layer;
a fifth insulating layer of the plurality of interlayer insulating layers is located on the second source drain metal layer;
the planarization layer is positioned on the fifth insulating layer;
the anode layer is on the planarization layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810083885.4A CN108231860B (en) | 2018-01-29 | 2018-01-29 | Display screen manufacturing method and AMOLED display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810083885.4A CN108231860B (en) | 2018-01-29 | 2018-01-29 | Display screen manufacturing method and AMOLED display screen |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108231860A CN108231860A (en) | 2018-06-29 |
| CN108231860B true CN108231860B (en) | 2020-10-02 |
Family
ID=62667712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810083885.4A Active CN108231860B (en) | 2018-01-29 | 2018-01-29 | Display screen manufacturing method and AMOLED display screen |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108231860B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022227055A1 (en) | 2021-04-30 | 2022-11-03 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538421A (en) * | 2014-12-16 | 2015-04-22 | 深圳市华星光电技术有限公司 | OLED display substrate and manufacturing method of OLED display substrate |
| CN104681595A (en) * | 2015-03-11 | 2015-06-03 | 上海和辉光电有限公司 | OLED display panel and bilateral driving method |
| CN105527767A (en) * | 2016-01-25 | 2016-04-27 | 武汉华星光电技术有限公司 | Array substrate and liquid crystal display |
| CN105590953A (en) * | 2014-11-12 | 2016-05-18 | 乐金显示有限公司 | Organic light-emitting diode display having high aperture ratio and method for manufacturing the same |
| KR20160079978A (en) * | 2014-12-26 | 2016-07-07 | 엘지디스플레이 주식회사 | Organic light emitting display device and method of manufacturing the same |
| CN105931988A (en) * | 2016-05-30 | 2016-09-07 | 深圳市华星光电技术有限公司 | Manufacturing method of AMOLED pixel drive circuit |
-
2018
- 2018-01-29 CN CN201810083885.4A patent/CN108231860B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105590953A (en) * | 2014-11-12 | 2016-05-18 | 乐金显示有限公司 | Organic light-emitting diode display having high aperture ratio and method for manufacturing the same |
| CN104538421A (en) * | 2014-12-16 | 2015-04-22 | 深圳市华星光电技术有限公司 | OLED display substrate and manufacturing method of OLED display substrate |
| KR20160079978A (en) * | 2014-12-26 | 2016-07-07 | 엘지디스플레이 주식회사 | Organic light emitting display device and method of manufacturing the same |
| CN104681595A (en) * | 2015-03-11 | 2015-06-03 | 上海和辉光电有限公司 | OLED display panel and bilateral driving method |
| CN105527767A (en) * | 2016-01-25 | 2016-04-27 | 武汉华星光电技术有限公司 | Array substrate and liquid crystal display |
| CN105931988A (en) * | 2016-05-30 | 2016-09-07 | 深圳市华星光电技术有限公司 | Manufacturing method of AMOLED pixel drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108231860A (en) | 2018-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10818739B2 (en) | Manufacture method of an OLED back plate | |
| US20130056784A1 (en) | Organic Light-Emitting Display Device and Method of Fabricating the Same | |
| CN109448635B (en) | OLED display panel | |
| WO2018054149A1 (en) | Organic light-emitting diode (oled) array substrate and fabrication method therefor, display device | |
| CN103839973B (en) | Active matrix organic light-emitting diode array base palte and preparation method and display unit | |
| US11568821B2 (en) | Array substrate and method for manufacturing same and method for controlling same, and display apparatus | |
| US11527735B2 (en) | Flexible display panel with connecting portion and flexible bridging portion, method for manufacturing the same and display device | |
| CN103077944B (en) | Display unit, array base palte and preparation method thereof | |
| US10916613B1 (en) | Array substrate and OLED display device | |
| JP2003308031A (en) | Active matrix organic electroluminescent device | |
| CN108364993B (en) | Display panel manufacturing method, display panel and display device | |
| WO2019105086A1 (en) | Display substrate, and fabrication method therefor, display panel thereof and display device thereof | |
| CN101075635B (en) | image display system | |
| WO2019179058A1 (en) | Oled device and manufacturing method thereof | |
| US20210193819A1 (en) | Thin film transistor array substrate and its manufacturing method and oled touch display device | |
| CN106328715A (en) | Thin film transistor and manufacturing method therefor | |
| KR20160053043A (en) | Organic Light Emitting Display Device and Manufacturing Method thereof | |
| CN113809099A (en) | Array substrate and display panel | |
| WO2024012233A9 (en) | Semiconductor substrate and driving method therefor, and semiconductor display apparatus | |
| KR101689886B1 (en) | Method of fabricating the thin film transistor substrate using a oxidized semiconductor | |
| KR20090002717A (en) | Electroluminescent element and manufacturing method thereof | |
| CN108231860B (en) | Display screen manufacturing method and AMOLED display screen | |
| CN110085678A (en) | The production method of display panel and thin film transistor (TFT) | |
| US10090336B2 (en) | TFT substrate, display device and manufacturing method | |
| US12154510B2 (en) | Display substrate including multiple cascaded shift register units, preparation method thereof, and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |