CN108231738A

CN108231738A - Semiconductor device structure and its manufacturing method

Info

Publication number: CN108231738A
Application number: CN201711480625.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Ruili Integrated Circuit Co Ltd
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-12-29
Filing date: 2017-12-29
Publication date: 2018-06-29

Abstract

The present invention provides a kind of semiconductor device structure and its manufacturing method, and semiconductor device structure includes Semiconductor substrate, wordline, bit line and conductive plug.Several fleet plough groove isolation structures are formed in Semiconductor substrate, fleet plough groove isolation structure isolates several active areas being intervally arranged in Semiconductor substrate；Wordline is located in Semiconductor substrate；Bit line is located in Semiconductor substrate；Bit line is including first part, second part and Part III, on the region that fleet plough groove isolation structure of the Part III between adjacent word line and between adjacent active regions is folded；Conductive plug includes the filling part between adjacent bit lines and extends to the extension in the active area below bit line Part III from the bottom of filling part and side wall.The logical contact area that can greatly increase conductive plug and active area of the present invention, is effectively improved the resistance of conductive plug, and then improves the yield and performance of semiconductor devices.

Description

Semiconductor device structure and its manufacturing method

Technical field

The invention belongs to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor device structure and its manufacturer Method.

Background technology

As dimensions of semiconductor devices reduces, the contact area of contact hole and active area is less and less, especially similar With in the structure of Unit 3 × 2 (cell), due to bit line critical size (CD) increase or occur dislocation (i.e. described bit line some Part is not completely corresponded up and down simultaneously positioned at the top of active area and fleet plough groove isolation structure with active area), this is allowed for Become smaller after the contact hole etching being connected positioned at the bit line with active area described in the part with the area of active region contact, even Can prevent contact hole from active region contact so that the resistance of the conductive plug formed in the contact hole becomes larger or can not It conducts, so as to influence the performance of semiconductor device structure and yield.

Invention content

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor device structure and its Manufacturing method, for solve prior art neutrality line occur dislocation or bit line critical size become larger after so that between bit line The area of conductive plug and active region contact becomes smaller, so that the resistance of conductive plug becomes larger, so as to influence semiconductor devices The problem of structure yield and performance.

To achieve the above object and other related purposes, the present invention provide a kind of semiconductor device structure, the semiconductor Device architecture includes：

Semiconductor substrate is formed with several fleet plough groove isolation structures, the shallow trench isolation in the Semiconductor substrate Structure isolates several active areas being intervally arranged in the Semiconductor substrate；

The wordline of several parallel intervals arrangement, in the Semiconductor substrate, the extending direction of the wordline and institute The extending direction of active area is stated into first angle；

The bit line of several parallel intervals arrangement, in the Semiconductor substrate；The extending direction of the bit line and institute The extending direction of active area is stated into second angle, and with the direction of wordline extension into third angle；Each bit line tool There are first part, second part and Part III；Wherein, the first part of the bit line between the adjacent wordline and with On the region that the active area is folded；The second part of the bit line is located in the wordline；The Part III position of the bit line Between the adjacent wordline, and on the region that is folded of the fleet plough groove isolation structure between the adjacent active area, institute The orthographic projection of the Part III of rheme line on the semiconductor substrate fleet plough groove isolation structure both sides institute also described in partial mulching State the subregion of active area；Along the extending direction of the wordline, the first part of the bit line and adjacent another institute's rheme The Part III of line is located in the same interval between the two adjacent wordline；

Conductive plug, the conductive plug have filling part and the extension extended laterally by the filling part, wherein, The filling part of at least one conductive plug is located in the Semiconductor substrate and in the Part III and phase of the bit line Between the first part of the adjacent bit line, to be electrically connected the active area locally covered by the Part III of the bit line；Institute It states extension to be extended in the active area below the Part III of the bit line by the bottom and side wall of the filling part, make Composition surface between the conductive plug and the active area is on-plane surface.

As a preferred embodiment of the present invention, according to the extending direction of the wordline, the width between the adjacent bit line Width spacing is more than width dimensions of the fleet plough groove isolation structure along the wordline extending direction, and less than the shallow trench isolation Structure is along width dimensions and the active area of the wordline extending direction along the two of the width dimensions of the wordline extending direction Person and.

As a preferred embodiment of the present invention, the bit line includes laminated construction and is covered in the laminated construction periphery Sidewall structure, wherein, the laminated construction includes the conducting wire adhesion layer, guidewire body layer and the top layer that are sequentially stacked from the bottom to top Dielectric layer；The semiconductor device structure further includes isolated insulation layer, and the isolated insulation layer is located at the third portion of the bit line Below point, and between the laminated construction and the Semiconductor substrate.

As a preferred embodiment of the present invention, the material of the conducting wire adhesion layer is included by tungsten silicide, titanium nitride and is led The one of which of electric type silicide, the material of the guidewire body layer include tungsten, and the material of the top layer dielectric layer includes nitridation Silicon.

As a preferred embodiment of the present invention, the sidewall structure includes first medium layer, second dielectric layer and third Dielectric layer, wherein, the first medium layer is covered on the outer wall of the laminated construction, and the second dielectric layer is covered in described On the outer wall of first medium layer, the third dielectric layer is covered on the outer wall of the second dielectric layer.

As a preferred embodiment of the present invention, the material of the isolated insulation layer includes nonconductive DOPOS doped polycrystalline silicon.

As a preferred embodiment of the present invention, the semiconductor device structure further includes bit line contact, and the bit line connects It touches below the first part of the bit line, institute's bitline contact is electrically connected the laminated construction and the active area.

As a preferred embodiment of the present invention, the material of institute's bitline contact includes conductivity type DOPOS doped polycrystalline silicon.

As a preferred embodiment of the present invention, the basic material of institute's bitline contact and the isolated insulation layer is formed in Same polysilicon layer.

As a preferred embodiment of the present invention, corresponding to the first part of the bit line, the Semiconductor substrate has Groove is formed by the etching removal part active area and the part fleet plough groove isolation structure, and the width of the groove is big In the width of institute's bitline contact, an at least dielectric layer for the sidewall structure of the bit line fills up the groove and connects institute State fleet plough groove isolation structure.

As a preferred embodiment of the present invention, the bottom of the filling part of the conductive plug is not less than the bottom of the groove Portion, and not higher than the top surface of the active area.

As a preferred embodiment of the present invention, the shape in the extension section is included with the bottom with the filling part The arc that portion and side wall are connected.

As a preferred embodiment of the present invention, the extension is from the bottom of the filling part and side wall to described active The size extended in area is between 0.1nm~50nm.

The present invention also provides a kind of manufacturing method in semiconductor device structure, the manufacturers of the semiconductor device structure Method includes the following steps：

1) semi-conductive substrate is provided, several fleet plough groove isolation structures are formed in the Semiconductor substrate, it is described shallow Groove isolation construction isolates several active areas being intervally arranged in the Semiconductor substrate；

2) in formed in the Semiconductor substrate several parallel intervals arrangement wordline, the extending direction of the wordline with The extending direction of the active area is into first angle；

3) bit line of several parallel intervals arrangement is formed in the upper surface of the Semiconductor substrate；The extension of the bit line The extending direction of direction and the active area is into second angle, and with the direction of wordline extension into first angle；Each institute Rheme line has first part, second part and Part III；Wherein, the first part of the bit line is located at the adjacent wordline Between and the region that is folded with the active area on；The second part of the bit line is located in the wordline；The of the bit line Three parts are between the adjacent wordline, and the area that the fleet plough groove isolation structure between the adjacent active area is folded On domain, fleet plough groove isolation structure described in the orthographic projection also partial mulching of the Part III of the bit line on the semiconductor substrate The subregion of active area described in both sides；Along the extending direction of the wordline, the first part of the bit line with it is adjacent another The Part III of the bit line is located in the same interval between the two adjacent wordline；

4) in forming filled media layer in the Semiconductor substrate, the filled media layer is covered in the wordline and is filled up Gap between the adjacent bit line；

5) form contact hole in the filled media layer between the bit line, the contact hole include filling hole and The elongated hole extended laterally by the filling hole, wherein, the filling hole of at least one contact hole is located at a bit line Part III and another bit line adjacent thereto first part between, be electrically connected by the Part III of the bit line The active area locally covered；The elongated hole is extended to the third portion of the bit line by the bottom and side wall in the filling hole In the active area below point, it is on-plane surface to make the composition surface between the filling hole and the active area；

6) in filling conductive material in the contact hole, the conductive material fills up the contact hole to form the conduction Embolism.

As a preferred embodiment of the present invention, step 3) includes the following steps：

3-1) in the laminated construction that the arrangement of several parallel intervals is formed in the Semiconductor substrate, the lamination packs Include the conducting wire adhesion layer being sequentially stacked from the bottom to top, guidewire body layer and top layer dielectric layer；The extending direction of the laminated construction Extending direction with the active area is into second angle, and with the direction of wordline extension into third angle；

3-2) sidewall structure is formed in the periphery of the laminated construction.

As a preferred embodiment of the present invention, step 3-1) further include following steps before：

The etching removal part active area and the part fleet plough groove isolation structure are to form groove, and the groove is with walking Rapid 5) the middle filling hole formed is adjoining；

In forming polysilicon layer on the bottom portion of groove and the Semiconductor substrate, the polysilicon layer defines described folded The position of layer structure and shape；The part that the polysilicon layer is located at the bottom portion of groove is the bit line and the active area The bit line contact being connected；

The part polysilicon layer corresponded to below the Part III of the bit line is doped exhausted to form isolation Edge layer.

As a preferred embodiment of the present invention, step 3-2) in include the following steps：

It 3-2-1) is formed in the periphery of the laminated construction and covers the first medium layer of the laminated construction outer wall, described the One dielectric layer fills up the groove；

The second dielectric layer of the covering first medium layer outer wall 3-2-2) is formed in the periphery of the first medium layer；

The third dielectric layer of the covering second dielectric layer outer wall 3-2-3) is formed in the periphery of the second dielectric layer.

As a preferred embodiment of the present invention, step 3-2-1) in, the first medium layer fills up the groove, is formed While the first medium layer, passivation layer is formed in the exposed upper surface of the Semiconductor substrate.

As a preferred embodiment of the present invention, in the bit line formed in step 3), the extension according to the wordline Direction, the wide cut spacing between the adjacent bit line are more than width of the fleet plough groove isolation structure along each wordline extending direction Size is spent, and less than described in the fleet plough groove isolation structure along the width dimensions of the wordline extending direction and active area edge The two of the width dimensions of wordline extending direction and.

As a preferred embodiment of the present invention, step 5) includes the following steps：

5-1) removal positioned at the bit line between the filled media layer, and remove positioned at the bit line Part III with The part active area and the part fleet plough groove isolation structure between the first part of the bit line is to form the filling Hole；

5-2) described in continuing to etch below the Part III of the bit line from the bottom in the filling hole and side wall Active area, to form the elongated hole.

As a preferred embodiment of the present invention, step 5-2) in, using isotropic etching (Isotropic etch) Technique forms the elongated hole.

As a preferred embodiment of the present invention, the elongated hole that is formed in isotropic etching technique is from the filling The size that the bottom in hole and side wall extend into the active area is between 0.1nm~50nm.

The present invention also provides a kind of semiconductor device structure, the semiconductor device structure includes：

Semiconductor substrate is formed with several fleet plough groove isolation structures, and the fleet plough groove isolation structure is in the semiconductor Several active areas being intervally arranged are isolated in substrate；

The bit line of several parallel intervals arrangement, in the Semiconductor substrate；The extending direction of the bit line and institute The extending direction of active area is stated into second angle, and with the direction of wordline extension into third angle；Each bit line tool There are first part, second part and Part III；Wherein, the first part of the bit line between the adjacent wordline and with On the region that the active area is folded；The second part of the bit line is located in the wordline；The Part III position of the bit line It is described on the region that the fleet plough groove isolation structure between the adjacent wordline and between the adjacent active area is folded Described in the orthographic projection of the Part III of bit line on the semiconductor substrate also fleet plough groove isolation structure both sides described in partial mulching The subregion of active area；Along the extending direction of the wordline, the first part of the bit line and adjacent another bit line Part III be located in the same interval between the two adjacent wordline；The Semiconductor substrate has the first groove, is located at The first part bottom of the bit line；The Semiconductor substrate also have the second groove, positioned at the bit line first part with In the active area between the Part III of the adjacent bit line, second groove and first groove are adjoining；

Conductive plug has filling part and the extension extended laterally by the filling part, wherein, at least led described in one The filling part of electric embolism is located in the Semiconductor substrate and the Part III in the bit line and the adjacent bit line Between first part, and fill up second groove, with electrical connection by the Part III of the bit line locally cover described in have Source region；The extension is extended to described active below the Part III of the bit line by the bottom and side wall of the filling part In area, it is on-plane surface to make the composition surface between the conductive plug and the active area.

As a preferred embodiment of the present invention, the bit line includes laminated construction and is covered in the laminated construction periphery Sidewall structure, wherein, the laminated construction includes the conducting wire adhesion layer, guidewire body layer and the top layer that are sequentially stacked from the bottom to top Dielectric layer.

As a preferred embodiment of the present invention, a dielectric layer of the laminated construction fills up first groove and connects The fleet plough groove isolation structure.

As a preferred embodiment of the present invention, the sidewall structure includes first medium layer, second dielectric layer and third Dielectric layer, wherein, the first medium layer is covered on the outer wall of the laminated construction, and fills up first groove, described Second dielectric layer is covered on the outer wall of the first medium layer, and the third dielectric layer is covered in the outer of the second dielectric layer On wall.

As a preferred embodiment of the present invention, the semiconductor device structure further includes isolated insulation layer, the isolation Insulating layer is located at below the Part III of the bit line, and between the laminated construction and the Semiconductor substrate.

As a preferred embodiment of the present invention, the semiconductor device structure further includes bit line contact, and the bit line connects It touches and is located in first groove, and below the first part of the bit line, institute's bitline contact is electrically connected the laminated construction With the active area positioned at first bottom portion of groove.

As a preferred embodiment of the present invention, the material of institute's bitline contact includes conductivity type DOPOS doped polycrystalline silicon, described The material of isolated insulation layer includes nonconductive DOPOS doped polycrystalline silicon.

As a preferred embodiment of the present invention, the bottom of the filling part of the conductive plug is not less than first groove Bottom, and not higher than the active area top surface.

As described above, semiconductor device structure provided by the invention and its manufacturing method, have the advantages that：This hair In bright semiconductor device structure, extended to by being added below the conductive plug filling part between bit line positioned at bit line Part III below active area in extension, the contact area of conductive plug and active area can be greatly increased, effectively Improve the resistance of conductive plug, and then improve the yield and performance of semiconductor devices.

Description of the drawings

Fig. 1 is shown as the flow chart of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention.

Fig. 2 and Fig. 3 is shown as the step 1) of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention Partial cross section's structure diagram of the structure of middle offer, wherein, Fig. 2 is overlooking the structure diagram, and Fig. 3 is along AA ' directions in Fig. 2 Cross section structure schematic diagram.

Fig. 4 is obtained after being shown as the step 2) of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention The overlooking the structure diagram of structure.

Fig. 5 to Figure 12 is shown as the step 3) of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention The schematic diagram of structure is obtained afterwards, wherein, Figure 12 is the overlooking the structure diagram of structure obtained after step 3), and Figure 11 is in Figure 12 Along the cross section structure schematic diagram in AA ' directions.

Figure 13 is obtained after being shown as the step 4) of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention Partial cross section's structure diagram of the structure arrived.

Figure 14 to Figure 15 is shown as the step of manufacturing method of the semiconductor device structure provided in one embodiment of the invention 5) partial cross section's structure diagram of the structure obtained after.

Figure 16 is obtained after being shown as the step 6) of the manufacturing method of the semiconductor device structure provided in one embodiment of the invention Partial cross section's structure diagram of the structure arrived.

Figure 17 is shown as the cross section structure schematic diagram of the semiconductor device structure provided in one embodiment of the invention.

Reference numerals explanation

10 Semiconductor substrates

101 grooves

11 groove isolation constructions

12 active areas

13 wordline

14 bit lines

141 first parts

142 second parts

143 Part III

144 laminated construction

144a conducting wire adhesion layers

144b guidewire body layers

144c top layer dielectric layers

145 sidewall structures

145a first medium layers

145b second dielectric layer

145c third dielectric layers

146 bit line contacts

147 polysilicon layers

148 isolated insulation layers

15 filled media layers

16 contact holes

161 filling holes

162 elongated holes

17 conductive plugs

171 filling parts

172 extensions

18 passivation layers

19 first grooves

20 second grooves

The size that d extensions extend to bit line lower section

α first angles

β second angles

γ third angles

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Disclosed content understands the further advantage and effect of the present invention easily.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.

It please refers to Fig.1 to Figure 17.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though package count when only display is with related component in the present invention rather than according to actual implementation in diagram Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during actual implementation, and its Assembly layout form may also be increasingly complex.

Referring to Fig. 1, the present invention provides a kind of manufacturing method of semiconductor device structure, the semiconductor device structure Manufacturing method includes the following steps：

1) semi-conductive substrate is provided, is formed with several fleet plough groove isolation structures, the fleet plough groove isolation structure is in institute It states and several active areas being intervally arranged is isolated in Semiconductor substrate；

3) bit line of several parallel intervals arrangement, the extension of the bit line are formed in the upper surface of the Semiconductor substrate The extending direction of direction and the active area is into second angle, and with the direction of wordline extension into third angle；Each institute Rheme line has first part, second part and Part III；Wherein, the first part of the bit line is located at the adjacent wordline Between on the region that is folded with institute active area；The second part of the bit line is located in the wordline；The third portion of the bit line Divide between the adjacent wordline, and the region that the fleet plough groove isolation structure between the adjacent active area is folded On, fleet plough groove isolation structure two described in the orthographic projection also partial mulching of the Part III of the bit line on the semiconductor substrate The subregion of active area described in side；Along the extending direction of the wordline, the first part of the bit line and adjacent another institute The Part III of rheme line is located in the same interval between the two adjacent wordline；

5) form contact hole in the filled media layer between the bit line, the contact hole include filling hole and The elongated hole extended laterally by the filling hole, wherein, the filling hole of at least one contact hole is located at a bit line Part III and another bit line adjacent thereto first part between, be electrically connected by the Part III of the bit line The institute's active area locally covered；The elongated hole is extended to the Part III of the bit line by the bottom and side wall in the filling hole In the active area of lower section, it is on-plane surface to make the composition surface between the filling hole and the active area；

In step 1), S1 steps and Fig. 2 to Fig. 3 in please referring to Fig.1 provide semi-conductive substrate 10, if being formed with Dry fleet plough groove isolation structure 11, the fleet plough groove isolation structure 11 isolate several intervals in the Semiconductor substrate 10 The active area 12 of arrangement.

As an example, the Semiconductor substrate 10 can include silicon substrate, gallium nitride substrate, Sapphire Substrate etc., this Place is not specifically limited.

As an example, after the fleet plough groove isolation structure 11 can be by forming groove in the Semiconductor substrate 10, It fills spacer material layer in the trench again and is formed.The material of the fleet plough groove isolation structure 11 can include silicon nitride, oxidation Silicon etc..The shape in 11 section of fleet plough groove isolation structure can be set according to actual needs, with the shallow ridges in Fig. 3 The shape in 11 section of recess isolating structure includes inverted trapezoidal as an example, in actual example, and the fleet plough groove isolation structure 11 is cut The shape in face is not limited thereto.

As an example, being formed with MOS device (not shown) in the active area 12, the MOS device includes grid, source electrode And drain electrode；Wherein, the source electrode is located at the opposite both sides of the grid with drain electrode distribution.

In step 2), S2 steps and Fig. 4 in please referring to Fig.1 are flat in forming several in the Semiconductor substrate 10 The wordline 13 of between-line spacing arrangement, and the extending direction of the extending direction of the wordline 13 and the active area 12 is into first angle α.

It is as an example, known to those skilled in the art in the method that the wordline 13 is formed in the Semiconductor substrate 10 It dawn, is not repeated herein.When being formed with the MOS device in the active area 12, the wordline 13 and the MOS device Grid is connected.

As an example, the numerical value of the first angle α can be less than 90 °, it is preferable that in the present embodiment, described first jiao The numerical value of α is spent between 20 °~60 °.

In step 3), S3 steps and Fig. 5 to Figure 12 in please referring to Fig.1, in the upper surface of the Semiconductor substrate 10 Form the bit line 14 of several parallel intervals arrangement；The extending direction of the extending direction of the bit line 14 and the active area 12 into Second angle β, and with the direction of the wordline 13 extension into third angle γ；Each bit line 14 have first part 141, Second part 142 and Part III 143；Wherein, the first part 141 of the bit line 14 between the adjacent wordline 13 and On the region being folded with the active area 12；The second part 142 of the bit line 14 is located in the wordline 13；The bit line 14 Part III 143 between the adjacent wordline 13, and the shallow trench isolation between the adjacent active area 12 On the region that structure 11 is folded, the orthographic projection of the Part III 143 of the bit line 14 in the Semiconductor substrate 10 is also local Cover the subregion of active area 12 described in 11 both sides of fleet plough groove isolation structure；Along the extending direction of the wordline 13, institute The first part 141 of rheme line 14 is located on two with the Part III 143 of adjacent another bit line 14 and is connected between the wordline 13 In same interval.

As an example, form the bit line 14 of several parallel intervals arrangement in the upper surface of the Semiconductor substrate 10 Following steps are further included before：

The part active area 12 and the part shallow trench where removing the drain electrode using lithographic etch process etching Isolation structure 11 is to form groove 101, as shown in Figure 5；The groove 101 is adjacent with the filling hole formed in step 5) Closely；

In formation polysilicon layer 147, the polysilicon layer 147 on 101 bottom of groove and the Semiconductor substrate 10 Define position and the shape for the laminated construction being subsequently formed；The polysilicon layer 147 is located at the part of 101 bottom of groove The bit line contact 146 that as described bit line 14 is connected with the active area 12, as shown in Figure 6；Specifically, when the active area When the MOS device is formed in 12, institute's bitline contact 146 is connected with the drain electrode；

The part progress conductivity type that the polysilicon layer 147 is corresponded to 141 lower section of first part of the bit line 14 is mixed It is miscellaneous, bitline contact 146 to obtain；The polysilicon layer 147 is corresponded to 143 lower section of Part III of the bit line 14 Part carries out nonconductive doping to form isolated insulation layer 148, as shown in Figure 7.It it should be noted that can be by correspondence The polysilicon layer 147 in 143 lower section of Part III of the bit line 14 carries out ion doping, so that described more at this Crystal silicon layer 147 has insulating properties；It certainly, in other examples, can also be under the Part III 143 corresponding to the bit line 14 The rectangular insulating layer into other materials is using as the isolated insulation layer 148.

As an example, when being formed with the MOS device in the active area 12, the bit line 14 is connected with the drain electrode It connects, specifically, the first part 141 of the bit line 14 is connected with the drain electrode；The Part III 143 of the bit line 14 is in institute It states orthographic projection in Semiconductor substrate 10 and covers the fleet plough groove isolation structure 11 between the adjacent source electrode and described active The subregion in area 12.

As an example, step 3) includes the following steps：

3-1) in the laminated construction 144 that the arrangement of several parallel intervals is formed in the Semiconductor substrate 10, the lamination Structure 144 includes the conducting wire adhesion layer 144a, guidewire body layer 144b and the top layer dielectric layer 144c that are sequentially stacked from the bottom to top, such as Shown in Fig. 8 to Figure 10；The extending direction of the extending direction of the laminated construction 144 and the active area 12 into second angle β, and Direction with the wordline 13 extension is into third angle γ；

Sidewall structure 145 3-2) is formed in the periphery of the laminated construction 144, as shown in figure 11.

As an example, step 3-1) in, the material of the conducting wire adhesion layer 144a can include but be not limited only to tungsten silicide (WSi), the one of which of titanium nitride (TiN) and conduction type silicon compound；The material of the guidewire body layer 144b can include but It is not limited only to tungsten (W)；The material of the top layer dielectric layer 143 can include but be not limited only to silicon nitride (SiN).

Specifically, step 3-2) in include the following steps：

The first medium layer of covering 144 outer wall of laminated construction 3-2-1) is formed in the periphery of the laminated construction 144 145a；The material of the first medium layer 145a can include but are not limited to silicon nitride, and the first medium layer 145a is filled up The groove 101；The first medium layer 145a of the groove 101 is filled up for the elongated hole 162 to be avoided to extend to institute The inside and lower section of bitline contact 146 so that the extension of the conductive plug formed in step 6) is relatively distant from Institute's bitline contact 146, to control the lateral erosion direction of the elongated hole 162.

It 3-2-2) is formed in the periphery of the first medium layer 145a and covers the second of the first medium layer 145a outer walls Dielectric layer 145b；The material of the second dielectric layer 145b can include but are not limited to silica (SiOx)；

The third of the covering second dielectric layer 145b outer walls 3-2-3) is formed in the periphery of the second dielectric layer 145b Dielectric layer 145c；The material of the third dielectric layer 145c can include but are not limited to silicon nitride.

As an example, step 3-2-1) in, the first medium layer 145a fills up the groove 101, forms described first While dielectric layer 145a, passivation layer 18 is formed in the exposed upper surface of the Semiconductor substrate 10.Specifically, form described the During one dielectric layer 145a, the first medium layer 145a is covered in the surface of the Semiconductor substrate 10 simultaneously, is covered in described The first medium layer 145a on 10 surface of Semiconductor substrate is the passivation layer 18.

As an example, the vertical view of the structure obtained after step 3) is as shown in figure 12, Figure 11 is along AA ' directions in Figure 12 Cross section structure schematic diagram, in the bit line 14 formed in step 3), according to the extension program of the wordline 13, adjacent institute's rheme Wide cut spacing between line 14 is more than width dimensions of the fleet plough groove isolation structure 11 along each 13 extending direction of wordline, and Less than the fleet plough groove isolation structure 11 along width dimensions and the active area 12 of each 13 extending direction of wordline along each institute State the width dimensions of 13 extending direction of wordline the two and.

In step 4), S4 steps and Figure 13 in please referring to Fig.1, in forming filled media in the Semiconductor substrate 10 Layer 15, the filled media layer 15 covers in the wordline 13 and fills up the gap between the bit line 14.

As an example, physical gas-phase deposition or the chemical vapor deposition method deposition filled media layer may be used 15, at the beginning of deposition is completed, the upper surface of the filled media layer 15 in the Semiconductor substrate 10 can be higher than described The upper surface of bit line 14, can also be with the upper surface flush of the bit line 14.

As an example, the material of the filled media layer 15 can be but be not limited only to SiOx.

As an example, the forming position of the filled media layer 15 correspond to the wordline 13, with 14th area of bit line It is separated out the source-drain electrode contact zone of array arrangement.

It should be noted that if the upper surface of the filled media layer 15 is higher than the upper surface of the bit line 14, in described Filled media layer 15 is formed in Semiconductor substrate 10 later can also be flat including carrying out surface with the structure obtained to step 4) The step of changing processing；Specifically, CMP process (CMP) removal, which may be used, is located at the described of 14 top of bit line Filled media layer 15 so that the upper surface of the filled media layer 15 of reservation and the upper surface flush of the bit line 14.

In step 5), S5 steps and Figure 14 to Figure 15 in please referring to Fig.1, the filling between the bit line 14 Contact hole 16 is formed in dielectric layer 15, the contact hole 16 includes filling hole 161 and fills what hole 161 extended laterally by described Elongated hole 162, wherein, the filling hole 161 of at least one contact hole 16 is located at the Part III 143 of a bit line 14 Between the first part 141 of another bit line 14 adjacent thereto, to be electrically connected 143 innings of the Part III of the bit line 14 The active area 12 that portion covers；The elongated hole 162 extends to the bit line 14 by the bottom and side wall in the filling hole 161 The lower section of Part III 143 the active area 12 in, make the composition surface between the filling hole 161 and the active area 12 be On-plane surface.

As an example, when being formed with the MOS device in the active area 12, the filling hole 161 and the MOS device Source electrode be in contact.

As an example, step 5) includes the following steps：

5-1) removal filled media layer 15 positioned at the bit line 14 between, and remove and be located at the of the adjacent bit line The part active area 12 and the part fleet plough groove isolation structure 11 between the first part of three parts and the bit line with The filling hole 161 is formed, as shown in figure 14；Specifically, photoetching and the etching removal of dry or wet etch technique may be used The filled media layer 15 between the bit line 14, and continue the part active area where etching removes the source electrode 12 and the part fleet plough groove isolation structure 11 with formed it is described filling hole 161；

5-2) continue etching under the Part III 143 of the bit line 14 from the bottom in the filling hole 161 and side wall The active area 12 of side, to form the elongated hole 162, as shown in figure 15.

As a preferred embodiment of the present invention, step 5-2) in, using isotropic etching (Isotropic etch) Technique forms the elongated hole；Specifically, hole 161 is filled from described using isotropic etching (Isotropic etch) technique Bottom and side wall continue etching and be located at the active area 12 of 14 lower section of the bit line to form the elongated hole 162.It is each to Since the rate etched to all directions is identical during isotropic etch process, 162 section of the elongated hole obtained after etching Shape can be with the arc that is connected of the filling hole 161.Certainly, in other examples, other can also be used Etching technics form the elongated hole 162, the shape in 162 section of elongated hole can also be set according to actual needs It is fixed.

As an example, the elongated hole 162 extends from the bottom in the filling hole 161 and side wall into the active area 12 Size can be set according to actual needs, it is preferable that in the present embodiment, the elongated hole 162 from it is described filling hole 161 Bottom and the size that extends into the active area 12 of side wall between 0.1nm~50nm.

In step 6), S6 steps and Figure 16 in please referring to Fig.1, in filling conductive material, institute in the contact hole 16 It states conductive material and fills up the contact hole 16 to form the conductive plug 17.

As an example, the conductive material fills up the filling hole 161 and the elongated hole in the contact hole 16 162, the conductive plug 17 of formation just includes the filling part 171 being located in the filling hole 161 and positioned at the elongated hole Extension 1672 in 162, the extension 172 are connected with the bottom of the filling part 171 and side wall, and from the filling The bottom in portion 171 and side wall are extended in the active area 12 of 143 lower section of Part III of the bit line 14.

As an example, physical gas-phase deposition or chemical vapor deposition method etc. may be used into the contact hole 16 Conductive material is filled to form the conductive plug 17；The material of the conductive plug 17 can include copper, aluminium, silver, tin, doping At least one of polysilicon etc..

The present invention semiconductor device structure manufacturing method manufacture the semiconductor device structure in, by positioned at 171 lower section of filling part of the conductive plug 17 between the bit line 14, which is added, to be extended to positioned at the third portion of the bit line 14 Divide the extension 172 in the active area 12 of 143 lower sections, the conductive plug 17 and the active area 12 can be greatly increased Contact area, be effectively improved the resistance of the conductive plug 17, and then improve the yield and performance of semiconductor devices.

Please continue to refer to Fig. 1 to Figure 16, the present invention also provides one kind in semiconductor device structure, the junction of semiconductor device Structure includes：Semiconductor substrate 10 is formed with several fleet plough groove isolation structures 11, the shallow trench in the Semiconductor substrate 10 Isolation structure 11 isolates several active areas 12 being intervally arranged in the Semiconductor substrate 10；Several parallel intervals are arranged The wordline 13 of cloth, the wordline 13 are located in the Semiconductor substrate 10, and the extending direction of the wordline and the active area 12 extending direction is into first angle α；The bit line 14 of several parallel intervals arrangement, the bit line 14 are located at semiconductor lining On bottom 10；The extending direction of the extending direction of the bit line 14 and the active area 12 into second angle β, and with the wordline 13 The direction of extension is into third angle γ；Each bit line 14 has first part 141, second part 142 and Part III 143；Wherein, the first part 141 of the bit line 14 is folded between the adjacent wordline 13 and with the active area 12 On region；The second part 142 of the bit line 14 is located in the wordline 13；The Part III 143 of the bit line 14 is located at phase Between the adjacent wordline 13, and on the region that is folded of the fleet plough groove isolation structure 11 between the adjacent active area 12； Shallow trench isolation knot described in orthographic projection also partial mulching of the Part III 143 of the bit line 14 in the Semiconductor substrate 10 The subregion of active area 12 described in 11 both sides of structure；Along the extending direction of the wordline 13, the first part 141 of the bit line 14 It is located in the same interval between the two adjacent wordline 13 with the Part III 143 of adjacent another bit line 14；It is conductive Embolism 17, the conductive plug 17 have filling part 171 and the extension 172 extended laterally by the filling part 171, In, the filling part 171 of at least one conductive plug 17 is located in the Semiconductor substrate 10, and in the bit line 14 Between the first part 141 of Part III 143 and the adjacent bit line, to be electrically connected by the Part III 143 of the bit line 14 The active area 12 locally covered；The extension 172 extends to the bit line by the bottom and side wall of the filling part 171 In the active area 12 of 14 143 lower section of Part III, make the engagement between the conductive plug 17 and the active area 12 Face is on-plane surface.

As an example, after the fleet plough groove isolation structure 11 can be by forming groove in the Semiconductor substrate 10, It fills spacer material layer in the trench again and is formed.The material of the fleet plough groove isolation structure 11 can include silicon nitride, oxidation Silicon etc..The shape in 11 section of fleet plough groove isolation structure can be set according to actual needs, with described shallow in Figure 16 The shape in 11 section of groove isolation construction includes inverted trapezoidal as an example, in actual example, the fleet plough groove isolation structure 11 The shape in section is not limited thereto.

As an example, being formed with MOS device (not shown) in the active area 12, the MOS device includes grid, source electrode And drain electrode；Wherein, the source electrode is located at the opposite both sides of the grid with drain electrode distribution.The wordline 13 and the MOS device The grid be connected, the Part III 143 of the bit line 14 is connected with the drain electrode of the MOS device, the conductive plugs Plug 17 is connected with the source electrode of the MOS device.

As an example, the bit line 14 includes laminated construction 144 and the side wall knot for being covered in 144 periphery of laminated construction Structure 145, wherein, the laminated construction 144 includes the conducting wire adhesion layer 144a, the guidewire body layer 144b that are sequentially stacked from the bottom to top And top layer dielectric layer 144c；The semiconductor device structure further includes isolated insulation layer 148, and the isolated insulation layer 148 is located at 143 lower section of Part III of the bit line 14, and between the laminated construction 144 and the Semiconductor substrate 10, such as scheme Shown in 10.

As an example, the material of the isolated insulation layer 148 includes nonconductive DOPOS doped polycrystalline silicon.

As an example, the material of the conducting wire adhesion layer 144a includes WSi (silicide), titanium nitride (TiN) and conductivity type The one of which of silicide, the material of the guidewire body layer 144b include W (tungsten), the material packet of the top layer dielectric layer 144c Containing SiN (silicon nitride).

As an example, the sidewall structure 145 includes first medium layer 145a, second dielectric layer 145b and third dielectric layer 145c, wherein, the first medium layer 145a is covered on the outer wall of the laminated construction 144, the second dielectric layer 145b It is covered on the outer wall of the first medium layer 145a, the third dielectric layer 145c is covered in the second dielectric layer 145b's On outer wall, as shown in figure 11.

As an example, the material of the first medium layer 145a and the third dielectric layer 145c include SiN；Described The material of second medium layer 145b includes silica (SiOx).

As an example, the extension program according to the wordline 13, the wide cut spacing between the adjacent bit line 14 is more than institute Width dimensions of the fleet plough groove isolation structure 11 along 13 extending direction of wordline are stated, and less than 11 edge of fleet plough groove isolation structure The width dimensions of 13 extending direction of wordline and the active area 12 are along the two of the width dimensions of 13 extending direction of wordline Person and.

As an example, the semiconductor device structure further includes bit line contact 146, institute's bitline contact 146 is located at described 141 lower section of first part of bit line 14, institute's bitline contact 146 are electrically connected the laminated construction 11 and the active area 12.Tool Body, institute's bitline contact 146 is electrically connected the drain electrode of the laminated construction 11 and the MOS device；More specifically, institute's rheme The material of line contact 146 includes conductivity type DOPOS doped polycrystalline silicon.

As an example, corresponding to the first part 141 of the bit line 14, the Semiconductor substrate 10 has groove 101, by The etching removal part active area 12 and the part fleet plough groove isolation structure 11 are formed, and the width of the groove 101 is big In the width of institute's bitline contact 146, an at least dielectric layer for the sidewall structure 145 of the bit line 14 fills up the groove 101 and connect the fleet plough groove isolation structure 11.Specifically, the first medium layer 145a fills up the groove 101 and connects The fleet plough groove isolation structure 11.The first medium layer 145a of the groove 101 is filled up for avoiding the conductive plug 17 extension 172 extends to the inside and lower section of institute's bitline contact 146 so that the extension of the conductive plug 17 172 are relatively distant from institute's bitline contact 146, to control the extending direction of the extension 172, so as to increase the conductive plug The isolation effect of 17 active area 12 with being located at 146 lower section of institute's bitline contact, avoids the two misconnection short circuit.

As an example, institute's bitline contact 146 and the basic material of the isolated insulation layer 148 are formed in same polysilicon Layer.

As an example, the semiconductor device structure further includes passivation layer 18, the passivation layer 18, which is covered in, described partly leads On the exposed upper surface of body substrate 10, the material of the passivation layer 18 can with the material identical of the first medium layer 145a, It can be formed while the first medium layer 145a is formed.

As an example, the semiconductor device structure further includes filled media layer 15, the filled media layer 15 is located at institute It states on passivation layer 18, the material of the filled media layer 15 can include silica (SiOx).The filled media layer 15 it is upper Surface can be with the upper surface flush of the bit line 14, and certainly, the upper surface of the filled media layer 15 can also be higher than institute The upper surface of rheme line 14, as shown in figure 13.

As an example, the shape in 172 section of extension includes having and the bottom of the filling part 171 and side wall phase The arc of connection.Certainly, in other examples, the shape in 172 section of extension can also be set as according to actual needs Other arbitrary shapes, as shown in figure 15.

As an example, the extension 172 extends from the bottom of the filling part 171 and side wall into the active area 12 Size d can be set according to actual needs, it is preferable that in this implementation, the extension 172 is from the filling part 171 Bottom and the size d that extends into the active area 12 of side wall between 0.1nm~50nm.

As an example, the material of the conductive plug 17 can be included in copper, aluminium, silver, tin, DOPOS doped polycrystalline silicon etc. at least It is a kind of.

As an example, the bottom of the filling part 171 of the conductive plug 17 is not less than the bottom of the groove 101, and not Higher than the top surface of the active area 12.

7 are please referred to Fig.1, the present invention also provides a kind of semiconductor device structure, the semiconductor device structure includes：Partly lead Body substrate 10, the Semiconductor substrate 10 are formed with several fleet plough groove isolation structures 11, and the fleet plough groove isolation structure 11 exists Several active areas 12 being intervally arranged are isolated in the Semiconductor substrate 10；The wordline 13 of several parallel intervals arrangement, The wordline 13 is located in the Semiconductor substrate 10, the extending direction of the extending direction of the wordline 13 and the active area 12 Into first angle α；The bit line 14 of several parallel intervals arrangement, the bit line 14 are located in the Semiconductor substrate 10；It is described The extending direction of the extending direction of bit line 14 and the active area 12 is into second angle β, and the direction extended with the wordline 13 Into third angle γ；Each bit line 14 has first part 141, second part 142 and Part III 143；Wherein, it is described The first part 141 of bit line 14 is between the adjacent wordline 13 and on the region that is folded with the active area 12；Institute's rheme The second part 142 of line 14 is located in the wordline 13；The Part III 143 of the bit line 14 be located at the adjacent wordline 13 it Between and the region that is folded of the fleet plough groove isolation structure 11 between the adjacent active area 12 on, the third of the bit line 14 It is active described in 11 both sides of fleet plough groove isolation structure described in orthographic projection also partial mulching of the part 143 in the Semiconductor substrate 10 The subregion in area 12；Along the extending direction of the wordline 13, the first part 141 of the bit line 14 with it is adjacent another described The Part III 143 of bit line 14 is located in the same interval between the two adjacent wordline 13；The Semiconductor substrate 10 has First groove 19, first groove 19 are located at 141 bottom of first part of the bit line 14；The Semiconductor substrate 10 also has There is the second groove 20, second groove 20 is located at the first part 141 of the bit line 14 and the third of the adjacent bit line 14 In the active area 12 between part 143, second groove 20 and first groove 19 are adjoining；Conductive plug 17, The conductive plug 17 has filling part 171 and the extension 172 extended laterally by the filling part 171, wherein, at least one The filling part 171 of the conductive plug 17 is located in the Semiconductor substrate 10 and in the Part III of the bit line 14 Between 143 and the first part 141 of the adjacent bit line 14, and second groove 20 is filled up, to be electrically connected by the bit line The active area 12 that 14 Part III 143 locally covers；The extension 172 by the filling part 171 bottom and side Wall is extended in the active area 12 of the lower section of Part III 143 of the bit line 14, makes the conductive plug 17 and described has Composition surface between source region 12 is on-plane surface.

As an example, the extension program according to the wordline 13, the wide cut spacing between the adjacent bit line 14 is more than institute Width dimensions of the fleet plough groove isolation structure 11 along 13 extending direction of wordline are stated, and less than 11 edge of fleet plough groove isolation structure The width dimensions of 13 extending direction of wordline add the active area 12 along the width dimensions of 13 extending direction of wordline The two and.

As an example, the bit line 14 includes laminated construction 144 and the side wall knot for being covered in 144 periphery of laminated construction Structure 145, wherein, the laminated construction 144 includes the conducting wire adhesion layer 144a, the guidewire body layer 144b that are sequentially stacked from the bottom to top And top layer dielectric layer 144c；One dielectric layer of the laminated construction 144 fills up first groove 19 and connects the shallow trench Isolation structure 11.

As an example, the material of the conducting wire adhesion layer 144a includes silicide (WSi), titanium nitride (TiN) and conductivity type The one of which of silicide, the material of the guidewire body layer 144b include tungsten (W), the material packet of the top layer dielectric layer 144c Silicon nitride comprising (SiN).

As an example, the sidewall structure 145 includes first medium layer 145a, second dielectric layer 145b and third dielectric layer 145c, wherein, the first medium layer 145a is covered on the outer wall of the laminated construction 144, and fills up first groove 19；The second dielectric layer 145b is covered on the outer wall of the first medium layer 145a, the third dielectric layer 145c coverings In on the outer wall of the second dielectric layer 145b.

As an example, the semiconductor device structure further includes isolated insulation layer 148, the isolated insulation layer 148 is located at 143 lower section of Part III of the bit line 14, and between the laminated construction 144 and the Semiconductor substrate 10.

As an example, the semiconductor device structure further includes bit line contact 146, institute's bitline contact 146 is located at described In first groove 19, and positioned at 141 lower section of first part of the bit line 14, institute's bitline contact 146 is electrically connected the lamination Structure 11 and the active area 12 positioned at 19 bottom of the first groove.Specifically, institute's bitline contact 146 be electrically connected it is described Laminated construction 11 and the drain electrode of the MOS device.

As an example, the material of institute's bitline contact 146 includes conductivity type DOPOS doped polycrystalline silicon, the isolated insulation layer 148 Material include nonconductive DOPOS doped polycrystalline silicon.

As an example, the basic material of institute's bitline contact 146 and the isolated insulation layer 148 is formed in same polysilicon Layer.

As an example, the width of first groove 19 is more than the width of institute's bitline contact 146, the first medium layer 145a is filled between the side wall of institute's bitline contact 146 and first groove 19.Fill up the described of first groove 19 First medium layer 145a be used for avoid the conductive plug 17 extension 172 extend to institute's bitline contact 146 inside and Lower section so that the extension 172 of the conductive plug 17 is relatively distant from institute's bitline contact 146, to control the extension The extending direction in portion 172, so as to increase the conductive plug 17 and the active area 12 positioned at 146 lower section of institute's bitline contact Isolation effect, both avoid misconnection short circuit.

As an example, the filled media layer 15 is located on the passivation layer 18, the material of the filled media layer 15 can To include silica (SiOx).The upper surface of the filled media layer 15 can with the upper surface flush of the bit line 14, when So, the upper surface of the filled media layer 15 can also be higher than the upper surface of the bit line 14.The shape of the filled media layer 15 Correspond to the wordline 13 into position, to separate out the drain contact region of array arrangement with the bit line 14.

As an example, the width of second groove 20 and the filling part 171 is of same size.Second groove 20 Contribute to the formation of the extension 172.

As an example, the shape in 172 section of extension includes having and the bottom of the filling part 171 and side wall phase The arc of connection.Certainly, in other examples, the shape in 172 section of extension can also be set as according to actual needs Other arbitrary shapes.

As an example, the bottom of the filling part 171 of the conductive plug 17 is not less than the bottom of first groove 19, and Not higher than the top surface of the active area 12.

In conclusion the present invention provides a kind of semiconductor device structure and its manufacturing method, the semiconductor device structure Including：Semiconductor substrate is formed with several fleet plough groove isolation structures, the fleet plough groove isolation structure in the Semiconductor substrate Several active areas being intervally arranged are isolated in the Semiconductor substrate；The wordline of several parallel intervals arrangement, is located at In the Semiconductor substrate, and the extending direction of the extending direction of the wordline and the active area is into first angle；Several The bit line of parallel interval arrangement, in the Semiconductor substrate；The extension of the extending direction of the bit line and the active area Direction is into second angle, and with the direction of wordline extension into third angle；Each bit line has first part, second Part and Part III；Wherein, the first part of the bit line is folded between the adjacent wordline and with the active area Region on；The second part of the bit line is located at the upper of the wordline；The Part III of the bit line is located at the adjacent word Between line, and on the region that is folded of the fleet plough groove isolation structure between the adjacent active area, the third of the bit line The portion of active area described in fleet plough groove isolation structure both sides described in the orthographic projection also partial mulching of part on the semiconductor substrate Subregion；Along the extending direction of the wordline, the first part of the bit line and the Part III of adjacent another bit line It is located in the same interval between the two adjacent wordline；Conductive plug, the conductive plug include filling part and by described The extension that filling part extends laterally, wherein, the filling part of at least one conductive plug is located at the Semiconductor substrate Above and between the Part III of the bit line and the first part of the adjacent bit line, with electrical connection by the third of the bit line The active area that part locally covers；The extension is extended to the of the bit line by the bottom and side wall of the filling part In the active area below three parts, it is on-plane surface to make the composition surface between the conductive plug and the active area.This hair In bright semiconductor device structure, extended to by being added below the conductive plug filling part between bit line positioned at bit line The extension in active area below Part III, can greatly increase the contact area of conductive plug and active area, effectively change The resistance of kind conductive plug, and then improve the yield and performance of semiconductor devices.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as Into all equivalent modifications or change, should by the present invention claim be covered.

Claims

1. a kind of semiconductor device structure, which is characterized in that the semiconductor device structure includes：

Semiconductor substrate is formed with several fleet plough groove isolation structures, and the fleet plough groove isolation structure is in the Semiconductor substrate Inside isolate several active areas being intervally arranged；

The wordline of several parallel intervals arrangement, in the Semiconductor substrate, the extending direction of the wordline has with described The extending direction of source region is into first angle；

The bit line of several parallel intervals arrangement, in the Semiconductor substrate；The extending direction of the bit line has with described The extending direction of source region is into second angle, and with the direction of wordline extension into third angle；Each bit line has the A part, second part and Part III；Wherein, the first part of the bit line between the adjacent wordline and with it is described On the region that active area is folded；The second part of the bit line is located in the wordline；The Part III of the bit line is located at phase On between the adjacent wordline and region that the fleet plough groove isolation structure between the adjacent active area is folded, the bit line Part III orthographic projection also partial mulching on the semiconductor substrate described in it is active described in fleet plough groove isolation structure both sides The subregion in area；Along the extending direction of the wordline, the of the first part of the bit line and adjacent another bit line Three parts are located in the same interval between the two adjacent wordline；

Conductive plug has filling part and the extension extended laterally by the filling part, wherein, at least one conductive plugs The filling part of plug be located in the Semiconductor substrate and the bit line Part III and the adjacent bit line first Between part, to be electrically connected the active area locally covered by the Part III of the bit line；The extension is filled out by described It fills the bottom in portion and side wall is extended in the active area below the Part III of the bit line, make the conductive plug and institute It is on-plane surface to state the composition surface between active area.

2. semiconductor device structure according to claim 1, it is characterised in that：According to the extending direction of the wordline, phase Wide cut spacing between the adjacent bit line is more than width dimensions of the fleet plough groove isolation structure along the wordline extending direction, and Extend less than the fleet plough groove isolation structure along the width dimensions of the wordline extending direction with the active area along the wordline The two of the width dimensions in direction and.

3. semiconductor device structure according to claim 1, it is characterised in that：The bit line includes laminated construction and covering Sidewall structure in laminated construction periphery, wherein, the conducting wire that the laminated construction includes being sequentially stacked from the bottom to top sticks Layer, guidewire body layer and top layer dielectric layer；The semiconductor device structure further includes isolated insulation layer, the isolated insulation layer position Below the Part III of the bit line, and between the laminated construction and the Semiconductor substrate.

4. semiconductor device structure according to claim 3, it is characterised in that：The material of the conducting wire adhesion layer include by The one of which of tungsten silicide, titanium nitride and conduction type silicon compound, the material of the guidewire body layer include tungsten, the top layer medium The material of layer includes silicon nitride.

5. semiconductor device structure according to claim 3, it is characterised in that：The sidewall structure includes first medium Layer, second dielectric layer and third dielectric layer, wherein, the first medium layer is covered on the outer wall of the laminated construction, described Second dielectric layer is covered on the outer wall of the first medium layer, and the third dielectric layer is covered in the outer of the second dielectric layer On wall.

6. semiconductor device structure according to claim 3, it is characterised in that：The material of the isolated insulation layer includes non- Conductivity type DOPOS doped polycrystalline silicon.

7. semiconductor device structure according to claim 3, it is characterised in that：The semiconductor device structure further includes position Line contacts, and institute's bitline contact is located at below the first part of the bit line, and institute's bitline contact is electrically connected the laminated construction With the active area.

8. semiconductor device structure according to claim 7, it is characterised in that：The material of institute's bitline contact includes conduction Type DOPOS doped polycrystalline silicon.

9. semiconductor device structure according to claim 7, it is characterised in that：Institute's bitline contact and the isolated insulation The basic material of layer is formed in same polysilicon layer.

10. semiconductor device structure according to claim 7, it is characterised in that：Corresponding to the first part of the bit line, The Semiconductor substrate has groove, by the etching removal part active area and the part fleet plough groove isolation structure institute shape Into the width of the groove is more than the width of institute's bitline contact, an at least dielectric layer for the sidewall structure of the bit line It fills up the groove and connects the fleet plough groove isolation structure.

11. semiconductor device structure according to claim 10, it is characterised in that：The bottom of the filling part of the conductive plug Portion is not less than the bottom of the groove, and not higher than the top surface of the active area.

12. semiconductor device structure according to any one of claim 1 to 11, it is characterised in that：The extension is cut The shape in face is included with the arc being connected with the bottom of the filling part and side wall.

13. semiconductor device structure according to any one of claim 1 to 11, it is characterised in that：The extension is certainly The size that the bottom of the filling part and side wall extend into the active area is between 0.1nm~50nm.

A kind of 14. manufacturing method of semiconductor device structure, which is characterized in that the manufacturing method packet of the semiconductor device structure Include following steps：

1) semi-conductive substrate is provided, several fleet plough groove isolation structures, the shallow trench are formed in the Semiconductor substrate Isolation structure isolates several active areas being intervally arranged in the Semiconductor substrate；

2) in formed in the Semiconductor substrate several parallel intervals arrangement wordline, the extending direction of the wordline with it is described The extending direction of active area is into first angle；

3) bit line of several parallel intervals arrangement is formed in the upper surface of the Semiconductor substrate；The extending direction of the bit line Extending direction with the active area is into second angle, and with the direction of wordline extension into first angle；Each institute's rheme Line has first part, second part and Part III；Wherein, the first part of the bit line is between the adjacent wordline And on the region being folded with the active area；The second part of the bit line is located in the wordline；The third portion of the bit line Divide between the adjacent wordline, and the region that the fleet plough groove isolation structure between the adjacent active area is folded On, fleet plough groove isolation structure two described in the orthographic projection also partial mulching of the Part III of the bit line on the semiconductor substrate The subregion of active area described in side；Along the extending direction of the wordline, the first part of the bit line and adjacent another institute The Part III of rheme line is located in the same interval between the two adjacent wordline；

4) in forming filled media layer in the Semiconductor substrate, the filled media layer is covered in the wordline and fills up phase Gap between the adjacent bit line；

5) contact hole is formed in the filled media layer between the bit line, the contact hole includes filling hole and by institute The elongated hole that contact hole extends laterally is stated, wherein, the filling hole of at least one contact hole is located at the of a bit line Between the first part of three parts and another bit line adjacent thereto, to be electrically connected by the Part III part of the bit line The active area covered；The elongated hole is extended to by the bottom and side wall in the filling hole under the Part III of the bit line In the active area of side, it is on-plane surface to make the composition surface between the filling hole and the active area；

6) in filling conductive material in the contact hole, the conductive material fills up the contact hole to form the conductive plugs Plug.

15. the manufacturing method of semiconductor device structure according to claim 14, it is characterised in that：Step 3) is including as follows Step：

3-1) in formed in the Semiconductor substrate several parallel intervals arrangement laminated construction, the laminated construction include by Under the supreme conducting wire adhesion layer being sequentially stacked, guidewire body layer and top layer dielectric layer；The extending direction of the laminated construction and institute The extending direction of active area is stated into second angle, and with the direction of wordline extension into third angle；

16. the manufacturing method of semiconductor device structure according to claim 15, it is characterised in that：Step 3-1) it goes back before Include the following steps：

Etching removes the part active area and the part fleet plough groove isolation structure to form groove, the groove and step 5) The filling hole of middle formation is adjoining；

In forming polysilicon layer on the bottom portion of groove and the Semiconductor substrate, the polysilicon layer defines the lamination knot The position of structure and shape；The part that the polysilicon layer is located at the bottom portion of groove is that the bit line is connected with the active area The bit line contact connect；

The part polysilicon layer corresponded to below the Part III of the bit line is doped to form isolated insulation layer.

17. the manufacturing method of semiconductor device structure according to claim 16, it is characterised in that：Step 3-2) include Following steps：

The first medium layer of the covering laminated construction outer wall 3-2-1) is formed in the periphery of the laminated construction；

18. the manufacturing method of semiconductor device structure according to claim 17, it is characterised in that：Step 3-2-1) in, The first medium layer fills up the groove, while forming the first medium layer, in exposed upper of the Semiconductor substrate Surface forms passivation layer.

19. the manufacturing method of semiconductor device structure according to claim 14, it is characterised in that：It is formed in step 3) In the bit line, according to the extending direction of the wordline, wide cut spacing between the adjacent bit line be more than the shallow trench every From width dimensions of the structure along each wordline extending direction, and it is less than the fleet plough groove isolation structure along the wordline extension side To width dimensions and the active area along the width dimensions of the wordline extending direction the two and.

20. the manufacturing method of the semiconductor device structure according to any one of claim 14 to 19, it is characterised in that：Step It is rapid 5) to include the following steps：

5-1) removal between the bit line filled media layer, positioned at a bit line Part III with it is adjacent thereto Another bit line first part between the part active area and the part fleet plough groove isolation structure to be formed State filling hole；

5-2) continue to etch from the bottom in the filling hole and side wall described active below the Part III of the bit line Area, to form the elongated hole.

21. the manufacturing method of semiconductor device structure according to claim 20, it is characterised in that：Step 5-2) in, it adopts The elongated hole is formed with isotropic etching technique.

22. the manufacturing method of semiconductor device structure according to claim 21, it is characterised in that：Isotropic etching work The elongated hole formed in skill is from the bottom in the filling hole and the size that extends into the active area of side wall between 0.1nm ~50nm.

23. a kind of semiconductor device structure, which is characterized in that the semiconductor device structure includes：

The bit line of several parallel intervals arrangement, in the Semiconductor substrate；The extending direction of the bit line has with described The extending direction of source region is into second angle, and with the direction of wordline extension into third angle；Each bit line has the A part, second part and Part III；Wherein, the first part of the bit line between the adjacent wordline and with it is described On the region that active area is folded；The second part of the bit line is located in the wordline；The Part III of the bit line is located at phase On between the adjacent wordline and region that the fleet plough groove isolation structure between the adjacent active area is folded, the bit line Part III orthographic projection also partial mulching on the semiconductor substrate described in it is active described in fleet plough groove isolation structure both sides The subregion in area；Along the extending direction of the wordline, the of the first part of the bit line and adjacent another bit line Three parts are located in the same interval between the two adjacent wordline；The Semiconductor substrate has the first groove, positioned at described The first part bottom of bit line；The Semiconductor substrate also have the second groove, positioned at the bit line first part with it is adjacent In the active area between the Part III of the bit line, second groove and first groove are adjoining；

Conductive plug has filling part and the extension extended laterally by the filling part, wherein, at least one conductive plugs The filling part of plug be located in the Semiconductor substrate and the bit line Part III and the adjacent bit line first Between part, and second groove is filled up, to be electrically connected the active area locally covered by the Part III of the bit line； The extension is extended to by the bottom and side wall of the filling part in the active area below the Part III of the bit line, It is on-plane surface to make the composition surface between the conductive plug and the active area.

24. semiconductor device structure according to claim 23, it is characterised in that：According to the extending direction of the wordline, Wide cut spacing between the adjacent bit line is more than width dimensions of the fleet plough groove isolation structure along the wordline extending direction, And prolong less than the fleet plough groove isolation structure along the width dimensions of the wordline extending direction with the active area along the wordline Stretch the width dimensions in direction the two and.

25. semiconductor device structure according to claim 23, it is characterised in that：The bit line includes laminated construction and covers The sidewall structure of the laminated construction periphery is placed on, wherein, the conducting wire that the laminated construction includes being sequentially stacked from the bottom to top sticks Attached layer, guidewire body layer and top layer dielectric layer.

26. semiconductor device structure according to claim 25, it is characterised in that：One dielectric layer of the laminated construction is filled out Full first groove simultaneously connects the fleet plough groove isolation structure.

27. semiconductor device structure according to claim 26, it is characterised in that：The sidewall structure includes first medium Layer, second dielectric layer and third dielectric layer, wherein, the first medium layer is covered on the outer wall of the laminated construction, and fill out Full first groove, the second dielectric layer are covered on the outer wall of the first medium layer, the third dielectric layer covering In on the outer wall of the second dielectric layer.

28. semiconductor device structure according to claim 25, it is characterised in that：The semiconductor device structure further includes Isolated insulation layer, the isolated insulation layer are located at below the Part III of the bit line, and positioned at the laminated construction with it is described Between Semiconductor substrate.

29. semiconductor device structure according to claim 28, it is characterised in that：The semiconductor device structure further includes Bit line contact, institute's bitline contact are located in first groove, and below the first part of the bit line, institute's bitline contact It is electrically connected the laminated construction and the active area positioned at first bottom portion of groove.

30. semiconductor device structure according to claim 29, it is characterised in that：The material of institute's bitline contact is included and is led Electric type DOPOS doped polycrystalline silicon, the material of the isolated insulation layer include nonconductive DOPOS doped polycrystalline silicon.

31. semiconductor device structure according to claim 30, it is characterised in that：Institute's bitline contact and the isolation are exhausted The basic material of edge layer is formed in same polysilicon layer.

32. semiconductor device structure according to claim 23, it is characterised in that：The bottom of the filling part of the conductive plug Portion is not less than the bottom of first groove, and not higher than the top surface of the active area.

33. the semiconductor device structure according to any one of claim 23 to 32, it is characterised in that：The extension is cut The shape in face is included with the arc being connected with the bottom of the filling part and side wall.

34. the semiconductor device structure according to any one of claim 23 to 32, it is characterised in that：The extension is certainly The size that the bottom of the filling part and side wall extend into the active area is between 0.1nm~50nm.