CN108228242B

CN108228242B - Configurable and flexible instruction scheduler

Info

Publication number: CN108228242B
Application number: CN201810118967.8A
Authority: CN
Inventors: 洪振洲; 李庭育; 陈育鸣; 魏智汎
Original assignee: Jiangsu Hua Cun Electronic Technology Co Ltd
Current assignee: Jiangsu Hua Cun Electronic Technology Co Ltd
Priority date: 2018-02-06
Filing date: 2018-02-06
Publication date: 2020-02-07
Anticipated expiration: 2038-02-06
Also published as: WO2019153683A1; CN108228242A

Abstract

The invention discloses a configurable and elastic instruction scheduler, which comprises a central microprocessor, a memory, a first hardware module and a second hardware module, wherein the central microprocessor is respectively connected with the memory, the first hardware module and the second hardware module through buses, an instruction queue unit and an instruction queue setting unit are arranged in the memory, and the instruction queue setting unit is respectively connected with the first hardware module and the second hardware module.

Description

Configurable and flexible instruction scheduler

Technical Field

The invention relates to the technical field of instruction scheduling, in particular to a configurable and flexible instruction scheduler.

Background

Instruction scheduling is a technique for instruction parallel execution, and a compiler or machine hardware increases the number of machine-executed instructions per beat by adjusting the order of the instructions, where the beat is a clock cycle of the machine-executed instructions that the compiler simulates when compiling a source program. In the prior art, a table scheduling algorithm is usually adopted to implement instruction scheduling, and a candidate instruction queue is usually adopted. Specifically, when instruction scheduling is performed, a data dependency graph is constructed for instructions to be scheduled, the data dependency graph is composed of a plurality of nodes, each node represents one instruction, and the data dependency graph can be used for representing the dependency relationship between the instructions. The priority of each instruction is then calculated, and the instructions in the data dependency graph are then scheduled beat-by-beat. Instruction scheduling is an efficient means for compilers to exploit the potential instruction-level parallelism of programs. The method improves the number of instructions which can be executed by a target machine in a period by readjusting the instruction sequence on the premise of not changing the program semantics and meeting the correlation and resource dependency of the target machine. Instruction scheduling is a key technique of modern high-performance compilers, and determines the relative execution order of operations, specific execution time and hardware resources used. From the viewpoint of code block division, instruction scheduling can be divided into local instruction scheduling and global instruction scheduling, where local instruction scheduling refers to instruction scheduling within a basic block, and global scheduling refers to instruction scheduling between basic blocks.

The conventional system-level single chip architecture is composed of a plurality of sub-modules including a central microprocessor, and the sub-modules are connected by an external bus, and a central controller respectively issues instructions through the external bus to complete operation, so that the performance of issuing instructions each time is low through the bus.

Disclosure of Invention

It is therefore an object of the present invention to provide a configurable and flexible instruction scheduler to solve the above-mentioned problems.

In order to achieve the purpose, the invention provides the following technical scheme: a configurable and elastic instruction scheduler comprises a central microprocessor, a memory, a first hardware module and a second hardware module, wherein the central microprocessor is respectively connected with the memory, the first hardware module and the second hardware module through buses; the instruction queue unit comprises a first instruction queue module, a second instruction queue module, a third instruction queue module and an Nth instruction queue module, wherein N is an integer larger than 3; the instruction queue setting unit comprises a first instruction queue setting module, a second instruction queue setting module, a third instruction queue setting module and an Mth instruction queue setting module, wherein M is an integer larger than 3; the first instruction queue setting module is connected with the first instruction queue module, the second instruction queue setting module is connected with the second instruction queue module, the third instruction queue setting module is connected with the third instruction queue module, and the Mth instruction queue setting module is connected with the Nth instruction queue module.

Compared with the prior art, the invention has the beneficial effects that: in the invention, the central microprocessor can give each submodule more flexible instruction length and instruction queue depth, so that the microprocessor can issue instructions more easily and independently.

Drawings

Fig. 1 is a schematic diagram of the structure of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a configurable and elastic instruction scheduler comprises a central microprocessor 1, a memory 2, a first hardware module 3 and a second hardware module 4, wherein the central microprocessor 1 is respectively connected with the memory 2, the first hardware module 3 and the second hardware module 4 through buses, an instruction queue unit 5 and an instruction queue setting unit 6 are arranged in the memory 2, and the instruction queue setting unit 6 is respectively connected with the first hardware module 3 and the second hardware module 4.

In the invention, an instruction queue unit 5 comprises a first instruction queue module 7, a second instruction queue module 8, a third instruction queue module 9 and an Nth instruction queue module, wherein N is an integer more than 3; the instruction queue setting unit 6 comprises a first instruction queue setting module 10, a second instruction queue setting module 11, a third instruction queue setting module 12 and an Mth instruction queue setting module, wherein M is an integer greater than 3; the first instruction queue setting module 10 is connected with the first instruction queue module 7, the second instruction queue setting module 11 is connected with the second instruction queue module 8, the third instruction queue setting module 12 is connected with the third instruction queue module 9, and the Mth instruction queue setting module is connected with the Nth instruction queue module.

The microprocessor gives orders to the order central control module via the external bus, the orders corresponding to different modules are written into the respective defined addresses in the memory, each order queue corresponds to different modules in the system and has different meanings, the order length and the number are all set in the order queue setting register, and after the microprocessor can give out a plurality of orders at one time, the microprocessor informs the queue how many orders are written for the external hardware sub-module to execute in the way of writing the register. Each hardware submodule knows how many instructions need to be processed and grabs the instructions through an external bus according to instruction queue setting signals, once the grabbing is completed, the hardware submodule informs a microprocessor through a bus rewriting register, and how many instructions are grabbed, so that the use of the instruction memory space can be optimized, and the instruction queue depth can be adjusted according to actual hardware requirements, and flexibility is attached. Similarly, the external hardware submodule may write commands up for execution by the microprocessor in this manner.

In the invention, the central microprocessor can give each submodule more flexible instruction length and instruction queue depth, so that the microprocessor can issue instructions more easily and independently.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A configurable and flexible instruction scheduler, comprising: the system comprises a central microprocessor (1), a memory (2), a first hardware module (3) and a second hardware module (4), wherein the central microprocessor (1) is respectively connected with the memory (2), the first hardware module (3) and the second hardware module (4) through buses, an instruction queue unit (5) and an instruction queue setting unit (6) are arranged in the memory (2), and the instruction queue setting unit (6) is respectively connected with the first hardware module (3) and the second hardware module (4); the instruction queue unit (5) comprises a first instruction queue module (7), a second instruction queue module (8), a third instruction queue module (9) and an Nth instruction queue module, wherein N is an integer greater than 3; the instruction queue setting unit (6) comprises a first instruction queue setting module (10), a second instruction queue setting module (11), a third instruction queue setting module (12) and an Mth instruction queue setting module, wherein M is an integer larger than 3; the first instruction queue setting module (10) is connected with the first instruction queue module (7), the second instruction queue setting module (11) is connected with the second instruction queue module (8), the third instruction queue setting module (12) is connected with the third instruction queue module (9), and the Mth instruction queue setting module is connected with the Nth instruction queue module.