CN108206142B - Bonding alignment precision detection method and semiconductor device - Google Patents
Bonding alignment precision detection method and semiconductor device Download PDFInfo
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- CN108206142B CN108206142B CN201611187333.5A CN201611187333A CN108206142B CN 108206142 B CN108206142 B CN 108206142B CN 201611187333 A CN201611187333 A CN 201611187333A CN 108206142 B CN108206142 B CN 108206142B
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Abstract
The invention provides a method for detecting bonding alignment precision and a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the first alignment mark is annular in shape; providing a second device wafer, and forming a second alignment mark on the second device wafer; forming a dielectric layer to cover the surface of the second device wafer, on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark; forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer; bonding the first device wafer and the second device wafer, aligning and bonding the first alignment mark and the virtual bonding layer, and enabling the second alignment mark to be opposite to the blank area surrounded by the first alignment mark; and imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of bonding.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for detecting bonding alignment precision and a semiconductor device.
Background
Wafer bonding technology is widely used in the fields of three-dimensional integrated circuits (3D ICs), Micro Electro Mechanical Systems (MEMS), CMOS Image Sensors (CIS), Silicon On Insulator (SOI), and the like. The bonding between the device wafer and the bare silicon wafer does not usually require high alignment accuracy, and the alloy bonding between the device wafer and the device wafer usually requires high alignment accuracy due to the structural and electrical interconnection of the devices. With the development of semiconductor technology, the complexity and integration of 3D devices will be higher and higher, and the requirement for bonding alignment accuracy will be higher and higher. An infrared light source is usually used to penetrate through the wafer to identify the detection pattern with alignment accuracy, and the method limits the detection pattern film layer. The characteristics of alloy bonding can change the bonding interface in the process, so that the quality of the pattern is reduced.
Under the present circumstances, it is difficult to meet the increasing quality requirement of the 3D device for the alignment precision of the bonding process, and therefore, a new method for detecting the alignment precision of the bonding process needs to be provided to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the present invention provides a method for detecting bonding alignment accuracy, where the method includes:
providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the first alignment mark is annular in shape;
providing a second device wafer, and forming a second alignment mark on the second device wafer;
forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, wherein the surface of the dielectric layer is flush with the surface of the second alignment mark;
forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;
bonding the first device wafer and the second device wafer, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is opposite to a blank area surrounded by the first alignment mark;
and imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of bonding.
Further, the virtual bonding layer is composed of a plurality of virtual bonding points which are separated and independent from each other.
Further, the size of each virtual bonding point is smaller than the loop line width of the first alignment mark.
Further, each of the virtual bond sites is rectangular in shape.
Furthermore, the side length range of the rectangle is 0.5-5 mu m.
Further, the first alignment mark has a rectangular ring shape.
Further, the loop line width of the first alignment mark is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm.
Further, a first device layer is formed on the first device wafer, the first device layer and the first alignment mark are located on the same surface of the first device wafer, and the first device layer is located on one side of the first alignment mark, wherein the step of forming the first alignment mark includes:
forming a top metal material layer on the surface of the first device wafer, wherein the top metal material layer covers the first device layer;
patterning the top metal material layer to form the first alignment mark and a top metal layer on the first device layer.
Further, the material of the first alignment mark includes aluminum.
Further, a second device layer is formed on the second device wafer, the second device layer and the second alignment mark are located on the same surface of the second device wafer, and the second device layer is located on one side of the second alignment mark, wherein the step of forming the second alignment mark includes:
forming an interconnection metal material layer on the surface of the second device wafer, wherein the interconnection metal material layer covers the second device layer;
and patterning the interconnection metal material layer to form the second alignment mark and an interconnection metal layer positioned above the second device layer, wherein the interconnection metal layer is electrically connected with the second device layer.
Further, the step of forming a dummy bonding layer on the dielectric layer around the second alignment mark includes:
depositing a bonding material layer on the dielectric layer;
and patterning the bonding material layer to form the virtual bonding layer and a bonding layer on the interconnection metal layer.
Further, the step of bonding the first device wafer and the second device wafer further includes:
and aligning the first device layer and the second device layer for bonding, wherein the top metal layer and the bonding layer are bonded.
Further, the material of the dummy bonding layer includes Ge.
Further, after the first device wafer and the second device wafer are bonded, the method further comprises the step of thinning the first device wafer from the back side of the first device wafer.
Further, an infrared light source is used for irradiating and imaging the pattern formed by the first alignment mark and the second alignment mark from the back side of the first device wafer so as to detect the alignment accuracy of bonding.
Further, the density of the virtual bonding points included in the virtual bonding layer takes the bonding force requirement of the whole device wafer on the non-critical area as a reference standard, and the density of the virtual bonding points enables the bonding force after the first alignment mark and the virtual bonding layer are bonded to be 30% -70% of the bonding force requirement of the whole device wafer on the non-critical area.
Further, the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is greater than a constant, where the constant is the sum of the bonding precision specification, the width of the bonding interface affecting the graphic boundary, and the buffer width of the virtual bonding layer.
Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.
The second embodiment of the present invention provides a semiconductor device, including:
a first device wafer on which a first alignment mark is formed, wherein the first alignment mark has a ring shape;
a second device wafer having a second alignment mark formed thereon;
forming a dielectric layer on the surface of the second device wafer on which the second alignment mark is formed, wherein the surface of the dielectric layer is flush with the surface of the second alignment mark;
forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;
and bonding the first device wafer and the second device wafer, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is opposite to a blank area surrounded by the first alignment mark.
Further, the virtual bonding layer is composed of a plurality of virtual bonding points which are separated and independent from each other.
Further, the density of the virtual bonding points included in the virtual bonding layer takes the bonding force requirement of the whole device wafer on the non-critical area as a reference standard, and the density of the virtual bonding points enables the bonding force after the first alignment mark and the virtual bonding layer are bonded to be 30% -70% of the bonding force requirement of the whole device wafer on the non-critical area.
Further, the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is greater than a constant, where the constant is the sum of the bonding precision specification, the width of the bonding interface affecting the graphic boundary, and the buffer width of the virtual bonding layer.
Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.
The detection method is applied to the indirect alignment of alloy bonding, and the original alignment image of Al-Ge direct bonding is changed into an alignment pattern of indirect alignment of a first alignment mark and a second alignment mark by introducing the indirect second alignment mark so as to improve the pattern quality. And by adding the virtual bonding layer pattern at the designated position according to the specific design rule, the whole detection pattern area can be bonded, the bonding quality is ensured, and the application range is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1D are schematic structural diagrams of devices corresponding to the implementation of relevant steps of a conventional bonding alignment accuracy detection method;
fig. 2A-2H are schematic structural diagrams of a device obtained by relevant steps of a bonding alignment precision detection method according to an embodiment of the present invention, wherein fig. 2G is a partial top view in an alignment detection mark region;
FIG. 2I is a diagram illustrating the effect of infrared detection according to an embodiment of the present invention;
fig. 3 shows a flowchart of a method for detecting bonding alignment accuracy according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Next, a method for detecting the bonding alignment accuracy in the prior art is briefly described with reference to fig. 1A to 1D, wherein fig. 1A to 1D are schematic structural diagrams of devices corresponding to the implementation of relevant steps of the method for detecting the bonding alignment accuracy in the prior art.
First, as shown in fig. 1A, a first device wafer 100 is provided, and an Al alignment mark 101 is formed on a surface of the first device wafer 100 intended to be bonded.
Next, as shown in fig. 1B, a second device wafer 200 is provided, and a Ge alignment mark 102 is formed on a surface of the second device wafer 200, where bonding is to be performed, where a size of the Ge alignment mark is smaller than a size of the Al alignment mark 101.
Thereafter, as shown in fig. 1C, the first device wafer 100 and the second device wafer 200 are bonded to each other, wherein the Al alignment mark 101 and the Ge alignment mark 102 are bonded to each other.
Finally, the pattern of the Ge alignment mark is identified on the background of the Al alignment mark by utilizing an infrared light source, and the obtained alignment pattern 10 is shown in FIG. 1D.
The existing detection method is difficult to meet the increasing quality requirement of 3D devices on the alignment precision of the bonding process.
Example one
In order to solve the above technical problem, the present invention provides a method for detecting bonding alignment accuracy, as shown in fig. 3, which mainly includes the following steps:
step S1, providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the first alignment mark has a ring shape;
step S2, providing a second device wafer, and forming a second alignment mark on the second device wafer;
step S3, forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark;
step S4, forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;
step S5, bonding the first device wafer and the second device wafer, wherein the first alignment mark and the dummy bonding layer are aligned and bonded, and the second alignment mark is opposite to the blank region surrounded by the first alignment mark;
step S6, imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of the bonding.
The detection method is applied to the indirect alignment of alloy bonding, and the original alignment image of Al-Ge direct bonding is changed into an alignment pattern of indirect alignment of a first alignment mark and a second alignment mark by introducing the indirect second alignment mark so as to improve the pattern quality. And by adding the virtual bonding layer pattern at the designated position according to the specific design rule, the whole detection pattern area can be bonded, the bonding quality is ensured, and the application range is improved.
The method for detecting bonding alignment accuracy according to the present invention is described in detail with reference to fig. 2A-2I, wherein fig. 2A-2H are schematic structural diagrams of a device obtained by relevant steps of the method for detecting bonding alignment accuracy according to an embodiment of the present invention, and fig. 2H is a partial top view in an alignment detection mark region; fig. 2I shows an infrared detection effect diagram according to an embodiment of the present invention.
First, as shown in fig. 2A, a first device wafer 300 is provided, a first device layer 301 is formed on the first device wafer 300, a first alignment mark 3021 is formed on the first device wafer 300, a top metal layer 3022 is formed on the first device layer 301, the first device layer 301 and the first alignment mark 3021 are located on the same surface of the first device wafer 300, and the first device layer 301 is located on one side of the first alignment mark 3021, wherein the first alignment mark 3021 is annular in shape.
Specifically, the material of the first device wafer 300 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
The first device layer formed on the first device wafer may be any device known to those skilled in the art, such as a CMOS device, a radio frequency device, a capacitor, a resistor, a MEMS device, a CIS chip, or a data processing chip, etc. The first device layer can also comprise interconnection lines composed of multiple interconnection metal layers and through holes, and the interconnection lines are used for realizing the electrical connection between the devices in the first device layer and other devices or circuits.
The material of the first alignment mark may be any metal material, and in this embodiment, the material of the first alignment mark may be aluminum.
The first alignment mark 3021 is exemplarily shaped as a ring, and specifically, may be shaped as a rectangular ring, a circular ring, an elliptical ring, a polygonal ring, or another suitable ring, and in this embodiment, it is preferable that the first alignment mark 3021 is shaped as a rectangular ring, for example, a square ring.
Alternatively, the loop line width of the first alignment mark 3021 is larger than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm, which is well known as an example, and can be set appropriately according to actual process requirements.
Wherein the first alignment mark is located in a non-critical region at one side of a device region where the first device layer is formed, the region generally having no actual function.
In one example, the method of forming the first alignment mark 3021 and the top metal layer 3022 includes the following steps a1 and a 2:
first, step a1 is performed to form a top metal material layer on the surface of the first device wafer 300, wherein the top metal material layer covers the first device layer.
Next, the top metal material layer is patterned to form the first alignment mark 3021 and a top metal layer 3022 on the first device layer 301.
Specifically, a patterned photoresist layer may be formed on the top metal material layer by using a photolithography process, the patterned photoresist layer defines the pattern position and size of the first alignment mark 3021 and the top metal layer 3022 to be formed, the top metal material layer is etched by using the patterned photoresist layer as a mask to form the first alignment mark 3021 and the top metal layer 3022, a common wet etching or dry etching process may be used, which is not specifically limited herein, and finally the photoresist layer is removed.
The thickness of the top metallic material layer may be 500nm to 2000nm, or other suitable thickness.
Optionally, top metal layer 3022 is electrically connected to the first device layer below it.
In which, this step can be directly implemented by using a conventional process for manufacturing an interconnection line of a semiconductor device, which only needs to use a mask including the pattern of the first alignment mark 3021, thereby not increasing any additional production cost.
Next, as shown in fig. 2B, a second device wafer 400 is provided, a second device layer is further formed on the second device wafer 400, a second alignment mark 4021 is formed on the second device wafer 400, the second device layer 401 and the second alignment mark 4021 are located on the same surface of the second device wafer 400, and the second device layer 401 is located on one side of the second alignment mark 4021.
Specifically, the material of the second device wafer 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
The second device layer formed on the second device wafer may be any device known to those skilled in the art, such as a CMOS device, a radio frequency device, a capacitor, a resistor, a MEMS device, a CIS chip, or a data processing chip. The second device layer can also comprise interconnection lines composed of multiple interconnection metal layers and through holes, and the interconnection lines are used for realizing the electrical connection between the devices in the second device layer and other devices or circuits.
The material of the second alignment mark 4021 may be any metal material, such as aluminum or copper.
Further, the shape of the second alignment mark 4021 may be any suitable shape, for example, it may be rectangular, circular, elliptical, or polygonal.
The size of the second alignment mark 4021 may be designed as a pattern smaller than the size of the inner edge of the first alignment mark, so that the second alignment mark 4021 can be opposed to and smaller than the blank region surrounded by the first alignment mark after alignment bonding.
In one example, the step of forming the second alignment mark 4021 includes the following steps B1 to B2:
first, step B1 is performed to form a layer of interconnect metal material on the surface of the second device wafer 400, where the layer of interconnect metal material covers the second device layer 401.
The interconnection metal material layer may be a film layer used for making any one of interconnection lines electrically connected to the second device layer 401, or may be a top interconnection metal layer of the interconnection lines, wherein the top interconnection metal layer is preferred.
May be formed using techniques that may be used by low pressure chemical vapor deposition (L PCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), electrochemical plating, Metal Organic Chemical Vapor Deposition (MOCVD), and atomic layer deposition (a L D), or other advanced deposition techniques.
Next, step B2 is performed to pattern the interconnection metal material layer to form the second alignment mark 4021 and an interconnection metal layer 4022 located above the second device layer 401, wherein the interconnection metal layer 4022 is electrically connected to the second device layer 401.
Specifically, a patterned photoresist layer may be formed on the top metal material layer by using a photolithography process, the patterned photoresist layer defines the pattern position and size of a second alignment mark and an interconnection metal layer to be formed, the interconnection metal material layer is etched by using the patterned photoresist layer as a mask to form the second alignment mark and the interconnection metal layer, a common wet etching or dry etching process may be used, and the photoresist layer is removed finally.
Next, as shown in fig. 2C, a dielectric layer 403 is formed to cover the surface of the second device wafer 400 where the second alignment mark 4021 is formed, and the surface of the dielectric layer 403 is flush with the surface of the second alignment mark 4021, and further, the dielectric layer 403 also covers the second device wafer 400 outside the interconnection metal layer 4022.
The dielectric layer 403 may be made of, for example, SiO2Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon carbonitride (SiCN), or the like. Alternatively, a film in which a SiCN thin film is formed on fluorocarbon (CF) or the like may be used. The fluorocarbon compound contains fluorine (F) and carbon (C) as main components. As the fluorocarbon, a fluorocarbon having an amorphous (non-crystalline) structure may be used. The dielectric layer 403 may have a porous structure such as carbon-doped silicon oxide (SiOC).
A dielectric layer may be deposited by a conventional deposition method, such as chemical vapor deposition, to cover the second device wafer 400, and a planarization process, such as a chemical mechanical polishing process, may be used to planarize the dielectric layer 403, stopping on the surface of the second alignment mark 4021.
Next, as shown in fig. 2D, a dummy bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403.
In one example, the virtual bond layer is comprised of several virtual bond points 4041 that are spaced apart from each other independently.
The shape of the virtual bonding point 4041 may be any shape, such as a rectangle, a circle, a triangle, an ellipse, a polygon, or other irregular shapes, and in this embodiment, the shape of the virtual bonding point 4041 may be a rectangle.
Optionally, a plurality of dummy bonding points 4041 are arranged at regular intervals to form a lattice as the dummy bonding layer, for the subsequent bonding between the dummy bonding layer and the first alignment mark 3021.
Further, a number of dummy bond points 4041 are evenly spaced in a ring shape that is similar or even the same as the first alignment mark but different in size.
In one example, the density of the virtual bonding points 4041 included in the virtual bonding layer is based on the bonding force requirement of the whole device wafer on the non-critical area, and the density of the virtual bonding points is such that the bonding force after the first alignment mark and the virtual bonding layer are bonded is 30% to 70% of the bonding force requirement of the whole device wafer on the non-critical area.
Non-critical areas generally refer to areas on the device wafer outside of the device layer that do not have any actual functional role.
Further, in order to prevent the pattern of the first alignment mark 3021 from being affected when bonding is performed later, the size of each of the dummy bonding points may be smaller than the loop width of the first alignment mark.
Optionally, the following conditions may also have to be satisfied during layout design: the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is larger than a constant, and the constant is the sum of the bonding precision specification, the influence width of the bonding interface on the graph boundary and the buffer width of the virtual bonding layer.
Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.
It should be noted that the bonding accuracy specification refers to the bonding alignment accuracy allowed by the process, and the specific value thereof is set according to the actual process requirement, for example, the bonding accuracy specification may be one third of the minimum line width.
The width of the bonding interface influencing the pattern boundary refers to the width of the bonding interface influencing the pattern boundary of the first alignment mark, which is allowed by the process after the first alignment mark and the virtual bonding layer are bonded.
Optionally, the side length of the rectangular virtual bonding point 4041 may be in a range of 0.5-5 μm, and may also be appropriately adjusted according to an actual process.
Optionally, the material of the dummy bonding layer includes Ge, and may be any other material suitable for alloy bonding with metal.
In one example, the process of forming the dummy bonding layer includes the steps of:
first, a bonding material layer is deposited on the dielectric layer 403, and the bonding material layer is used for forming a virtual bonding layer and a bonding layer which is then bonded with the first device wafer.
The Ge bonding material layer may be formed using a germanium evaporation or germanium sputtering process that is conventional for microelectronic integrated circuits.
The thickness of the formed bonding material layer may be set reasonably according to the actual process, for example, the thickness may be 500 to 1500nm, and is not limited specifically herein.
Next, the bonding material layer is patterned to form the dummy bonding layer and a bonding layer 4042 on the interconnection metal layer 4022.
Patterning of the bonding material layer may be achieved using a photolithography process and an etching process, which are not specifically described herein.
Next, as shown in fig. 2E, the first device wafer 300 and the second device wafer 400 are aligned and bonded, the top metal layer and the bonding layer are bonded together, and the first alignment mark 3021 and the dummy bonding layer are aligned and bonded, wherein the second alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021.
Specifically, a suitable bonding process is selected according to the materials of the top metal layer and the bonding layer, the first alignment mark and the dummy bonding layer, for example, when the materials of the top metal layer and the first alignment mark are aluminum and the materials of the bonding layer and the dummy bonding layer are Ge, aluminum germanium eutectic bonding may be performed by using a bonding process that is conventional in the industry, the bonding temperature is controlled between 425 ℃ and 445 ℃, and aluminum and germanium are fused with each other in the temperature range so that the first device wafer 300 and the second device wafer 400 are bonded together.
After bonding, the second alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021, so that indirect alignment between the first alignment mark 4021 and the second alignment mark 3021 is achieved.
Herein, a region including the first device layer and the second device layer may be referred to as a device region 31, and a region including the first alignment mark and the second alignment mark in sequence in the device region may be referred to as an alignment detection mark region 30.
Fig. 2H shows a partial plan view of the bonded alignment detection mark region 30.
Next, as shown in fig. 2F, the first device wafer 300 is thinned from the back side of the first device wafer 300.
The back side of the first device wafer 300 is the surface opposite the side on which the first device layer is formed.
The thinning of this step may be performed using a back grinding process or chemical mechanical grinding, etc.
The thickness of the thinned first device wafer is reasonably set according to the device requirements, and is not specifically limited herein.
Next, as shown in fig. 2G, a pattern composed of the first alignment mark and the second alignment mark is imaged to detect the alignment accuracy of bonding.
Any imaging method that can be applied to the present invention may be used to obtain a pattern of the first alignment mark and the second alignment mark as a detection pattern for detecting the alignment accuracy of bonding.
In this embodiment, preferably, an infrared imaging method is used, and an infrared light source is used to irradiate and image the pattern formed by the first alignment mark and the second alignment mark from the back side of the first device wafer, so as to detect the alignment accuracy of bonding.
Fig. 2I shows an infrared detection effect diagram according to an embodiment of the present invention, from which the alignment accuracy between the first alignment mark and the second alignment mark can be measured, so as to obtain the alignment accuracy of the whole bonding process. Due to the introduction of indirect metal alignment layers (first alignment marks and second alignment marks), infrared imaging of the Al-metal pattern is adopted, and the alignment quality can be improved.
In summary, the method for detecting bonding alignment accuracy of the present invention is an indirect alignment detection method applied to alloy bonding, and introduces an indirect metal alignment mark (a first alignment mark and a second alignment mark) to change an original Al-Ge alignment image into an "Al-metal" alignment pattern, so as to improve the pattern quality. And through adding the Ge virtual bonding layer pattern at the appointed position according to the specific design rule, the whole detection pattern area can be bonded, the bonding quality is ensured, the application range is improved, and the method specifically comprises the following advantages:
1) introducing indirect metal alignment layers (a first alignment mark and a second alignment mark), and improving the alignment quality by adopting infrared imaging of an Al-metal pattern;
2) the process of the cited indirect Al alignment mark is a front-stage semiconductor manufacturing process, so that the alignment error between the indirect Al alignment mark and the Ge virtual bonding layer within 70nm can be guaranteed, the error introduction of the indirect layer is effectively controlled, and the measurement precision is guaranteed.
3) And the Ge virtual bonding layer with a specific design rule is set, so that the alignment detection mark area can be effectively bonded on the premise of ensuring the infrared imaging quality, and the process risk caused by uneven bonding is reduced.
4) The invention is realized in the process with more than one layer of interconnection lines without adding any production cost additionally.
Example two
The invention also provides a semiconductor device, and the bonding alignment accuracy of the semiconductor device can be detected by using the detection method of the first embodiment.
As shown in fig. 2G and 2H, the semiconductor device mainly includes:
a first device wafer 300, on which a first alignment mark 3021 is formed, wherein the first alignment mark 3021 has a ring shape;
a second device wafer 400, wherein a second alignment mark 4021 is formed on the second device wafer 400;
a dielectric layer 403 is formed on the surface of the second device wafer 400 where the second alignment mark 4021 is formed, and the surface of the dielectric layer 403 is flush with the surface of the second alignment mark 4021;
a virtual bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403;
the first device wafer 300 and the second device wafer 400 are bonded, wherein the first alignment mark 3021 and the dummy bonding layer 4041 are aligned and bonded, and the second alignment mark 4021 is opposite to a blank region surrounded by the first alignment mark 3021.
As an example, the semiconductor device of the present invention includes a first device wafer 300, a first device layer 301 formed on the first device wafer 300, a first alignment mark 3021 formed on the first device wafer 300, a top metal layer 3022 formed on the first device layer 301, the first device layer 301 and the first alignment mark 3021 being located on the same plane as the first device wafer 300, and the first device layer 301 being located on one side of the first alignment mark 3021, wherein the first alignment mark 3021 is annular in shape.
Specifically, the material of the first device wafer 300 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
The first device layer formed on the first device wafer may be any device known to those skilled in the art, such as a CMOS device, a radio frequency device, a capacitor, a resistor, a MEMS device, a CIS chip, or a data processing chip, etc. The first device layer can also comprise interconnection lines composed of multiple interconnection metal layers and through holes, and the interconnection lines are used for realizing the electrical connection between the devices in the first device layer and other devices or circuits.
The material of the first alignment mark may be any metal material, and in this embodiment, the material of the first alignment mark may be aluminum.
The first alignment mark 3021 is exemplarily shaped as a ring, and specifically, may be shaped as a rectangular ring, a circular ring, an elliptical ring, a polygonal ring, or another suitable ring, and in this embodiment, it is preferable that the first alignment mark 3021 is shaped as a rectangular ring, for example, a square ring.
Alternatively, the loop line width of the first alignment mark 3021 is larger than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm, which is well known as an example, and can be set appropriately according to actual process requirements.
Wherein the first alignment mark is located in a non-critical region at one side of a device region where the first device layer is formed, the region generally having no actual function.
The thickness of the first alignment mark and the top metal layer 3022 may be 500nm to 2000nm, or other suitable thicknesses.
Optionally, top metal layer 3022 is electrically connected to the first device layer below it.
Further, the semiconductor device further includes a second device wafer 400, on which a second device layer 401 is further formed, on which a second alignment mark 4021 is formed, the second device layer 401 and the second alignment mark 4021 are located on the same surface of the second device wafer 400, and the second device layer 401 is located on one side of the second alignment mark 4021.
Specifically, the material of the second device wafer 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
The second device layer formed on the second device wafer may be any device known to those skilled in the art, such as a CMOS device, a radio frequency device, a capacitor, a resistor, a MEMS device, a CIS chip, or a data processing chip. The second device layer can also comprise interconnection lines composed of multiple interconnection metal layers and through holes, and the interconnection lines are used for realizing the electrical connection between the devices in the second device layer and other devices or circuits.
The material of the second alignment mark 4021 may be any metal material, such as aluminum or copper.
Further, the shape of the second alignment mark 4021 may be any suitable shape, for example, it may be rectangular, circular, elliptical, or polygonal.
The size of the second alignment mark 4021 may be designed as a pattern smaller than the size of the inner edge of the first alignment mark, so that the second alignment mark 4021 can be opposed to and smaller than the blank region surrounded by the first alignment mark after alignment bonding.
Further, a dielectric layer 403 is formed on the surface of the second device wafer 400 where the second alignment mark 4021 is formed, and the surface of the dielectric layer 403 is flush with the surface of the second alignment mark 4021, and the dielectric layer 403 also covers the second device wafer 400 outside the interconnection metal layer 4022.
The dielectric layer 403 may be made of, for example, SiO2Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon carbonitride (SiCN), or the like. Alternatively, a film in which a SiCN thin film is formed on fluorocarbon (CF) or the like may be used. The fluorocarbon compound contains fluorine (F) and carbon (C) as main components. As the fluorocarbon, a fluorocarbon having an amorphous (non-crystalline) structure may be used. The dielectric layer 403 may have a porous structure such as carbon-doped silicon oxide (SiOC).
Further, a dummy bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403.
In one example, the virtual bond layer is comprised of several virtual bond points 4041 that are spaced apart from each other independently.
The shape of the virtual bonding point 4041 may be any shape, such as a rectangle, a circle, a triangle, an ellipse, a polygon, or other irregular shapes, and in this embodiment, the shape of the virtual bonding point 4041 may be a rectangle.
Optionally, a plurality of dummy bonding points 4041 are arranged at regular intervals to form a lattice as the dummy bonding layer, for the subsequent bonding between the dummy bonding layer and the first alignment mark 3021.
Further, a number of dummy bond points 4041 are evenly spaced in a ring shape that is similar or even the same as the first alignment mark but different in size.
In one example, the density of the virtual bonding points 4041 included in the virtual bonding layer is based on the bonding force requirement of the whole device wafer on the non-critical area, and the density of the virtual bonding points is such that the bonding force after the first alignment mark and the virtual bonding layer are bonded is 30% to 70% of the bonding force requirement of the whole device wafer on the non-critical area.
Non-critical areas generally refer to areas on the device wafer outside of the device layer that do not have any actual functional role.
Further, in order to prevent the pattern of the first alignment mark 3021 from being affected when bonding is performed later, the size of each of the dummy bonding points may be smaller than the loop width of the first alignment mark.
Optionally, the following conditions may also have to be satisfied during layout design: the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is larger than a constant, and the constant is the sum of the bonding precision specification, the influence width of the bonding interface on the graph boundary and the buffer width of the virtual bonding layer.
Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.
It should be noted that the bonding accuracy specification refers to the bonding alignment accuracy allowed by the process, and the specific value thereof is set according to the actual process requirement, for example, the bonding accuracy specification may be one third of the minimum line width.
The width of the bonding interface influencing the pattern boundary refers to the width of the bonding interface influencing the pattern boundary of the first alignment mark, which is allowed by the process after the first alignment mark and the virtual bonding layer are bonded.
Optionally, the side length of the rectangular virtual bonding point 4041 may be in a range of 0.5-5 μm, and may also be appropriately adjusted according to an actual process.
Optionally, the material of the dummy bonding layer includes Ge, and may be any other material suitable for alloy bonding with metal.
Further, the first device wafer 300 and the second device wafer 400 are bonded, wherein the top metal layer and the bonding layer are bonded together, the first alignment mark 3021 and the dummy bonding layer 4041 are aligned and bonded, and the second alignment mark 4021 is opposite to the blank region surrounded by the first alignment mark 3021.
Herein, a region including the first device layer and the second device layer may be referred to as a device region 31, and a region including the first alignment mark and the second alignment mark in sequence in the device region may be referred to as an alignment detection mark region 30.
Fig. 2H shows a partial top view of the alignment detection mark region 30.
Since the semiconductor device of the present invention includes the same first alignment mark, second alignment mark, dummy bonding layer, and the like as in the foregoing embodiment one, it is possible to perform detection of bonding accuracy using the detection method in the foregoing embodiment one, and therefore, the semiconductor device of the present invention also has the advantage of the foregoing embodiment one.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (23)
1. A method for detecting bonding alignment accuracy, the method comprising:
providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the first alignment mark is annular in shape;
providing a second device wafer, and forming a second alignment mark on the second device wafer;
forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, wherein the surface of the dielectric layer is flush with the surface of the second alignment mark;
forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;
bonding the first device wafer and the second device wafer, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is opposite to a blank area surrounded by the first alignment mark;
and imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of bonding.
2. The detection method of claim 1, wherein the virtual bond layer is comprised of a number of virtual bond sites that are spaced apart from each other independently.
3. The method of inspection as set forth in claim 2, wherein the size of each of the dummy bond sites is smaller than the loop width of the first alignment mark.
4. The method of detecting as defined in claim 2, wherein each of said virtual bond sites is rectangular in shape.
5. The detection method according to claim 4, wherein the rectangle has a side length in a range of 0.5 to 5 μm.
6. The detection method of claim 1, wherein the first alignment mark is in the shape of a rectangular ring.
7. The detection method according to claim 6, wherein the loop line width of the first alignment mark is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm.
8. The inspection method of claim 1, further comprising forming a first device layer on the first device wafer, the first device layer being on the same side of the first device wafer as the first alignment mark, and the first device layer being on a side of the first alignment mark, wherein forming the first alignment mark comprises:
forming a top metal material layer on the surface of the first device wafer, wherein the top metal material layer covers the first device layer;
patterning the top metal material layer to form the first alignment mark and a top metal layer on the first device layer.
9. The detection method of claim 1, wherein the material of the first alignment mark comprises aluminum.
10. The inspection method of claim 8, further comprising forming a second device layer on the second device wafer, the second device layer being on the same side of the second device wafer as the second alignment mark, and the second device layer being on a side of the second alignment mark, wherein forming the second alignment mark comprises:
forming an interconnection metal material layer on the surface of the second device wafer, wherein the interconnection metal material layer covers the second device layer;
and patterning the interconnection metal material layer to form the second alignment mark and an interconnection metal layer positioned above the second device layer, wherein the interconnection metal layer is electrically connected with the second device layer.
11. The method of detecting as claimed in claim 10, wherein the step of forming a dummy bonding layer on the dielectric layer around the second alignment mark comprises:
depositing a bonding material layer on the dielectric layer;
and patterning the bonding material layer to form the virtual bonding layer and a bonding layer on the interconnection metal layer.
12. The inspection method of claim 11, wherein bonding the first device wafer and the second device wafer further comprises:
and aligning the first device layer and the second device layer for bonding, wherein the top metal layer and the bonding layer are bonded.
13. The detection method of claim 1, wherein a material of the dummy bonding layer comprises Ge.
14. The inspection method of claim 1, further comprising the step of thinning the first device wafer from a back side of the first device wafer after the first device wafer and the second device wafer are bonded.
15. The inspection method of claim 1, wherein the pattern of the first alignment mark and the second alignment mark is illuminated and imaged from the back side of the first device wafer using an infrared light source to detect the alignment accuracy of the bonding.
16. The detecting method as claimed in claim 2, wherein the density of the virtual bonding points included in the virtual bonding layer is based on the bonding force requirement of the whole device wafer on the non-critical area as a reference standard, and the density of the virtual bonding points is such that the bonding force after the first alignment mark and the virtual bonding layer are bonded is 30% to 70% of the bonding force requirement of the whole device wafer on the non-critical area.
17. The inspection method of claim 1, wherein a difference between a loop line width of the first alignment mark and a width of the dummy bonding layer is greater than a constant which is a sum of a bonding precision specification, a width of a bonding interface affecting a pattern boundary, and a buffer width of the dummy bonding layer.
18. The method of detecting as defined in claim 17, wherein the buffer width of the virtual bond layer is greater than or equal to 1/3 of the bonding precision specification.
19. A semiconductor device, characterized in that the semiconductor device comprises:
a first device wafer on which a first alignment mark is formed, wherein the first alignment mark has a ring shape;
a second device wafer having a second alignment mark formed thereon;
forming a dielectric layer on the surface of the second device wafer on which the second alignment mark is formed, wherein the surface of the dielectric layer is flush with the surface of the second alignment mark;
forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;
and bonding the first device wafer and the second device wafer, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is opposite to a blank area surrounded by the first alignment mark.
20. The semiconductor device of claim 19, wherein the virtual bond layer is comprised of a number of virtual bond sites that are spaced apart from each other independently.
21. The semiconductor device of claim 19, wherein a density of the virtual bond sites included in the virtual bond layer is based on a bonding force requirement of the entire device wafer on the non-critical area, and the density of the virtual bond sites is such that a bonding force after the first alignment mark and the virtual bond layer are bonded is 30% to 70% of the bonding force requirement of the entire device wafer on the non-critical area.
22. The semiconductor device of claim 19, wherein a difference between a loop line width of the first alignment mark and a width of the dummy bonding layer is greater than a constant which is a sum of a bonding precision specification, a width of a bonding interface affecting a pattern boundary, and a buffer width of the dummy bonding layer.
23. The semiconductor device of claim 22, wherein a buffer width of the dummy bonding layer is greater than or equal to 1/3 of the bonding precision specification.
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| CN108899288B (en) * | 2018-07-20 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | Wafer mark monitoring method and method for judging alignment position of laser marking machine |
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN110444530A (en) * | 2019-07-12 | 2019-11-12 | 南通沃特光电科技有限公司 | A kind of wafer bonding align structures and its alignment methods |
| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
| CN110729174A (en) * | 2019-09-24 | 2020-01-24 | 杭州臻镭微波技术有限公司 | Three-dimensional stacking alignment method |
| CN110767590A (en) * | 2019-10-31 | 2020-02-07 | 长春长光圆辰微电子技术有限公司 | Method for aligning and bonding two silicon wafers by using silicon wafer notches |
| CN112838019B (en) * | 2019-11-25 | 2024-12-03 | 格科微电子（上海）有限公司 | Alignment detection method for wafer bonding |
| CN110993490A (en) * | 2019-12-30 | 2020-04-10 | 长春长光圆辰微电子技术有限公司 | A method for realizing heterogeneous bonding of chips of different sizes |
| CN111591955B (en) * | 2020-05-26 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Wafer bonding structure and method |
| CN111933618B (en) * | 2020-08-13 | 2022-01-28 | 武汉新芯集成电路制造有限公司 | Wafer assembly with alignment mark, forming method thereof and wafer alignment method |
| CN113809066B (en) * | 2021-09-16 | 2023-10-24 | 长江存储科技有限责任公司 | Wafer, wafer structure and wafer manufacturing method |
| CN114361014B (en) * | 2021-12-06 | 2024-07-26 | 武汉新芯集成电路股份有限公司 | Wafer bonding method and wafer bonding equipment |
| US11899376B1 (en) * | 2022-08-31 | 2024-02-13 | Applied Materials, Inc. | Methods for forming alignment marks |
| CN117116914B (en) * | 2023-10-24 | 2023-12-22 | 苏州芯慧联半导体科技有限公司 | Measurement mark and measurement method for wafer alignment |
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