CN108206142B - Bonding alignment precision detection method and semiconductor device - Google Patents

Abstract

The invention provides a method for detecting bonding alignment precision and a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the first alignment mark is annular in shape; providing a second device wafer, and forming a second alignment mark on the second device wafer; forming a dielectric layer to cover the surface of the second device wafer, on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark; forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer; bonding the first device wafer and the second device wafer, aligning and bonding the first alignment mark and the virtual bonding layer, and enabling the second alignment mark to be opposite to the blank area surrounded by the first alignment mark; and imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of bonding.

Description

A detection method of bonding alignment accuracy and semiconductor device

technical field

The present invention relates to the technical field of semiconductors, in particular to a method for detecting bonding alignment accuracy and a semiconductor device.

Background technique

Wafer bonding technology is widely used in three-dimensional integrated circuits (3D IC), micro-electromechanical systems (MEMS), CMOS image sensors (CIS), silicon-on-insulator (SOI) and other fields. Usually the bonding between the device wafer and the bare silicon wafer does not require high alignment accuracy, and the alloy bonding between the device wafer and the device wafer usually requires the interconnection of the device structure and electrical properties. High alignment accuracy. With the development of semiconductor technology, the complexity and integration of 3D devices will become higher and higher, and the requirements for bonding and alignment accuracy will also increase. Usually, an infrared light source is used to penetrate the wafer to identify the detection pattern of the alignment accuracy, and this method limits the detection pattern film layer to a certain extent. The characteristics of the alloy bonding itself will make the bonding interface change during this process, which will reduce the quality of the graphics.

This status quo is difficult to meet the increasing quality requirements of 3D devices for the alignment accuracy of the bonding process. Therefore, it is necessary to propose a new detection method for the bonding alignment accuracy to solve the above technical problems.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In view of the deficiencies of the prior art, the first embodiment of the present invention provides a method for detecting bonding alignment accuracy, and the method includes:

A first device wafer is provided, and a first alignment mark is formed on the first device wafer, wherein the shape of the first alignment mark is annular;

providing a second device wafer, and forming a second alignment mark on the second device wafer;

forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark;

forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer;

The first device wafer and the second device wafer are bonded, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is The blank areas surrounded by the first alignment marks are opposite;

The pattern formed by the first alignment mark and the second alignment mark is imaged to detect the alignment accuracy of the bonding.

Further, the virtual bonding layer is composed of several virtual bonding points that are independently spaced from each other.

Further, the size of each of the virtual bonding points is smaller than the width of the ring line of the first alignment mark.

Further, the shape of each of the virtual bonding points is a rectangle.

Further, the side length of the rectangle ranges from 0.5 to 5 μm.

Further, the shape of the first alignment mark is a rectangular ring.

Further, the loop line width of the first alignment mark is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm.

Further, a first device layer is also formed on the first device wafer, the first device layer and the first alignment mark are located on the same surface of the first device wafer, and the first device layer is located on the same surface of the first device wafer. A device layer is located on one side of the first alignment mark, wherein the step of forming the first alignment mark includes:

forming a top metal material layer on the surface of the first device wafer, the top metal material layer covering the first device layer;

The top metal material layer is patterned to form the first alignment marks and a top metal layer on the first device layer.

Further, the material of the first alignment mark includes aluminum.

Further, a second device layer is also formed on the second device wafer, the second device layer and the second alignment mark are located on the same surface of the second device wafer, and the second device layer is located on the same surface of the second device wafer. Two device layers are located on one side of the second alignment mark, wherein the step of forming the second alignment mark includes:

forming an interconnecting metal material layer on the surface of the second device wafer, the interconnecting metal material layer covering the second device layer;

The interconnecting metal material layer is patterned to form the second alignment mark and an interconnecting metal layer over the second device layer, the interconnecting metal layer being electrically connected to the second device layer.

Further, the step of forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer includes:

depositing a bonding material layer on the dielectric layer;

The bonding material layer is patterned to form the dummy bonding layer and a bonding layer on the interconnect metal layer.

Further, the step of bonding the first device wafer and the second device wafer further includes:

The first device layer and the second device layer are aligned for bonding, wherein the top metal layer and the bonding layer are bonded.

Further, the material of the virtual bonding layer includes Ge.

Further, after the first device wafer and the second device wafer are bonded, the step of thinning the first device wafer from the back of the first device wafer is further included.

Further, the pattern formed by the first alignment mark and the second alignment mark is irradiated and imaged from the backside of the first device wafer by using an infrared light source, so as to detect the alignment accuracy of the bonding.

Further, the density of the virtual bonding points included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area, and the density of the virtual bonding points makes the first alignment mark and the virtual bonding point. The bonding force after layer bonding is 30% to 70% of the bonding force requirement for the entire device wafer to non-critical areas.

Further, the difference between the width of the ring line of the first alignment mark and the width of the virtual bonding layer is greater than a constant, and the constant is the specification of bonding accuracy, the width of the influence of the bonding interface on the graphic boundary and the virtual bonding layer. The sum of the three buffer widths.

Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.

The second embodiment of the present invention provides a semiconductor device, and the semiconductor device includes:

a first device wafer, on which a first alignment mark is formed, wherein the shape of the first alignment mark is a ring;

a second device wafer, a second alignment mark is formed on the second device wafer;

A dielectric layer is formed on the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark;

A dummy bonding layer surrounding the second alignment mark is formed on the dielectric layer;

The first device wafer and the second device wafer are bonded, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is The blank area surrounded by the first alignment mark is opposite.

Further, the virtual bonding layer is composed of several virtual bonding points that are independently spaced from each other.

Further, the density of the virtual bonding points included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area, and the density of the virtual bonding points makes the first alignment mark and the virtual bonding point. The bonding force after layer bonding is 30% to 70% of the bonding force requirement for the entire device wafer to non-critical areas.

Further, the difference between the width of the ring line of the first alignment mark and the width of the virtual bonding layer is greater than a constant, and the constant is the specification of bonding accuracy, the width of the influence of the bonding interface on the graphic boundary and the virtual bonding layer. The sum of the three buffer widths.

Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.

The detection method of the present invention is a detection method applied to indirect alignment of alloy bonding. By introducing an indirect second alignment mark, the alignment image of the original Al-Ge direct bonding is changed to "the first alignment image". An alignment mark and a second alignment mark” are indirectly aligned with the alignment pattern to improve the quality of the pattern. And by adding a virtual bonding layer graphic at a specified position according to a specific design rule, the entire detection graphic area can be bonded, which ensures the bonding quality and improves its application range.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

1A to 1D are schematic structural diagrams of devices corresponding to the implementation of relevant steps of an existing method for detecting bonding alignment accuracy;

2A-2H show the schematic structural diagrams of the device obtained by the relevant steps of the method for detecting the bonding alignment accuracy according to an embodiment of the present invention, wherein, FIG. 2G is a partial top view of the alignment detection mark area;

Fig. 2I shows the infrared detection effect diagram of one embodiment of the present invention;

FIG. 3 shows a flowchart of a method for detecting bonding alignment accuracy according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

For a thorough understanding of the present invention, detailed structures and steps will be presented in the following description, so as to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Hereinafter, the existing method for detecting the bonding alignment accuracy will be briefly described with reference to FIG. 1A to FIG. 1D , wherein FIG. 1A to FIG. 1D illustrate the implementation of the relevant steps of the existing method for detecting the bonding alignment accuracy. The structure diagram of the corresponding device.

First, as shown in FIG. 1A , a first device wafer 100 is provided, and Al alignment marks 101 are formed on the surface of the first device wafer 100 to be bonded.

Next, as shown in FIG. 1B , a second device wafer 200 is provided, and Ge alignment marks 102 are formed on the surface of the second device wafer 200 to be bonded, wherein the size of the Ge alignment marks is smaller than that of the Al alignment marks 101 size.

After that, as shown in FIG. 1C , the first device wafer 100 and the second device wafer 200 are bonded relative to each other, wherein the Al alignment marks 101 and the Ge alignment marks 102 are bonded.

Finally, an infrared light source is used to identify the pattern of the Ge alignment mark on the background of the Al alignment mark, and the obtained alignment pattern 10 is shown in FIG. 1D . In this method, if the Al-Ge is in direct contact, roughness and roughness will be formed due to the alloy reaction. The blurred Al-Ge interface or Ge boundary makes the alignment pattern lower in quality. If Al-Ge is not in contact with this method, the pattern will be difficult to identify due to the penetration of Ge by infrared rays.

Existing inspection methods are difficult to meet the increasing quality requirements of 3D devices for the alignment accuracy of the bonding process.

Example 1

In order to solve the above-mentioned technical problems, the present invention provides a method for detecting bonding alignment accuracy, as shown in FIG. 3 , which mainly includes the following steps:

Step S1, providing a first device wafer, and forming a first alignment mark on the first device wafer, wherein the shape of the first alignment mark is a ring;

Step S2, providing a second device wafer, and forming a second alignment mark on the second device wafer;

Step S3, forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark;

Step S4, forming a virtual bonding layer surrounding the second alignment mark on the dielectric layer;

Step S5, bonding the first device wafer and the second device wafer, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second pair of the alignment mark is opposite to the blank area surrounded by the first alignment mark;

Step S6, imaging the pattern formed by the first alignment mark and the second alignment mark to detect the alignment accuracy of the bonding.

The detection method of the present invention is a detection method applied to indirect alignment of alloy bonding. By introducing an indirect second alignment mark, the alignment image of the original Al-Ge direct bonding is changed to "the first alignment image". An alignment mark and a second alignment mark” are indirectly aligned with the alignment pattern to improve the quality of the pattern. And by adding a virtual bonding layer graphic at a specified position according to a specific design rule, the entire detection graphic area can be bonded, which ensures the bonding quality and improves its application range.

Below, the method for detecting the bonding alignment accuracy of the present invention will be described in detail with reference to FIGS. 2A-2I , wherein FIGS. 2A-2H show the relevant steps of the method for detecting the bonding alignment accuracy according to an embodiment of the present invention. A schematic diagram of the structure of the obtained device, wherein FIG. 2H is a partial top view of the alignment detection mark area; FIG. 2I shows an infrared detection effect diagram of an embodiment of the present invention.

First, as shown in FIG. 2A , a first device wafer 300 is provided, a first device layer 301 is formed on the first device wafer 300 , and a first alignment mark is formed on the first device wafer 300 3021, forming a top metal layer 3022 on the first device layer 301, the first device layer 301 and the first alignment mark 3021 are located on the same side of the first device wafer 300, and the The first device layer 301 is located on one side of the first alignment mark 3021 , wherein the shape of the first alignment mark 3021 is annular.

Specifically, the material of the first device wafer 300 may be at least one of the following materials: silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.

The first device layer formed on the first device wafer can be any device known to those skilled in the art, such as CMOS devices, radio frequency devices, capacitors, resistors, MEMS devices, CIS chips or data processing chips. The first device layer may further include interconnecting lines composed of multiple interconnecting metal layers and through holes for realizing electrical connection between the devices in the first device layer and other devices or circuits.

The material of the first alignment mark may be any metal material, and in this embodiment, the material of the first alignment mark may be aluminum.

Exemplarily, the shape of the first alignment mark 3021 is a ring, specifically, a rectangular ring, a circular ring, an elliptical ring, a polygonal ring or other suitable rings. An alignment mark 3021 is in the shape of a rectangular ring, such as a square ring.

Optionally, the loop line width of the first alignment mark 3021 is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm. Make reasonable settings.

Wherein, the first alignment mark is located in a non-critical area on one side of the device area where the first device layer is formed, and this area generally does not have actual function.

In one example, the method of forming the first alignment mark 3021 and the top metal layer 3022 includes the following steps A1 and A2:

First, step A1 is performed to form a top metal material layer on the surface of the first device wafer 300 , and the top metal material layer covers the first device layer.

Next, the top metal material layer is patterned to form the first alignment marks 3021 and the top metal layer 3022 on the first device layer 301 .

Specifically, a photolithography process can be used to form a patterned photoresist layer on the top metal material layer, where the patterned photoresist layer defines the predetermined first alignment marks 3021 and the pattern positions of the top metal layer 3022 and size, and then use the patterned photoresist layer as a mask to etch the top metal material layer to form the first alignment mark 3021 and the top metal layer 3022. Common wet etching or dry etching can be used. The etching process is not specifically limited here, and finally the photoresist layer is removed.

The thickness of the top metal material layer may be 500 nm˜2000 nm, or other suitable thicknesses.

Optionally, the top metal layer 3022 is electrically connected to the first device layer below it.

Wherein, this step can be directly realized by using a conventional fabrication process of interconnecting lines of semiconductor devices, which only needs to use a photomask including the pattern of the first alignment marks 3021, so no additional production cost is added.

Next, as shown in FIG. 2B , a second device wafer 400 is provided, a second device layer is further formed on the second device wafer, and a second alignment mark 4021 is formed on the second device wafer 400 , the second device layer 401 and the second alignment mark 4021 are located on the same surface of the second device wafer 400 , and the second device layer 401 is located on a side of the second alignment mark 4021 side.

Specifically, the material of the second device wafer 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.

The second device layer formed on the second device wafer can be any device known to those skilled in the art, such as CMOS devices, radio frequency devices, capacitors, resistors, MEMS devices, CIS chips or data processing chips. The second device layer may also include interconnect lines composed of multiple interconnect metal layers and through holes, for realizing electrical connection between the devices in the second device layer and other devices or circuits.

The material of the second alignment mark 4021 may be any metal material, such as aluminum or copper.

Further, the shape of the second alignment mark 4021 may be any suitable shape, such as a rectangle, a circle, an ellipse, or a polygon.

The size of the second alignment mark 4021 can be designed to be smaller than the size of the inner edge of the first alignment mark, so that the second alignment mark 4021 can be opposite to the blank area surrounded by the first alignment mark after alignment bonding, and its size is smaller than the blank area.

In one example, the step of forming the second alignment mark 4021 includes the following steps B1 to B2:

First, step B1 is performed to form an interconnection metal material layer on the surface of the second device wafer 400 , and the interconnection metal material layer covers the second device layer 401 .

The interconnecting metal material layer may be a film layer used to make any layer of interconnecting lines electrically connected to the second device layer 401, or may be the top interconnecting metal layer of the interconnecting lines, wherein preferably the top interconnecting metal layer .

It may be formed using low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), electrochemical coating, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques.

Next, step B2 is performed to pattern the interconnecting metal material layer to form the second alignment mark 4021 and an interconnecting metal layer 4022 located above the second device layer 401, the interconnecting metal layer 4022 and the interconnecting metal layer 4022 The second device layer 401 is electrically connected.

Specifically, a photolithography process can be used to form a patterned photoresist layer on the top metal material layer, where the patterned photoresist layer defines the predetermined second alignment marks and the pattern positions and dimensions of the interconnecting metal layer. , and then use the patterned photoresist layer as a mask to etch the interconnecting metal material layer to form a second alignment mark and an interconnecting metal layer. Common wet etching or dry etching processes can be used here. No specific limitation is made, and finally the photoresist layer is removed.

Next, as shown in FIG. 2C , a dielectric layer 403 is formed to cover the surface of the second device wafer 400 on which the second alignment marks 4021 are formed, and the surface of the dielectric layer 403 is aligned with the second alignment mark 4021 . The surface of the alignment mark 4021 is flush, and further, the dielectric layer 403 also covers the second device wafer 400 outside the interconnection metal layer 4022 .

The dielectric layer 403 can be made of, for example, SiO ₂ , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbon nitride (SiCN). Alternatively, a film or the like in which a SiCN thin film is formed on a fluorocarbon (CF) can also be used. Fluorocarbons are mainly composed of fluorine (F) and carbon (C). As the fluorocarbon, those having an amorphous (non-crystalline) structure can also be used. The dielectric layer 403 may also use a porous structure such as silicon oxycarbide (SiOC).

A conventional deposition method such as chemical vapor deposition can be used first to form a dielectric layer to cover the second device wafer 400, and then a planarization process such as a chemical mechanical polishing process can be used to planarize the dielectric layer 403, stopping at the second device wafer 400. Alignment marks 4021 on the surface.

Next, as shown in FIG. 2D , a dummy bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403 .

In one example, the virtual bonding layer consists of several virtual bonding points 4041 that are independently spaced from each other.

The shape of the virtual bonding point 4041 may be any shape, such as a rectangle, a circle, a triangle, an ellipse, a polygon or other irregular shapes. In this embodiment, the shape of the virtual bonding point 4041 may be a rectangle.

Optionally, several virtual bonding points 4041 are evenly spaced to form a dot matrix as the virtual bonding layer, which is used for the bonding of the virtual bonding layer and the first alignment mark 3021 later.

Further, several virtual bonding points 4041 are evenly spaced and arranged in a ring shape similar to or even the same as the first alignment mark but with different sizes.

In one example, the density of the virtual bonding points 4041 included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area, and the density of the virtual bonding points makes the first alignment mark The bonding force after bonding with the virtual bonding layer is 30% to 70% of the bonding force requirement for the non-critical area of the entire device wafer.

Among them, the non-critical area generally refers to the area on the device wafer other than the device layer that does not have any actual function.

Further, in order not to affect the pattern of the first alignment mark 3021 during subsequent bonding, the size of each of the virtual bonding points may be smaller than the width of the ring line of the first alignment mark.

Optionally, the following conditions may also be satisfied during layout design: the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is greater than a constant, and the constant is the bonding accuracy specification, the bonding The interface affects the sum of the graphic boundary width and the buffer width of the virtual bonding layer.

Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.

It is worth mentioning that the bonding accuracy specification refers to the bonding alignment accuracy allowed by the process, and its specific value is set according to the actual process requirements. For example, the bonding accuracy specification can be one-third of the minimum line width.

The width of the influence of the bonding interface on the pattern boundary refers to the width of the influence on the pattern boundary of the first alignment mark by the bonding interface of the two allowed by the process after the first alignment mark and the virtual bonding layer are subsequently bonded.

Optionally, the side length of the rectangular virtual bonding point 4041 may range from 0.5 to 5 μm, and may also be appropriately adjusted according to the actual process.

Optionally, the material of the virtual bonding layer includes Ge, and can also be any other material suitable for alloy bonding with metal.

In one example, the process of forming a virtual bonding layer includes the following steps:

First, a bonding material layer is deposited on the dielectric layer 403, and the bonding material layer is used to form a dummy bonding layer, and then a bonding layer for bonding with the first device wafer.

The Ge bonding material layer may be formed by a conventional germanium evaporation or germanium sputtering process for microelectronic integrated circuits.

The thickness of the formed bonding material layer can be reasonably set according to the actual process, for example, it can be 500-1500 nm, etc., which is not specifically limited here.

Next, the bonding material layer is patterned to form the dummy bonding layer and the bonding layer 4042 on the interconnect metal layer 4022 .

The patterning of the bonding material layer can be achieved by using a photolithography process and an etching process, which will not be described in detail here.

The bonding layer 4042 is used for bonding the first device layer of the first device wafer and the second device layer of the second device wafer.

Next, as shown in FIG. 2E , the first device wafer 300 and the second device wafer 400 are relatively aligned and bonded, and the top metal layer and the bonding layer are bonded together, so that the The first alignment mark 3021 and the dummy bonding layer are aligned and bonded, wherein the second alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021 .

Specifically, a suitable bonding process is selected according to the materials of the top metal layer and the bonding layer, the first alignment mark and the dummy bonding layer. The material is aluminum, and when the material of the bonding layer and the virtual bonding layer is Ge, the aluminum-germanium eutectic bonding can be performed by using a conventional bonding process in the industry, and the bonding temperature is controlled between 425°C and 445°C. , the aluminum and germanium are fused to each other within this temperature range so that the first device wafer 300 and the second device wafer 400 are bonded together.

After bonding, the second alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021 to realize indirect alignment between the first alignment mark 4021 and the second alignment mark 3021 .

Wherein, the region including the first device layer and the second device layer can be called the device region 31 , and the region including the first alignment mark and the second alignment mark in turn is the alignment detection mark region 30 .

The partial top view of the alignment detection mark region 30 after bonding is shown in FIG. 2H .

Next, as shown in FIG. 2F , the first device wafer 300 is thinned from the backside of the first device wafer 300 .

The back surface of the first device wafer 300 refers to the surface opposite to the surface on which the first device layer is formed.

Thinning in this step can be performed using a backgrinding process or chemical mechanical polishing.

The thickness of the thinned first device wafer is reasonably set according to device requirements, which is not specifically limited here.

Next, as shown in FIG. 2G , the image formed by the first alignment mark and the second alignment mark is imaged to detect the alignment accuracy of the bonding.

Any imaging method applicable to the present invention can be used to obtain a pattern composed of the first alignment mark and the second alignment mark, and the pattern is used as a detection pattern for detecting the alignment accuracy of the bonding.

The imaging method can use, for example, ultrasonic imaging, X-ray imaging, infrared imaging, etc. In this embodiment, an infrared imaging method is preferably used, and an infrared light source is used to detect the first device wafer from the back of the first device wafer. The pattern formed by the alignment mark and the second alignment mark is illuminated and imaged to detect the alignment accuracy of the bonding.

FIG. 2I shows an infrared detection effect diagram of an embodiment of the present invention. From the effect diagram, the alignment accuracy between the first alignment mark and the second alignment mark can be measured, and then the alignment accuracy of the entire bonding process can be obtained. . Due to the introduction of indirect metal alignment layers (first and second alignment marks), infrared imaging of Al-metal patterns can improve alignment quality.

To sum up, the detection method of the bonding alignment accuracy of the present invention is an indirect alignment detection method applied to alloy bonding. By introducing indirect metal alignment marks (the first alignment mark and the second pair of Alignment mark), so that the original Al-Ge alignment image is changed to "Al-metal" alignment pattern to improve the image quality. And by adding the Ge virtual bonding layer pattern at the designated position according to specific design rules, the entire detection pattern area can be bonded, which ensures the bonding quality and improves its application range, including the following advantages:

1) Introduce indirect metal alignment layers (first alignment marks and second alignment marks), and use infrared imaging of Al-metal patterns to improve alignment quality;

2) The cited indirect Al alignment mark, whose process is the front-end semiconductor manufacturing process, can ensure the alignment error with the Ge virtual bonding layer within 70nm, effectively control the introduction of errors in the indirect layer, and ensure the measurement accuracy.

3) The setting of the Ge virtual bonding layer with specific design rules, under the premise of ensuring the quality of infrared imaging, enables the alignment detection mark area to be effectively bonded, reducing the process risk caused by uneven bonding.

4) The present invention is implemented in a process with more than one layer of interconnection lines, without any additional production cost.

Embodiment 2

The present invention also provides a semiconductor device, the bonding alignment accuracy of the semiconductor device can be detected by using the detection method of the first embodiment.

As shown in FIG. 2G and FIG. 2H , the semiconductor device mainly includes:

the first device wafer 300, a first alignment mark 3021 is formed on the first device wafer 300, wherein the shape of the first alignment mark 3021 is a ring;

the second device wafer 400, on which a second alignment mark 4021 is formed;

A dielectric layer 403 is formed on the surface of the second device wafer 400 on which the second alignment marks 4021 are formed, and the surface of the dielectric layer 403 is flush with the surface of the second alignment marks 4021;

A dummy bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403;

The first device wafer 300 and the second device wafer 400 are bonded, wherein the first alignment mark 3021 and the dummy bonding layer 4041 are aligned and bonded, and the second pair of The alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021 .

As an example, the semiconductor device of the present invention includes a first device wafer 300 on which a first device layer 301 is formed and on which a first alignment is formed mark 3021, a top metal layer 3022 is formed on the first device layer 301, the first device layer 301 and the first alignment mark 3021 are located on the same side of the first device wafer 300, and The first device layer 301 is located on one side of the first alignment mark 3021 , wherein the shape of the first alignment mark 3021 is annular.

Specifically, the material of the first device wafer 300 may be at least one of the following materials: silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.

The first device layer formed on the first device wafer can be any device known to those skilled in the art, such as CMOS devices, radio frequency devices, capacitors, resistors, MEMS devices, CIS chips or data processing chips. The first device layer may further include interconnecting lines composed of multiple interconnecting metal layers and through holes for realizing electrical connection between the devices in the first device layer and other devices or circuits.

The material of the first alignment mark may be any metal material, and in this embodiment, the material of the first alignment mark may be aluminum.

Exemplarily, the shape of the first alignment mark 3021 is a ring, specifically, a rectangular ring, a circular ring, an elliptical ring, a polygonal ring or other suitable rings. An alignment mark 3021 is in the shape of a rectangular ring, such as a square ring.

Optionally, the loop line width of the first alignment mark 3021 is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm. Make reasonable settings.

Wherein, the first alignment mark is located in a non-critical area on one side of the device area where the first device layer is formed, and this area generally does not have actual function.

The thickness of the first alignment mark and the top metal layer 3022 may be 500 nm˜2000 nm, or other suitable thicknesses.

Optionally, the top metal layer 3022 is electrically connected to the first device layer below it.

Further, the semiconductor device further includes a second device wafer 400 , a second device layer 401 is formed on the second device wafer, and a second alignment layer is formed on the second device wafer 400 Mark 4021, the second device layer 401 and the second alignment mark 4021 are located on the same side of the second device wafer 400, and the second device layer 401 is located on the second alignment mark 4021 side.

Specifically, the material of the second device wafer 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.

The second device layer formed on the second device wafer can be any device known to those skilled in the art, such as CMOS devices, radio frequency devices, capacitors, resistors, MEMS devices, CIS chips or data processing chips. The second device layer may also include interconnect lines composed of multiple interconnect metal layers and through holes, for realizing electrical connection between the devices in the second device layer and other devices or circuits.

The material of the second alignment mark 4021 may be any metal material, such as aluminum or copper.

Further, the shape of the second alignment mark 4021 may be any suitable shape, such as a rectangle, a circle, an ellipse, or a polygon.

The size of the second alignment mark 4021 can be designed to be smaller than the size of the inner edge of the first alignment mark, so that the second alignment mark 4021 can be opposite to the blank area surrounded by the first alignment mark after alignment bonding, and its size is smaller than the blank area.

Further, a dielectric layer 403 is formed on the surface of the second device wafer 400 on which the second alignment mark 4021 is formed, and the surface of the dielectric layer 403 and the surface of the second alignment mark 4021 Flush, the dielectric layer 403 also covers the second device wafer 400 outside the interconnection metal layer 4022 .

The dielectric layer 403 can be made of, for example, SiO ₂ , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbon nitride (SiCN). Alternatively, a film or the like in which a SiCN thin film is formed on a fluorocarbon (CF) can also be used. Fluorocarbons are mainly composed of fluorine (F) and carbon (C). As the fluorocarbon, those having an amorphous (non-crystalline) structure can also be used. The dielectric layer 403 may also use a porous structure such as silicon oxycarbide (SiOC).

Further, a dummy bonding layer surrounding the second alignment mark 4021 is formed on the dielectric layer 403 .

In one example, the virtual bonding layer consists of several virtual bonding points 4041 that are independently spaced from each other.

The shape of the virtual bonding point 4041 may be any shape, such as a rectangle, a circle, a triangle, an ellipse, a polygon or other irregular shapes. In this embodiment, the shape of the virtual bonding point 4041 may be a rectangle.

Optionally, several virtual bonding points 4041 are evenly spaced to form a dot matrix as the virtual bonding layer, which is used for the bonding of the virtual bonding layer and the first alignment mark 3021 later.

Further, several virtual bonding points 4041 are evenly spaced and arranged in a ring shape similar to or even the same as the first alignment mark but with different sizes.

In one example, the density of the virtual bonding points 4041 included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area, and the density of the virtual bonding points makes the first alignment mark The bonding force after bonding with the virtual bonding layer is 30% to 70% of the bonding force requirement for the non-critical area of the entire device wafer.

Among them, the non-critical area generally refers to the area on the device wafer other than the device layer that does not have any actual function.

Further, in order not to affect the pattern of the first alignment mark 3021 during subsequent bonding, the size of each of the virtual bonding points may be smaller than the width of the ring line of the first alignment mark.

Optionally, the following conditions may also be satisfied during layout design: the difference between the loop line width of the first alignment mark and the width of the virtual bonding layer is greater than a constant, and the constant is the bonding accuracy specification, the bonding The interface affects the sum of the graphic boundary width and the buffer width of the virtual bonding layer.

Further, the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification.

It is worth mentioning that the bonding accuracy specification refers to the bonding alignment accuracy allowed by the process, and its specific value is set according to the actual process requirements. For example, the bonding accuracy specification can be one-third of the minimum line width.

The width of the influence of the bonding interface on the pattern boundary refers to the width of the influence on the pattern boundary of the first alignment mark by the bonding interface of the two allowed by the process after the first alignment mark and the virtual bonding layer are subsequently bonded.

Optionally, the side length of the rectangular virtual bonding point 4041 may range from 0.5 to 5 μm, and may also be appropriately adjusted according to the actual process.

Optionally, the material of the virtual bonding layer includes Ge, and can also be any other material suitable for alloy bonding with metal.

Further, the first device wafer 300 and the second device wafer 400 are bonded, wherein the top metal layer and the bonding layer are bonded together, and the first alignment mark 3021 and the dummy bonding layer 4041 are aligned and bonded, and the second alignment mark 4021 is opposite to the blank area surrounded by the first alignment mark 3021 .

Wherein, the region including the first device layer and the second device layer can be called the device region 31 , and the region including the first alignment mark and the second alignment mark in turn is the alignment detection mark region 30 .

The partial top view of the alignment detection mark region 30 is shown in FIG. 2H .

Since the semiconductor device of the present invention includes the same first alignment marks, second alignment marks, and dummy bonding layers as in the first embodiment, the bonding accuracy can be detected by using the detection method in the first embodiment. , the semiconductor device of the present invention also has the advantages of the first embodiment.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (23)

1. a detection method of bonding alignment accuracy, is characterized in that, described method comprises: A first device wafer is provided, and a first alignment mark is formed on the first device wafer, wherein the shape of the first alignment mark is annular; providing a second device wafer, and forming a second alignment mark on the second device wafer; forming a dielectric layer to cover the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark; forming a dummy bonding layer surrounding the second alignment mark on the dielectric layer; The first device wafer and the second device wafer are bonded, wherein the first alignment mark and the virtual bonding layer are aligned and bonded, and the second alignment mark is The blank areas surrounded by the first alignment marks are opposite; The pattern formed by the first alignment mark and the second alignment mark is imaged to detect the alignment accuracy of the bonding. 2 . The detection method according to claim 1 , wherein the virtual bonding layer is composed of several virtual bonding points with independent intervals. 3 . 3 . The detection method according to claim 2 , wherein the size of each virtual bonding point is smaller than the width of the loop line of the first alignment mark. 4 . 4. The detection method according to claim 2, wherein the shape of each of the virtual bonding points is a rectangle. 5 . The detection method according to claim 4 , wherein the side length of the rectangle ranges from 0.5 to 5 μm. 6 . 6. The detection method according to claim 1, wherein the shape of the first alignment mark is a rectangular ring. 7 . The detection method according to claim 6 , wherein the loop line width of the first alignment mark is greater than 20 μm, and the length or width of the outer edge of the first alignment mark ranges from 50 μm to 300 μm. 8 . 8 . The detection method according to claim 1 , wherein a first device layer is further formed on the first device wafer, and the first device layer and the first alignment mark are located in the The same side of the first device wafer, and the first device layer is located on one side of the first alignment mark, wherein the step of forming the first alignment mark includes: forming a top metal material layer on the surface of the first device wafer, the top metal material layer covering the first device layer; The top metal material layer is patterned to form the first alignment marks and a top metal layer on the first device layer. 9 . The detection method of claim 1 , wherein the material of the first alignment mark comprises aluminum. 10 . 10 . The detection method according to claim 8 , wherein a second device layer is further formed on the second device wafer, and the second device layer and the second alignment mark are located on the second device wafer. 11 . The second device wafer is on the same side, and the second device layer is located on one side of the second alignment mark, wherein the step of forming the second alignment mark includes: forming an interconnecting metal material layer on the surface of the second device wafer, the interconnecting metal material layer covering the second device layer; The interconnecting metal material layer is patterned to form the second alignment mark and an interconnecting metal layer over the second device layer, the interconnecting metal layer being electrically connected to the second device layer. 11. The detection method of claim 10, wherein the step of forming a dummy bonding layer on the dielectric layer surrounding the second alignment mark comprises: depositing a bonding material layer on the dielectric layer; The bonding material layer is patterned to form the dummy bonding layer and a bonding layer on the interconnect metal layer. 12. The detection method of claim 11, wherein the step of bonding the first device wafer and the second device wafer further comprises: The first device layer and the second device layer are aligned for bonding, wherein the top metal layer and the bonding layer are bonded. 13. The detection method of claim 1, wherein the material of the virtual bonding layer comprises Ge. 14. The detection method according to claim 1, wherein after the first device wafer and the second device wafer are bonded, the method further comprises: facing the first device wafer from the back of the first device wafer. The step of thinning the first device wafer is described. 15. The detection method according to claim 1, characterized in that, using an infrared light source from the back side of the first device wafer, the pattern formed by the first alignment mark and the second alignment mark is subjected to Illuminated and imaged to check the alignment accuracy of the bond. 16. The detection method according to claim 2, wherein the density of the virtual bonding points included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area as a reference standard, and the virtual bonding point density is a reference standard. The density of the bonding points makes the bonding force after the first alignment mark and the dummy bonding layer are bonded to be 30%-70% of the bonding force requirement of the whole device wafer to the non-critical area. 17 . The detection method of claim 1 , wherein the difference between the width of the ring line of the first alignment mark and the width of the virtual bonding layer is greater than a constant, and the constant is a bonding accuracy specification, a bond The sum of the influence width of the interface on the graphic boundary and the buffer width of the virtual bonding layer. 18 . The detection method according to claim 17 , wherein the buffer width of the virtual bonding layer is greater than or equal to 1/3 of the bonding precision specification. 19 . 19. A semiconductor device, characterized in that the semiconductor device comprises: a first device wafer, on which a first alignment mark is formed, wherein the shape of the first alignment mark is a ring; a second device wafer, a second alignment mark is formed on the second device wafer; A dielectric layer is formed on the surface of the second device wafer on which the second alignment mark is formed, and the surface of the dielectric layer is flush with the surface of the second alignment mark; A dummy bonding layer surrounding the second alignment mark is formed on the dielectric layer; The first device wafer and the second device wafer are bonded, wherein the first alignment mark and the dummy bonding layer are aligned and bonded, and the second alignment mark is The blank area surrounded by the first alignment mark is opposite. 20. The semiconductor device of claim 19, wherein the dummy bonding layer is composed of a plurality of dummy bonding points independently spaced from each other. 21. The semiconductor device according to claim 19, wherein the density of the virtual bonding points included in the virtual bonding layer is based on the bonding force requirement of the entire device wafer to the non-critical area as a reference standard, and the virtual bonding point density is a reference standard. The density of the bonding points makes the bonding force after the first alignment mark and the dummy bonding layer are bonded to be 30% to 70% of the bonding force requirement of the whole device wafer to the non-critical area. 22. The semiconductor device of claim 19, wherein the difference between the width of the loop of the first alignment mark and the width of the dummy bonding layer is greater than a constant, the constant being a bonding accuracy specification, a bond The sum of the influence width of the interface on the graphic boundary and the buffer width of the virtual bonding layer. 23. The semiconductor device of claim 22, wherein the buffer width of the dummy bonding layer is greater than or equal to 1/3 of the bonding precision specification.

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