CN108199696B - Automatic gain control circuit of transimpedance amplifier - Google Patents
Automatic gain control circuit of transimpedance amplifier Download PDFInfo
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- CN108199696B CN108199696B CN201810183064.8A CN201810183064A CN108199696B CN 108199696 B CN108199696 B CN 108199696B CN 201810183064 A CN201810183064 A CN 201810183064A CN 108199696 B CN108199696 B CN 108199696B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3084—Automatic control in amplifiers having semiconductor devices in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses an automatic gain control circuit of a transimpedance amplifier, which comprises a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS tube Q1, an NMOS tube Q2, an error amplifier U3 and a bias current source Ib; the input end of the transimpedance amplifier TIA1 is connected with the drain electrode of the NMOS tube Q1; the output end of the transimpedance amplifier TIA1 is connected with the source electrode of the NMOS tube Q1; the input end of the transimpedance amplifier TIA2 is connected with the drain electrode of the NMOS tube Q2; the output end of the transimpedance amplifier TIA2 is connected with the source electrode of the NMOS tube Q2; the non-inverting input end and the inverting input end of the error amplifier U2 are respectively connected with the input end and the output end of the transimpedance amplifier TIA 2; the output end of the error amplifier U2 is connected with the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2; the output end of the bias current source Ib is connected with the non-inverting input end of the error amplifier U2 and the drain electrode of the MOS tube Q2. According to the invention, the NMOS transistor Q1 and the NMOS transistor Q2 can realize the quick response of the automatic gain control of the transimpedance amplifier TIA1 without adopting a device with a low starting voltage threshold.
Description
Technical Field
The invention relates to the field of transimpedance amplifiers, in particular to an automatic gain control circuit of a transimpedance amplifier.
Background
In modern high-speed optical fiber communication systems, a transimpedance amplifier TIA (Trans-Impedance Amplifier) is used to convert and amplify a weak photocurrent signal generated by a photodiode into a voltage signal, and output the voltage signal to a subsequent circuit for processing. Therefore, the TIA is at the forefront of the receiving end and is a core device of the receiving end of the optical communication system, and the core indexes such as noise, sensitivity, dynamic range, sensitivity and the like basically determine the performance of the whole receiving system.
The input dynamic range in a transimpedance amplifier circuit is an important indicator defined as the difference between saturated input optical power and sensitivity. The saturated input optical power and sensitivity are defined as the maximum and minimum input optical power, respectively, within a certain allowable error rate range. The sensitivity is mainly determined by equivalent input noise, and the smaller the equivalent input noise is, the higher the sensitivity index is; the saturated input optical power is mainly determined by factors such as pulse width distortion of the output signal. To obtain a relatively good sensitivity index, the value of the transresistance RFz is required to be as large as possible under the premise of bandwidth permission, and the larger the transresistance is, the smaller the saturated input optical power is.
An automatic gain control (Automatic Gain Control, AGC) circuit is typically added to a transimpedance amplifier for practical use to address this problem. I.e. at smaller input optical powers, a large transimpedance is maintained; when the input optical power is larger, the transimpedance is automatically adjusted and reduced, so that the output signal cannot generate excessive pulse width distortion, and the dynamic range is widened.
The AGC function typically employs an adjustable active resistor in parallel with a feedback resistor to achieve adjustment of the transimpedance. There are two common methods for detecting whether the input optical power is too high to cause the output to generate too large pulse width distortion, firstly, detecting the ac output amplitude of the transimpedance amplifier TIA, as shown in fig. 1; and secondly, detecting the output direct current level change of the transimpedance amplifier TIA, as shown in fig. 2.
Both methods require the addition of a low pass filter LPF in the feedback loop to filter out high frequency components to maintain the transimpedance stable and reduce output signal jitter. Typically, the low frequency cut-off frequency of the AGC loop needs to be as low as several tens KHz in order to guarantee acceptable jitter characteristics. Since the AGC loop has a low frequency cut-off frequency, which is low again, the AGC loop requires a long settling time, typically around tens of us. Both AGC circuits are therefore only suitable for continuous communication mode.
In a passive optical network (Passive Optical Network, PON) system, at OLT (Optical Line Terminal), signals received by a receiving end are Burst (Burst Mode) signals, that is, several tens of ONU (Optical Network Unit) office ends alternately send signals to the OLT according to a certain time division, and the optical power and the transmission distance of each ONU are different, so that the optical signals received by the OLT have the characteristics of time sequence Burst and abrupt change of optical power, as shown in fig. 3.
PON is mainly divided into GPON and EPON, wherein the difficulty of implementing GPON is much greater than EPON due to NRZ encoding and stricter timing requirements. Taking GPON as an example, a typical GPON burst packet is shown in fig. 4. A burst packet consists of a preamble (36 ns), delimiters (16 ns), valid data (NRZ encoded), and a security gap field (26 ns). When the burst receiving system of the OLT receives a burst data packet, the entire burst receiving system needs to establish a stable working state within the preamble timing sequence, i.e., 36ns, to correctly process the subsequent valid data signals.
Therefore, if the AGC loop is required to converge and stabilize within 36ns by using the conventional automatic gain control method, the low frequency cut-off frequency of the AGC feedback loop cannot be made too low, and the theoretical calculation cannot be lower than 5MHz. And since the signal of GPON is encoded as NRZ code, the longest line code (consequential identical digit, CID) reaches 72 bits, and the low frequency cut-off frequency of the AGC loop must be low enough to reduce the DC drift (DC Wandering) effect and jitter when transmitting such encoded signal. The existence of such a discrepancy therefore results in the conventional AGC control loop not being suitable for use in a burst mode GPON receiving system.
In order to overcome the above contradiction, the conventional burst automatic gain control circuit uses a voltage-controlled shunt element connected in parallel with the feedback resistor RF of the transimpedance amplifier TIA to clamp the output amplitude of the transimpedance amplifier TIA, as shown in fig. 5 and 6, the voltage-controlled shunt element may be a diode D, as shown in fig. 5 and may also be a MOS transistor Q adopting a diode connection mode; when the current of the input signal increases to a certain extent, the voltage of the output node of the transimpedance amplifier TIA is reduced, so that the voltage drop of the feedback resistor RF is increased to enable the voltage-controlled shunt element to be started, and the voltage-controlled shunt element shunts part of the current of the input signal, so that the output amplitude of the transimpedance amplifier TIA is not increased sharply any more, and the output amplitude of the transimpedance amplifier TIA is clamped within a certain range. However, this method has a disadvantage that the threshold of the turn-on voltage of a typical diode is about 0.7V, and the threshold of the turn-on voltage of a MOS transistor adopting the diode connection method is also substantially above 0.4V; however, the TIA output amplitude of the transimpedance amplifier will not generate significant distortion only within 0.2V, so that the voltage-controlled shunt element can only use a special low threshold (low threshold) device to realize the fast response of the automatic gain control of the transimpedance amplifier, which is costly in terms of process cost and requires special process support, and many commercial processes do not support the process options of such special devices.
Disclosure of Invention
The invention aims to provide an automatic gain control circuit of a cross-foot amplifier, which overcomes the defects of the prior art.
In order to achieve the above object, the solution of the present invention is:
a transimpedance amplifier automatic gain control circuit comprises a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS tube Q1, an NMOS tube Q2, an error amplifier U3 and a bias current source Ib; the circuit structures, the device sizes and the process parameters of the transimpedance amplifier TIA2 and the transimpedance amplifier TIA1 are the same; the starting voltage threshold values of the NMOS tube Q1 and the NMOS tube Q2 are the same; the input end of the transimpedance amplifier TIA1 is connected with the drain electrode of the NMOS tube Q1; the output end of the transimpedance amplifier TIA1 is connected with the source electrode of the NMOS tube Q1; the input end of the transimpedance amplifier TIA2 is connected with the drain electrode of the NMOS tube Q2; the output end of the transimpedance amplifier TIA2 is connected with the source electrode of the NMOS tube Q2; the non-inverting input end and the inverting input end of the error amplifier U2 are respectively connected with the input end and the output end of the transimpedance amplifier TIA 2; the output end of the error amplifier U2 is connected with the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2; the input end of the bias current source Ib is connected with the working power supply VDD, and the output end of the bias current source Ib is connected with the non-inverting input end of the error amplifier U2 and the drain electrode of the MOS tube Q2.
The transimpedance amplifier TIA1 comprises an inverting amplifier U1 and a resistor R1; the transimpedance amplifier TIA2 comprises an inverting amplifier U2 and a resistor R2; the input end and the output end of the inverting amplifier U1 are respectively connected with the two ends of the resistor R1; the input end of the inverting amplifier U1 is the input end of the transimpedance amplifier TIA1, and the output end of the inverting amplifier U1 is the output end of the transimpedance amplifier TIA 1; the input end and the output end of the inverting amplifier U2 are respectively connected with the two ends of the resistor R2; the input end of the inverting amplifier U2 is the input end of the transimpedance amplifier TIA2, and the output end of the inverting amplifier U2 is the output end of the transimpedance amplifier TIA 2.
The inverting amplifier U1 comprises a resistor R01, an NMOS tube M1 and an NMOS tube M2; the gate of the NMOS tube M2 is the input end of the inverting amplifier U1; the source electrode of the NMOS tube M2 is grounded, the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is connected with a bias power supply Vb, the drain electrode of the NMOS tube M1 is the output end of the inverting amplifier U1, the drain electrode of the NMOS tube M1 is connected with one end of a resistor R01, and the other end of the resistor R01 is connected with a working power supply VDD; the inverting amplifier U2 comprises a resistor R02, an NMOS tube M3 and an NMOS tube M4; the threshold values of the starting voltages of the NMOS tube M3 and the NMOS tube M1 are the same; the threshold values of the starting voltages of the NMOS tube M4 and the NMOS tube M2 are the same; the resistance value of the resistor R02 is the same as that of the resistor R01; the gate of the NMOS tube M4 is the input end of the inverting amplifier U2; the source electrode of the NMOS tube M4 is grounded, the drain electrode of the NMOS tube M4 is connected with the source electrode of the NMOS tube M3, the grid electrode of the NMOS tube M3 is connected with the bias power supply Vb, the drain electrode of the NMOS tube M3 is the output end of the inverting amplifier U2, the drain electrode of the NMOS tube M3 is connected with one end of a resistor R02, and the other end of the resistor R02 is connected with the working power supply VDD.
The output current of the bias current source Ib is between zero and 1 microampere.
After the scheme is adopted, the transimpedance amplifier TIA1 is used for accessing an input signal, and the transimpedance amplifier TIA2 is not accessed by itself. The transimpedance amplifier TIA2 utilizes a negative feedback loop formed by an error amplifier and an NMOS tube Q2, so that the voltage of the input end and the voltage of the output end of the transimpedance amplifier TIA2 are identical to the voltage of the input end and the voltage of the output end of the transimpedance amplifier TIA1 when no input signal is input to the transimpedance amplifier TIA1, namely the transimpedance amplifier TIA2 copies the transimpedance amplifier TIA1 at the moment; the voltage at the input end and the voltage at the output end of the transimpedance amplifier TIA2 are equal to the voltage at the input end and the voltage at the output end of the transimpedance amplifier TIA1 when no input signal is input, then the gate voltage and the drain voltage of the NMOS transistor Q1 are also equal to the drain voltage and the drain voltage of the NMOS transistor Q2 respectively, and since the gate of the NMOS transistor Q1 is connected with the gate of the NMOS transistor Q2, it is known that the operating states of the NMOS transistor Q1 and the NMOS transistor Q2 are the same when the transimpedance amplifier TIA1 is not input.
According to the invention, when an input signal is input into the transimpedance amplifier TIA1, the grid voltage of the NMOS tube Q1 is unchanged, and the source voltage of the NMOS tube Q1 is gradually reduced along with the increase of the current of the input signal of the transimpedance amplifier TIA1, so that the NMOS tube Q1 is gradually conducted to shunt part of the current flowing through the input signal, and the output voltage of the transimpedance amplifier TIA1 is clamped within a certain range; when no input signal is input to the transimpedance amplifier TIA1, a micro current is output by controlling the bias current source Ib so that the NMOS tube Q2 is in a close-to-on state, and the NMOS tube Q1 is also in a close-to-on state at the moment, the source voltage of the NMOS tube Q1 only needs to be changed slightly so that the NMOS tube Q1 is fully conducted, and therefore, the NMOS tube Q1 can split partial current of the input signal, the change difference value of the source voltage of the NMOS tube Q1 is not required to reach the threshold value of the starting voltage of the NMOS tube Q1, and the response speed is high.
Comprehensively, the NMOS transistors Q1 and Q2 do not need to adopt devices with low starting voltage threshold, and the NMOS transistors Q1 and Q2 can also realize quick response of automatic gain control of the transimpedance amplifier TIA1 by adopting devices with common starting voltage threshold.
Drawings
FIG. 1 is an automatic gain control circuit for detecting the AC output amplitude of a transimpedance amplifier TIA;
FIG. 2 is an automatic gain control circuit for detecting the output DC level variation of a transimpedance amplifier TIA;
fig. 3 is a timing diagram of an optical signal received by the OLT;
FIG. 4 is a timing diagram of a GPON burst packet;
fig. 5 is a first circuit diagram of a conventional burst AGC control circuit;
fig. 6 is a second circuit diagram of a conventional burst AGC control circuit;
FIG. 7 is a general schematic of the present invention;
fig. 8 is a schematic diagram of a specific circuit of the present invention.
Detailed Description
In order to further explain the technical scheme of the invention, the invention is explained in detail by specific examples.
Referring to FIG. 7, the invention discloses an automatic gain control circuit of a transimpedance amplifier, which comprises a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS tube Q1, an NMOS tube Q2, an error amplifier U3 and a bias current source Ib; the circuit structures, the device sizes and the process parameters of the transimpedance amplifier TIA2 and the transimpedance amplifier TIA1 are the same; the threshold of the turn-on voltage of the NMOS transistor Q1 is the same as that of the turn-on voltage of the NMOS transistor Q2. Wherein the transimpedance amplifier TIA1 may comprise an inverting amplifier U1 and a resistor R1; and the transimpedance amplifier TIA2 comprises an inverting amplifier U2 and a resistor R2; the input end and the output end of the inverting amplifier U1 are respectively connected with the two ends of the resistor R1; the input end of the inverting amplifier U1 is the input end of the transimpedance amplifier TIA1, and the output end of the inverting amplifier U1 is the output end of the transimpedance amplifier TIA 1; the input end and the output end of the inverting amplifier U2 are respectively connected with the two ends of the resistor R2; the input end of the inverting amplifier U2 is the input end of the transimpedance amplifier TIA2, and the output end of the inverting amplifier U2 is the output end of the transimpedance amplifier TIA 2.
Specifically, the input end of the transimpedance amplifier TIA1 is connected with the drain electrode of the NMOS tube Q1; the output end of the transimpedance amplifier TIA1 is connected with the source electrode of the NMOS tube Q1; the input end of the transimpedance amplifier TIA2 is connected with the drain electrode of the NMOS tube Q2; the output end of the transimpedance amplifier TIA2 is connected with the source electrode of the NMOS tube Q2; the non-inverting input end and the inverting input end of the error amplifier U2 are respectively connected with the input end and the output end of the transimpedance amplifier TIA 2; the output end of the error amplifier U2 is connected with the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2; the input end of the bias current source Ib is connected with the working power supply VDD, and the output end of the bias current source Ib is connected with the non-inverting input end of the error amplifier U2 and the drain electrode of the MOS tube Q2.
In order to facilitate understanding of the inverting amplifier U1 and the inverting amplifier U2, the specific structures of the inverting amplifier U1 and the inverting amplifier U2 are specifically described below, and it should be noted that the technical idea of the present invention may be applied to other types of inverting amplifier U1 and inverting amplifier U2, and is not limited to the inverting amplifier U1 and the inverting amplifier U2 described below.
Referring to fig. 8, the inverting amplifier U1 is a cascode amplifier, and the inverting amplifier U1 includes a resistor R01, an NMOS transistor M1, and an NMOS transistor M2; the gate of the NMOS tube M2 is the input end of the inverting amplifier U1; the source electrode of the NMOS tube M2 is grounded, the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is connected with the bias power supply Vb, the drain electrode of the NMOS tube M1 is the output end of the inverting amplifier U1, the drain electrode of the NMOS tube M1 is connected with one end of a resistor R01, and the other end of the resistor R01 is connected with the working power supply VDD.
Referring to fig. 8, the inverting amplifier U2 is a cascode amplifier, and the inverting amplifier U2 includes a resistor R02, an NMOS transistor M3, and an NMOS transistor M4; the threshold values of the starting voltages of the NMOS tube M3 and the NMOS tube M1 are the same; the threshold values of the starting voltages of the NMOS tube M4 and the NMOS tube M2 are the same; the resistance value of the resistor R02 is the same as that of the resistor R01; the gate of the NMOS tube M4 is the input end of the inverting amplifier U2; the source electrode of the NMOS tube M4 is grounded, the drain electrode of the NMOS tube M4 is connected with the source electrode of the NMOS tube M3, the grid electrode of the NMOS tube M3 is connected with the bias power supply Vb, the drain electrode of the NMOS tube M3 is the output end of the inverting amplifier U2, the drain electrode of the NMOS tube M3 is connected with one end of a resistor R02, and the other end of the resistor R02 is connected with the working power supply VDD.
The transimpedance amplifier TIA1 of the present invention is used to tap in an input signal, while the transimpedance amplifier TIA2 itself has no input signal tap in. The two paths of negative feedback loops formed by the error amplifier and the NMOS tube Q2 are almost equal to the input end voltage of the transimpedance amplifier TIA2 (namely the drain voltage of the NMOS tube Q2) and the output end voltage of the transimpedance amplifier TIA2 (namely the source voltage of the NMOS tube Q2) according to the principle of 'virtual short' of negative feedback; when no input signal is input to the transimpedance amplifier TIA1, the input end voltage (namely the drain voltage of the NMOS transistor Q1) of the transimpedance amplifier TIA1 is equal to the output end voltage (namely the source voltage of the NMOS transistor Q1) of the transimpedance amplifier TIA1, so that the input end voltage and the output end voltage of the transimpedance amplifier TIA2 are equal to the input end voltage and the output end voltage of the transimpedance amplifier TIA1 when no input signal is input, then the gate voltage and the drain voltage of the NMOS transistor Q1 are equal to the drain voltage and the drain voltage of the NMOS transistor Q2 respectively, and the gate of the NMOS transistor Q1 is connected with the gate of the NMOS transistor Q2, so that the working states of the NMOS transistor Q1 and the NMOS transistor Q2 are the same when the transimpedance amplifier TIA1 is not input; the gate voltage of the NMOS transistor Q2 satisfies the following formula:
V G_Q2 =V S_Q2 +V GS_Q2 = V S_Q2 +[(2I d L)/ (μC ox W)] 0.5 +V th; ;
wherein: v (V) G_Q2 The gate voltage of the NMOS transistor Q2; v (V) S_Q2 The source voltage of the NMOS tube Q2; v (V) GS_Q2 Is the voltage drop between the gate and source of NMOS transistor Q2; i d Is the current flowing through the NMOS transistor Q2; l is the channel length of the NMOS transistor Q2; w is the channel width of the NMOS transistor Q2; μ is the electron transfer rate; c (C) ox The unit area gate oxide capacitance of the NMOS transistor Q2; v (V) th The threshold value of the starting voltage of the NMOS tube Q1 and the NMOS tube Q2;
and I d For a component of the output current of the bias current source Ib, if the output current of the bias current source Ib is controlled to be sufficiently close to zero, e.g. the output current of the bias current source Ib is between zero and 1 microampere, then I d Can be considered zero, at which point:
V G_Q2 =V S_Q2 +V GS_Q2 = V S_Q2 +V th ；
V GS_Q2 = V th，
therefore, when the output current of the bias current source Ib is close to zero, the NMOS transistor Q2 is in a critical on state; when the transimpedance amplifier TIA1 is not input, the working states of the NMOS tube Q1 and the NMOS tube Q2 are the same, so when the transimpedance amplifier TIA1 is not input, the output current of the bias current source Ib is close to zero enough, and the NMOS tube Q1 is in a close-to-on state.
According to the invention, when an input signal is input into the transimpedance amplifier TIA1, the grid voltage of the NMOS tube Q1 is unchanged, and the source voltage of the NMOS tube Q1 is gradually reduced along with the increase of the current of the input signal of the transimpedance amplifier TIA1, so that the NMOS tube Q1 is gradually conducted to shunt part of the current flowing through the input signal, and the output voltage of the transimpedance amplifier TIA1 is clamped within a certain range; when no input signal is input to the transimpedance amplifier TIA1, the NMOS tube Q2 and the NMOS tube Q1 can be in a close conduction state by controlling the bias current source Ib to output a micro current, so that when the input signal is input to the transimpedance amplifier TIA1, the source voltage of the NMOS tube Q1 can be completely conducted by only small change, the NMOS tube Q1 can split partial current of the input signal, the change difference value of the source voltage of the NMOS tube Q1 is not required to reach the threshold value of the starting voltage of the NMOS tube Q1, and the response speed is high.
Comprehensively, the NMOS transistors Q1 and Q2 do not need to adopt devices with low starting voltage threshold, and the NMOS transistors Q1 and Q2 can also realize quick response of automatic gain control of the transimpedance amplifier TIA1 by adopting devices with common starting voltage threshold.
The above examples and drawings are not intended to limit the form or form of the present invention, and any suitable variations or modifications thereof by those skilled in the art should be construed as not departing from the scope of the present invention.
Claims (4)
1. An automatic gain control circuit of a transimpedance amplifier, which is characterized in that: the amplifier comprises a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS tube Q1, an NMOS tube Q2, an error amplifier U3 and a bias current source Ib; the circuit structures, the device sizes and the process parameters of the transimpedance amplifier TIA2 and the transimpedance amplifier TIA1 are the same; the starting voltage threshold values of the NMOS tube Q1 and the NMOS tube Q2 are the same;
the input end of the transimpedance amplifier TIA1 is connected with the drain electrode of the NMOS tube Q1; the output end of the transimpedance amplifier TIA1 is connected with the source electrode of the NMOS tube Q1;
the input end of the transimpedance amplifier TIA2 is connected with the drain electrode of the NMOS tube Q2; the output end of the transimpedance amplifier TIA2 is connected with the source electrode of the NMOS tube Q2;
the non-inverting input end and the inverting input end of the error amplifier U2 are respectively connected with the input end and the output end of the transimpedance amplifier TIA 2; the output end of the error amplifier U2 is connected with the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2;
the input end of the bias current source Ib is connected with the working power supply VDD, and the output end of the bias current source Ib is connected with the non-inverting input end of the error amplifier U2 and the drain electrode of the MOS tube Q2; when the output current of the bias current source Ib is close to zero, the NMOS transistor Q2 is in a critical on state.
2. The automatic gain control circuit of a transimpedance amplifier according to claim 1, wherein: the transimpedance amplifier TIA1 comprises an inverting amplifier U1 and a resistor R1; the transimpedance amplifier TIA2 comprises an inverting amplifier U2 and a resistor R2;
the input end and the output end of the inverting amplifier U1 are respectively connected with the two ends of the resistor R1; the input end of the inverting amplifier U1 is the input end of the transimpedance amplifier TIA1, and the output end of the inverting amplifier U1 is the output end of the transimpedance amplifier TIA 1;
the input end and the output end of the inverting amplifier U2 are respectively connected with the two ends of the resistor R2; the input end of the inverting amplifier U2 is the input end of the transimpedance amplifier TIA2, and the output end of the inverting amplifier U2 is the output end of the transimpedance amplifier TIA 2.
3. A transimpedance amplifier automatic gain control circuit according to claim 2, wherein: the inverting amplifier U1 comprises a resistor R01, an NMOS tube M1 and an NMOS tube M2;
the gate of the NMOS tube M2 is the input end of the inverting amplifier U1; the source electrode of the NMOS tube M2 is grounded, the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is connected with a bias power supply Vb, the drain electrode of the NMOS tube M1 is the output end of the inverting amplifier U1, the drain electrode of the NMOS tube M1 is connected with one end of a resistor R01, and the other end of the resistor R01 is connected with a working power supply VDD;
the inverting amplifier U2 comprises a resistor R02, an NMOS tube M3 and an NMOS tube M4; the threshold values of the starting voltages of the NMOS tube M3 and the NMOS tube M1 are the same; the threshold values of the starting voltages of the NMOS tube M4 and the NMOS tube M2 are the same; the resistance value of the resistor R02 is the same as that of the resistor R01;
the gate of the NMOS tube M4 is the input end of the inverting amplifier U2; the source electrode of the NMOS tube M4 is grounded, the drain electrode of the NMOS tube M4 is connected with the source electrode of the NMOS tube M3, the grid electrode of the NMOS tube M3 is connected with the bias power supply Vb, the drain electrode of the NMOS tube M3 is the output end of the inverting amplifier U2, the drain electrode of the NMOS tube M3 is connected with one end of a resistor R02, and the other end of the resistor R02 is connected with the working power supply VDD.
4. The automatic gain control circuit of a transimpedance amplifier according to claim 1, wherein: the output current of the bias current source Ib is between zero and 1 microampere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810183064.8A CN108199696B (en) | 2018-03-06 | 2018-03-06 | Automatic gain control circuit of transimpedance amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810183064.8A CN108199696B (en) | 2018-03-06 | 2018-03-06 | Automatic gain control circuit of transimpedance amplifier |
Publications (2)
| Publication Number | Publication Date |
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| CN108199696A CN108199696A (en) | 2018-06-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019169566A1 (en) * | 2018-03-07 | 2019-09-12 | 厦门优迅高速芯片有限公司 | Automatic gain control circuit of transimpedance amplifier |
| US10804859B2 (en) * | 2018-12-10 | 2020-10-13 | Analog Devices, Inc. | Transimpedance amplifiers with feedforward current |
| CN110086433A (en) * | 2019-02-20 | 2019-08-02 | 厦门优迅高速芯片有限公司 | A kind of burst trans-impedance amplifier with reset signal |
| CN110492945B (en) * | 2019-08-21 | 2021-05-07 | 武汉华工正源光子技术有限公司 | ROF optical receiving module with stable output amplitude |
| CN113452334B (en) * | 2021-07-12 | 2024-10-18 | 江苏科大亨芯半导体技术有限公司 | Fast response automatic gain control method for transimpedance amplifier |
| CN113726339B (en) * | 2021-08-19 | 2022-06-03 | 江苏润石科技有限公司 | Error feedback-based offset voltage reduction method and data converter |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11239108A (en) * | 1998-02-24 | 1999-08-31 | Toshiba Corp | Optical reception circuit |
| EP1032145A2 (en) * | 1999-02-26 | 2000-08-30 | Nec Corporation | Automatic gain switching-type burst optical signal receiving circuit |
| JP2005020138A (en) * | 2003-06-24 | 2005-01-20 | Sony Corp | Current/voltage converter circuit and optical receiver |
| TWI236211B (en) * | 2004-07-28 | 2005-07-11 | Ind Tech Res Inst | High frequency amplifier |
| JP2009049488A (en) * | 2007-08-14 | 2009-03-05 | Nippon Telegr & Teleph Corp <Ntt> | Preamplifier circuit |
| JP2009225216A (en) * | 2008-03-18 | 2009-10-01 | Nippon Telegr & Teleph Corp <Ntt> | Transimpedance amplifier connection circuit |
| US7961053B1 (en) * | 2009-12-23 | 2011-06-14 | Infinera Corporation | Integrated circuit having a dummy transimpedance amplifier |
| JP2012104948A (en) * | 2010-11-08 | 2012-05-31 | Renesas Electronics Corp | Amplification circuit |
| CN105207634A (en) * | 2015-09-18 | 2015-12-30 | 厦门优迅高速芯片有限公司 | Burst-type automatic gain control circuit controlled bit by bit |
| CN106031059A (en) * | 2014-03-03 | 2016-10-12 | 松下知识产权经营株式会社 | light receiving circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2311434C (en) * | 2000-06-13 | 2004-10-19 | Ibm Canada Limited-Ibm Canada Limitee | Differential photoelectric receiver circuit |
| US6792252B2 (en) * | 2002-02-06 | 2004-09-14 | Telefonaktiebolaget Lm Ericsson (Publ) | Wideband error amplifier |
| US7309852B2 (en) * | 2004-10-18 | 2007-12-18 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd. | Variable noise control for an optical transducer |
-
2018
- 2018-03-06 CN CN201810183064.8A patent/CN108199696B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11239108A (en) * | 1998-02-24 | 1999-08-31 | Toshiba Corp | Optical reception circuit |
| EP1032145A2 (en) * | 1999-02-26 | 2000-08-30 | Nec Corporation | Automatic gain switching-type burst optical signal receiving circuit |
| JP2005020138A (en) * | 2003-06-24 | 2005-01-20 | Sony Corp | Current/voltage converter circuit and optical receiver |
| TWI236211B (en) * | 2004-07-28 | 2005-07-11 | Ind Tech Res Inst | High frequency amplifier |
| JP2009049488A (en) * | 2007-08-14 | 2009-03-05 | Nippon Telegr & Teleph Corp <Ntt> | Preamplifier circuit |
| JP2009225216A (en) * | 2008-03-18 | 2009-10-01 | Nippon Telegr & Teleph Corp <Ntt> | Transimpedance amplifier connection circuit |
| US7961053B1 (en) * | 2009-12-23 | 2011-06-14 | Infinera Corporation | Integrated circuit having a dummy transimpedance amplifier |
| JP2012104948A (en) * | 2010-11-08 | 2012-05-31 | Renesas Electronics Corp | Amplification circuit |
| CN106031059A (en) * | 2014-03-03 | 2016-10-12 | 松下知识产权经营株式会社 | light receiving circuit |
| CN105207634A (en) * | 2015-09-18 | 2015-12-30 | 厦门优迅高速芯片有限公司 | Burst-type automatic gain control circuit controlled bit by bit |
Non-Patent Citations (1)
| Title |
|---|
| 一种宽动态范围跨阻放大器的设计;杨赟秀,邓世杰,卢星;半导体光电;全文 * |
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