CN108199581B - Power supply and method for providing an output voltage - Google Patents
Power supply and method for providing an output voltage Download PDFInfo
- Publication number
- CN108199581B CN108199581B CN201810150409.XA CN201810150409A CN108199581B CN 108199581 B CN108199581 B CN 108199581B CN 201810150409 A CN201810150409 A CN 201810150409A CN 108199581 B CN108199581 B CN 108199581B
- Authority
- CN
- China
- Prior art keywords
- voltage
- counter
- offset
- target
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000007704 transition Effects 0.000 description 23
- 238000010586 diagram Methods 0.000 description 16
- 239000003990 capacitor Substances 0.000 description 14
- 230000007423 decrease Effects 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000012508 change request Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Images
Landscapes
- Control Of Voltage And Current In General (AREA)
- Dc-Dc Converters (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to a power supply and a method for providing an output voltage, and provides a system and a method for digital voltage compensation in a power supply integrated circuit. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a current first digital count corresponding to a current voltage code value to a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method further includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.
Description
The application is a divisional application with the application date of "10.8.2013", the application number of "201310464431.9", entitled "digital voltage compensation for power integrated circuits".
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the right to priority from U.S. provisional application No. 61/792,745, filed on 3/15/2013, the disclosure of which is incorporated herein by reference.
Technical Field
The present disclosure relates generally to power supplies for processing units, and more particularly to systems and methods for reducing hysteresis in transitions between different voltage levels, where the voltages are supplied by the power supplies.
Background
Controllers for Central Processing Units (CPUs) typically operate with a custom specified output impedance. For example, as the current increases, the output voltage (Vout) of the power supply decreases from the request (VID) voltage in a controlled manner. When the controller is required to change its VID voltage, the extra load current is either sourced out to the output filter capacitor (VID up) or sunk from the filter capacitor (VID down). However, the controller cannot distinguish this extra current from the normal load circuit, resulting in hysteresis and rounding of the vout. Sometimes the allowable time to transition to the new VID voltage is specified by the design requirements of the CPU and a signal is sent to the CPU indicating that the transition between different voltage levels is complete. If Vout is sluggish, the CPU will apply a high current load to the unprepared Vout, causing the Vout to drop below the requested voltage.
Disclosure of Invention
Systems and methods for digital voltage compensation in power supply integrated circuits are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a current first digital count corresponding to a current voltage code value to a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method further includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.
Drawings
Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered to be limiting in scope, the exemplary embodiments will be described with additional specificity and detail through use of the accompanying drawings, in which:
FIG. 1 is a block diagram of a switching voltage regulator for managing voltage provided to a processor in one embodiment described in the present disclosure;
FIG. 2 is a schematic diagram of a power supply circuit in one embodiment described in the present disclosure;
FIGS. 3A and 3B are diagrams illustrating different voltages provided by a prior art power supply circuit in response to a voltage requested by a processor;
fig. 4A and 4B are diagrams illustrating compensation voltages provided by a power supply circuit in response to a processor requested voltage in one embodiment described in the present disclosure; and
fig. 5 is a flow chart of a method of providing a voltage in response to a digital voltage code in one embodiment described in the present disclosure.
In accordance with common practice, the various components described are not drawn to scale but are drawn to emphasize specific components relevant to the exemplary embodiments.
Description of the main elements in the figures
100 switching regulator
102 processor
104 digital-to-analog converter (DAC)
106 error amplifier and compensation circuit
108 falling circuit
109 offset counter
110 modulator
111 output filter
113 control circuit
115 normal counter
117 power switch
200 switch voltage regulator
206 error amplifier and compensation circuit
208 falling circuit
210 modulator
212 feedback voltage signal
214 feedback resistor
216 resistor
217 electric power switch
218 capacitor
220 feedback node
222 resistor
224 capacitor
226 capacitor
228 error control signal
230 amplifier
300A diagram
300B diagram
302 requested VID
304A supplied voltage
304B is supplied with
306 high voltage level
308 low voltage level
402 requested VID
404A, and a voltage supplied by the voltage supply circuit
404B, supplied with a voltage
406 voltage level
408 voltage level
410 offset
412 linear countdown
414 exponential countdown
500 method
502 method
504 method
506 method
508 method
510 method
514 method
516 method
518 method
Detailed Description
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. However, it is understood that other implementations may be used and that logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the figures and detailed description should not be construed as limiting the order in which individual steps may be implemented. The following detailed description is, therefore, not to be taken in a limiting sense.
Power supply circuits that provide a core supply voltage to a Central Processing Unit (CPU) typically operate with a specified output impedance, i.e., as the load current increases, the output voltage decreases from the requested voltage in a controlled manner. When the power supply circuit is required to change the supplied voltage to a new value, additional load current is sourced out of or sunk from the capacitor in the output filter as needed to charge or discharge the capacitor. The power supply circuit may not be able to distinguish this additional current from the normal load circuit, causing hysteresis and rounding of the output voltage as it moves to the new voltage value. The CPU manufacturer may specify that the allowable time be moved to the new voltage and may impose a requirement to cause the power supply circuit to send a signal to the CPU indicating that the new voltage is being supplied as if no additional current were being supplied within the allowable time. If the voltage has already been hysteretic while the current load to the CPU of the power supply increases, corresponding to a higher target core voltage, a lower (hysteretic) output voltage will cause the output voltage to drop below the minimum voltage required for the CPU to function properly.
The power supply circuit typically contains control circuitry including registers to hold digital codes corresponding to the requested supply voltage; a counter to feed a digital-to-analog converter (DAC), wherein the DAC generates a reference to an output voltage; and a digital component to determine the relative values of the register and the counter. When a requested voltage code (VID) is received that is higher than the existing DAC counter output, the counter starts counting (by a clock signal) until its digital output equals the contents of the register (holding the code corresponding to the requested supply output voltage). As discussed below, according to an implementation of the present invention, an offset is added to the count at the beginning of the up-transition, and the offset count feeds a DAC that drives a reference voltage. When the normal count reaches the target value such that it equals the register, the offset count is counted down to zero. The addition of the offset does not cause a hysteresis in the power supply output voltage when the VID code adjusts the output voltage upward, and thus does not cause any undesirable undershoot when the VID code adjusts the power supply output voltage downward.
Fig. 1 is a block diagram of a switching voltage regulator 100 for managing power supplied to a processor 102. Processor 102 may be any device configured to execute machine-readable instructions. For example, the processor 102 may function as a CPU and the terms CPU and processor may be used as such, both above and below. When executing instructions, processor 102 consumes power provided to processor 102 by switching voltage regulator 100. In some implementations, the amount of power consumed by the processor 102 depends on the computational load (i.e., clock speed) of the processor 102. For example, when the processor 102 is required to execute many instructions for a short period of time, the processor 102 may require a higher supply voltage and may consume more power than when the processor 102 is in an idle state. In some implementations, to perform the calculation, the processor 102 requests an increase in the voltage provided by the switching voltage regulator 100 before it increases its clock speed. In addition, the increase in voltage may have an associated time period within which the switching voltage regulator 100 will provide the increased voltage. If the increased supply voltage is not provided to the processor 102 within the time limit, instruction execution by the processor 102 may be disrupted.
In at least one implementation, when the processor requests a voltage increase, the processor 102 sends a digital Voltage (VID) request to the switching voltage regulator 100, which passes the digital VID request to a control circuit 113 that controls a digital-to-analog converter (DAC) 104. The digital VID request requires a particular voltage level from the power supply circuit 100. In response to the digital VID request, control circuit 113 instructs DAC104 to send an analog representation of the digital VID request as a reference voltage to error amplifier and compensation circuit 106. In addition to the analog reference voltage received from DAC104, error amplifier and compensation circuit 106 also receives a droop current from block 108, where the droop current is a current proportional to the sum of the load currents used by processor 102 and may include the current required to charge or discharge the filter capacitors in output filter 111 during the programmed output voltage change. As the error amplifier and compensation circuit 106 receives the droop current from 108, the output voltage of the switching voltage regulator 100 decreases in a controlled manner as the droop current increases. Due to the current required to charge or discharge the output capacitor of the output filter 111 when the supply voltage vout changes corresponding to the VID changes issued by the processor 102, additional droop current is sourced out of the droop circuit 108 to the circuit 106 or sunk from the circuit 106. Because the error amplifier and compensation circuit 106 cannot distinguish between changes in the droop current because changes in the programmed vout from the normal droop current change due to load current changes, the switching voltage regulator 100 output vout lags and rounds off when vout changes according to the requested VID changes from the processor 102. In the case of a rising request voltage, the hysteresis and rounding due to the falling current 108 may cause the switching voltage regulator 100 to immediately provide a voltage less than the request voltage and may cause the execution instructions to be corrupted. In the case of a reduced request voltage, the hysteresis and rounding will cause the processor to temporarily consume more power to execute instructions than necessary, but the hysteresis during the adjustment of the down V output will not cause disruption to the processor operation. The voltage provided by the error amplifier and compensation circuit 106 is input to a modulator 110, typically a pulse width modulator PWM. The modulator 110 controls a power switch 117, which provides the phase voltages. The phase voltages are filtered by an output filter 111 that generates a Vout output voltage to processor 102. In addition, the power switch 117 and the output filter 111 are coupled to the power V input of the external system.
To prevent the switching voltage regulator 100 from lagging and rounding in response to an upward change in the requested voltage, the data sent by the control circuit 113 to the DAC104 is offset so that the voltage reference provided to the error amplifier and compensation circuit 106 reaches and exceeds the requested target voltage (i.e., it overshoots the target reference voltage corresponding to the new VID code) before the time required for the output voltage to reach the target voltage. For example, when the processor 102 requests a new VID that is higher than the previous VID, the control circuit 113 in the switching voltage regulator 100 receives the requested VID and may initialize two counters: a normal (VID) counter and an offset counter 109. The offset counter 109 output is added to the normal counter 115, which is sent to the DAC104 to control the reference voltage provided by the DAC 104. The normal counter 115 counts to the requested new target voltage and then stops. The offset counter 109 may be a fixed value when the normal counter 115 is counting, and the offset counter 109 starts counting down to zero when the normal counter 115 reaches a target value. Thus, the digital count provided by the control circuit 113 to the DAC104 and the analog reference provided by the DAC104 to the error amplifier and compensation circuit 106 is a voltage that begins at a higher (offset) value than the reference voltage and reaches a value that exceeds the requested final target voltage before the VID codes begin to change, and then dips back down to the requested target voltage when the VID begins to change. With the offset properly chosen, the output voltage of switching voltage regulator 100 reaches the requested target voltage within the requested time, slightly overshoots the requested target voltage, and transitions back to the requested target voltage. The same function may be performed for requested VID values that are lower than the current voltage value. When the processor 102 requests a voltage lower than the currently received voltage, the control circuit 113 subtracts the offset count from the normal counter 115 and provides a new count to the DAC104, and when the normal counter 115 reaches a target value, the offset count is decremented towards zero. Due to the offset, the reference voltage provided by the DAC104 becomes lower than the final target voltage and then jumps back to the target voltage. Because some systems may be extremely sensitive to excessively low output voltages, a smaller offset (or no offset) may be used when the voltage transitions from a higher voltage to a lower voltage.
Fig. 2 is a schematic diagram of an exemplary switching voltage regulator 200. As illustrated, the error amplifier and compensation circuit 206 provides a more detailed diagram of the error amplifier and compensation circuit 106 of fig. 1. The other circuits correspond to the circuits similarly named in fig. 1. That is, 202 corresponds to 102, 204 corresponds to 104, 208 corresponds to 108, 209 corresponds to 109, 210 corresponds to 110, 211 corresponds to 111, 213 corresponds to 113, 215 corresponds to 115, and 217 corresponds to 117.
In some implementations, the error amplifier and compensation circuit 206 receives three inputs and outputs a control signal 228 to the modulator 210. The three inputs are the reference voltage from the DAC 204, the droop current from 208, and the feedback voltage signal 212 (vout) from the output of the switching voltage regulator 200. The error amplifier and compensation circuit 206 and modulator 210 use three inputs to adjust the switching frequency and/or pulse width of the power switch 217 to maintain an output voltage that approximately corresponds to the reference value supplied by the DAC 204. The error amplifier and compensation circuit 206 may control the gain and phase characteristics to meet the desired accuracy and response time of providing power to the load. In some embodiments, error amplifier 230 is part of an integrated controller circuit and the resistors and capacitors of error amplifier and compensation circuit 206 are external components. In other embodiments, the resistors and capacitors of the error amplifier and compensation circuit 206 are also part of the integrated controller circuit.
In at least one implementation, the error amplifier 230 may be a differential amplifier that receives the reference voltage from the DAC 204 and amplifies the difference between the reference voltage and the voltage at the feedback node 220. The error amplifier and compensation circuit 206 components may include resistors 214, 216, and 222 and capacitors 218, 224, and 226. To reduce the output voltage as a function of the output current, the falling current from 208 is passed through a feedback resistor 214. The higher droop current from 208 (corresponding to a higher regulator output current) increases the voltage drop across resistor 216, resulting in a lower output voltage vout. The compensation circuit of the error amplifier and compensation circuit 206 is a single implementation of possible compensation circuits in the error amplifier and compensation circuit 206. Those skilled in the art will appreciate that many other implementations of the compensation circuit are possible and contemplated herein.
In some prior art implementations, a power supply circuit (such as switching voltage regulator 100) may not adequately compensate or overcompensate for excess droop current when Vout changes due to a requested VID code change from a processor or other device requesting a voltage change. Fig. 3A and 3B are diagrams illustrating a comparison of an output voltage provided by a power supply circuit with a requested VID from a processor. For example, FIG. 3A is a diagram 300A illustrating a voltage 304A provided by an insufficiently compensated power supply circuit in response to a requested VID 302 requesting both a higher voltage level 308 and a lower voltage level 306. As shown in FIG. 3A, when the power supply circuit does not adequately compensate (or does not compensate at all) for the falling current change caused by the Vout change, and the requested VID 302 rises from a low voltage level 308 to a high voltage level 306, the supplied output voltage 304A lags behind the requested VID 302, such that the supplied voltage 304A is less than the requested VID 302 for a period of time as the requested VID 302 moves from the low voltage level 308 to the high voltage level 306. Because the supplied voltage 304A is less than the requested VID 302, the operation of the processor may be negatively affected. Conversely, when the requested VID moves from the high voltage level 306 to the low voltage level 308, the provided voltage 304A still lags the requested VID 302, but since the requested VID moves from the high voltage level 306 to the low voltage level 308, the provided voltage 304A lags the requested VID 302 causing the provided voltage 304A to be higher than the requested VID 302. When the supplied voltage 304A is higher than the requested VID 302, the processor is able to function properly but will draw temporarily more power than is needed or desired.
In an alternative prior art implementation, with prior art R-C based compensation between the inverting input of the error amplifier and ground, the output voltage may be overcompensated. FIG. 3B is a diagram 300B illustrating the voltage 304B provided by such an overcompensated power supply circuit in response to a requested VID 302 requesting both a higher voltage level 308 and a lower voltage level 306. As shown in fig. 3B, where the power supply circuit overcompensates for a falling current change, causing the vout to change due to a VID code change, the requested VID 302 rises from a low voltage level 308 to a high voltage level 306, and the supplied voltage 304B rises with the requested VID 302 but overshoots the high voltage level 306 by rising to a voltage level above the high voltage level 306 and then transitioning down back to the high voltage level 306. In contrast to the insufficiently compensated power supply circuit of FIG. 3A, by overshooting the high voltage level 306, the voltage 304B provided when the requested VID 302 transitions from the low voltage level 308 to the high voltage level 306 is equal to or higher than the requested VID 302. Because the provided voltage 304B is higher than the requested VID 302, the performance of the processor receiving the provided voltage 304B is not adversely affected. Conversely, over-compensated power supply circuits may negatively impact processor performance when the requesting VID 302 transitions from a high voltage level 306 to a low voltage level 308. For example, because the provided voltage 304B is provided by an overcompensated power supply circuit, the provided voltage 304B undershoots the low voltage level 308 to a voltage level that is lower than the low voltage level 308. Because the supplied voltage 304B undershoots the low voltage level 308, the performance of the processor may suffer when the requesting VID 302 transitions from the high voltage level 306 to the low voltage level 308.
In some prior art implementations, as shown in the compensation circuit 206 in fig. 2, adding external discrete components to an insufficiently compensated system changes the system to an overcompensated system. For example, if the series resistor/capacitor combination is connected from the feedback node 220 to ground, then the added circuitry will sink current from 220 or source current out into 220 during the voltage transition as 220 moves higher or lower to follow the increase or decrease in DAC 204 voltage. However, the same compensation is added as the DAC 204 voltage increases or decreases. For example, if the system response is as in fig. 3A and the appropriate series resistor/capacitor combination is added to achieve the desired response of fig. 3B in the upward direction, the system will also give an undesirable undershoot response in the downward direction of fig. 3B.
The DAC offset method of the present invention described above with respect to fig. 1 may be used to ensure that the voltage provided by the power supply circuit is equal to or greater than the voltage corresponding to the VID codes from the processor during the upward transition, or more closely follows the desired downward transition, due to the effect of the reduced current caused by the change in the programmed vout when the power supply circuit is not adequately compensated or is not compensated. Fig. 4A and 4B are diagrams illustrating a comparison of a voltage provided by a power supply circuit with a reference voltage corresponding to a VID code from a processor when the power supply circuit receives the reference voltage from a DAC (including a DAC offset according to the present invention).
FIG. 4A is a diagram illustrating an implementation of the DAC offset with the voltage 404A provided by the power supply circuit when the requested VID 402 transitions from a low voltage level 408 to a high voltage level 406. As shown, an offset 410 is added to the provided voltage 404A by the DAC when the requested VID 402 begins to transition from a low voltage level 408 to a high voltage level 406. In at least one implementation, the offset 410 exists as an offset count that is added to the normal count that begins counting from a low VID value corresponding to the voltage level 408 to a high VID value corresponding to the voltage level 406. When the normal count reaches a high level corresponding to voltage level 406, the DAC begins to count down the offset count toward zero. By applying the offset 410, the provided voltage 404A overshoots the voltage requested by the processor or other device such that the provided voltage 404A is higher than the requested VID 402.
In some implementations, the offset increases as the VID code of the request changes (Δ VI)D) But is increased so that the offset 410 may be calculated to be equal to K1+K2Δ VID where K1Is the programmed offset, K2Is the programming gain and avid is the difference between the VID code corresponding to the high voltage level 406 and the VID code corresponding to the low voltage level 408. Additionally, when the offset 410 is counting down to zero, the offset may be driven to zero using a linear countdown 412 or an exponential countdown 414. Alternative countdown methods (functions) known to those skilled in the art to count down the offset count toward zero are also contemplated. In some implementations, when the offset is linearly counted down, there is a risk that the supplied voltage 404A may become smaller than the requested VID 402. By transitioning the offset count exponentially to zero, the risk of the provided voltage 404A becoming less than the requested VID 402 is reduced. Additionally, in certain embodiments, the offset 410 is limited to within a certain value.
FIG. 4B is a diagram illustrating an implementation of a DAC offset according to the present invention with a voltage 404B provided by the power supply circuit when the requested VID 402 transitions from a high value corresponding to a high voltage level 406 to a low value corresponding to a voltage level 408. As shown, a negative offset 410 is added to the provided voltage 404b by the DAC when the requesting VID 402 begins to transition from a high voltage level 406 to a low voltage level 408. In at least one implementation, the offset 410 exists as an offset count that is subtracted from the normal count that begins counting from high to low. When the normal count reaches a low level corresponding to voltage level 408, the DAC begins counting the offset count back toward zero. By applying the offset 410, the supplied voltage 404B can move faster toward the low voltage level 408. Likewise, a linear countdown 412, an exponential countdown 414, and the like may be used to return a negative offset count to zero when the requesting VID 402 transitions from the high voltage level 406 to the low voltage level 408. In the event that undershoot is undesirable, the negative offset applied in the downward VID code adjustments may be eliminated (i.e., the offset is applied only during the upward VID code adjustments) or alternatively, the countdown of the offset counter may begin before the VID counter reaches a lower target value corresponding to the V-output target level 408.
Fig. 5 is a flow diagram of a method 500 for offsetting a DAC reference voltage provided to an error amplifier. To offset the DAC reference voltage, method 500 begins at 502, where a digital voltage change request is received. For example, the processor sends the new VID code to the control circuit. The method 500 then proceeds to 504 where a digital offset is calculated based on a comparison of the new VID code to the existing VID code corresponding to the existing DAC voltage. The method 500 then proceeds to 506, where a digital offset is used to preset an offset counter and the digital offset is added to the value of the VID counter, which then begins counting toward its new target value corresponding to the new VID code. The value of the sum of the VID counter and the offset counter is used by the DAC to provide the analog reference voltage. In addition, the VID (Normal) counter is incremented or decremented based on whether the digital voltage request (new VID code) transitions to a higher or lower value (corresponding to a higher or lower new target output voltage).
In at least one example embodiment, the method 500 proceeds to 508 to determine whether the VID counter output value and the new VID target value are equal to each other. If the VID counter output value and the target value are not equal to each other, then the method 500 proceeds to 510 where the VID counter counts to the new target value. If the output value of the VID counter and the new target value are equal to each other, then the method 500 proceeds to 512 where the VID counter is stopped and the offset counter is decremented towards zero. Accordingly, method 500 proceeds to 514 to determine whether the offset counter is equal to zero. If the offset count is not equal to zero, then method 500 proceeds to 516, where the offset count is counted (decremented) toward zero. If the offset count is equal to zero, then the method 500 proceeds to 518, where a new target value corresponding to the new VID code is provided to the DAC, where the power supply circuit then provides the requested voltage to the processor. Different count profiles (e.g., linear, exponential, etc.) may be implemented via modulating the counter frequency used to decrement the offset counter.
Exemplary embodiments
Example 1 includes a power supply to provide an output voltage, the power supply comprising: an error amplifier that controls the power supply based on comparing a reference voltage to a feedback voltage representative of the output voltage, one input of the error amplifier being coupled to the feedback voltage via at least one resistor, wherein the error amplifier receives a representation of the output voltage by the feedback voltage; a droop circuit that generates a droop current to droop a droop voltage across the at least one resistor; a first counter having an output count that changes from a current first digital count corresponding to a current voltage code value to a target first digital count corresponding to a new voltage code value based on a received digital voltage code corresponding to an output voltage value; a second counter having a second output count and preset to an offset count value when a new voltage code value is received, wherein the output count of the first counter is combined with the second output count of the second counter to generate a combined count value; wherein the second counter decrements the second output count from the offset count value to zero when the first counter reaches the target first digital count; and a digital-to-analog converter (DAC) configured to provide a reference voltage based on the combined count value, wherein the DAC offsets the reference voltage based on the offset count value during an output voltage transition corresponding to a transition from the current voltage code value to the new voltage code value.
Example 2 includes the power supply of example 1, wherein the DAC offsets the reference voltage corresponding to the offset count value when the output voltage transitions from a lower voltage value corresponding to the current voltage code value to a higher voltage value corresponding to the new voltage code value.
Example 3 includes the power supply of example 2, wherein the control circuit overcompensates for a droop current change due to the output voltage transition from the lower voltage value to the higher voltage value.
Example 4 includes the power supply of any one of examples 1-3, wherein the second counter counts down linearly from the offset count value to zero.
Example 5 includes the power supply of any one of examples 1-4, wherein the second counter counts down exponentially from the offset count value to zero.
Example 6 includes the power supply of any of examples 1-5, wherein the offset count value is a function of a difference between the new voltage code value and the current voltage code value.
Example 7 includes the power supply of any one of examples 1-6, wherein the offset count value is a function of a predetermined programmed offset value.
Example 8 includes the power supply of any one of examples 1-7, further comprising a modulator coupled to the error amplifier, wherein the modulator modulates the input voltage for powering the output voltage.
Example 9 includes the power supply of any one of examples 8-9, wherein the output voltage provides a supply voltage for the processor, and wherein the digital voltage code is generated by the processor.
Example 10 includes the switching voltage regulator of example 9, wherein the processor is notified when the first counter has reached the target first digital count.
Example 11 includes a method for providing power, the method comprising: receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a current first digital count corresponding to a current voltage code value to a target first digital count corresponding to a new voltage code value; setting a second count to an offset count value on a second counter when a new voltage code value is received; combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.
Example 12 includes the method of example 11, wherein the offset count value is set on the second counter when the current voltage code value corresponds to a lower voltage value and the new voltage code value corresponds to a higher voltage value.
Example 13 includes the method of any one of examples 11-12, further comprising: providing a reference voltage based on the combined count value; comparing, at an error amplifier, a reference voltage to a feedback voltage representative of the output voltage, wherein an input of the error amplifier is coupled to the feedback voltage via at least one resistor, wherein the error amplifier receives the output voltage representative of the output voltage by the feedback voltage; the reduced current is generated by reducing a reduced voltage across at least one resistor.
Example 14 includes the method of any one of examples 11 to 13, wherein decrementing the second count includes at least one of: linearly changing the second count toward zero; and exponentially changing the second count toward zero.
Example 15 includes the method of any one of examples 11 to 14, wherein the offset count value is a function of at least one of: a difference between the new voltage code value and the current voltage code value; and a predetermined programmed offset value.
Example 16 includes a system for providing power to a processor, the system comprising: a processor configured to execute machine-readable instructions, wherein the processor provides a digital voltage code; a first counter having an output count that changes from a current first digital count corresponding to a current voltage code value to a target first digital count corresponding to a new voltage code value based on a digital voltage code; a second counter having a second output count and being preset to an offset count value when the digital voltage code is received, wherein the output count of the first counter is combined with a second count of the second counter to generate a combined count value, wherein the second counter decrements the second count from the offset count value to zero when the first counter reaches the target first digital count; a digital-to-analog converter (DAC) configured to provide a reference voltage based on the combined count value; an error amplifier configured to compare a reference voltage with a feedback voltage representing an output voltage, one input of the error amplifier being coupled to the feedback voltage via at least one resistor; a droop circuit that generates a droop current to droop a droop voltage across the at least one resistor; and a modulator coupled to the error amplifier, wherein the modulator modulates the input voltage for providing power to the processor.
Example 17 includes the system of example 16, wherein the DAC shifts the reference voltage corresponding to the second count when the output voltage transitions from a lower voltage value corresponding to the current voltage code value to a higher voltage value corresponding to the new voltage code value.
Example 18 includes the system of example 17, wherein the control circuit overcompensates for a droop current change due to the output voltage transition from the lower voltage value to the higher voltage value.
Example 19 includes the system of any one of examples 16 to 18, wherein the second counter decrements the second count by at least one of: linearly changing the second count toward zero; and exponentially changing the second count toward zero.
Example 20 includes the system of any one of examples 16 to 19, wherein the offset count value is a function of at least one of: a difference between the new voltage code value and the current voltage code value; and a predetermined programmed offset value.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims (18)
1. A power supply providing an output voltage, the power supply comprising:
an error amplifier that controls the power supply based on comparing a reference voltage with a feedback voltage representing the output voltage; and
a control circuit that receives a requested target for the output voltage, the requested target being higher than a current target, and calculates an offset based on the requested target and the current target, the offset for modifying the reference voltage such that the output voltage reaches the requested target within a specified time.
2. The power supply of claim 1, further comprising:
a digital-to-analog converter (DAC) coupled to the error amplifier, the digital-to-analog converter (DAC) providing the reference voltage to the error amplifier,
wherein the control circuit provides a digital voltage code to the digital-to-analog converter (DAC) that converts the digital voltage code to the reference voltage, wherein in response to the received request target, the control circuit adds the offset to a normal code corresponding to the current target to obtain the digital voltage code provided to the digital-to-analog converter (DAC).
3. The power supply of claim 2, wherein the control circuit comprises a first counter, wherein in response to a received request target, the first counter starts counting from a first count corresponding to the current target to a second count corresponding to the request target.
4. The power supply of claim 3, wherein the control circuit comprises a second counter representing the offset, wherein the second counter is combined with the first counter to obtain the digital voltage code.
5. The power supply of claim 4, wherein the second counter begins to decrement to zero when the first counter reaches the second count.
6. The power supply of claim 5, wherein the second counter is decremented linearly with respect to time.
7. The power supply of claim 5, wherein the second counter is exponentially decremented with respect to time.
8. The power supply of claim 1, wherein the offset is a function of a difference between the requested target and the current target.
9. The power supply of claim 8, wherein the function causes the offset to increase in response to an amount of increase in the difference.
10. A method for providing an output voltage, comprising:
controlling a power supply based on comparing a reference voltage to a feedback voltage representative of the output voltage;
receiving a request target for the output voltage;
calculating an offset based on the request target and a current target, wherein the request target is higher than the current target; and
modifying the reference voltage using the offset such that the output voltage reaches the requested target within a specified time.
11. The method of claim 10, further comprising:
converting a digital voltage code into the reference voltage;
in response to receiving the requested target, adding the offset to a normal code corresponding to the current target to obtain the digital voltage code converted to the reference voltage.
12. The method of claim 11, further comprising:
in response to receiving the request target, a first counter is counted from a first count corresponding to the current target to a second count corresponding to the request target.
13. The method of claim 12, further comprising:
combining a second counter representing the offset with the first counter to obtain the digital voltage code.
14. The method of claim 13, further comprising:
starting to decrement the second counter to zero when the first counter reaches the second count.
15. The method of claim 14, wherein decrementing the second counter is performed linearly with respect to time.
16. The method of claim 14, wherein decrementing is performed exponentially with respect to time.
17. The method of claim 10, wherein the offset is a function of a difference between the requested target and the current target.
18. The method of claim 17, wherein the function causes the offset to increase in response to the increased amount of the difference.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361792745P | 2013-03-15 | 2013-03-15 | |
| US61/792,745 | 2013-03-15 | ||
| US13/851,651 US9118245B2 (en) | 2013-03-15 | 2013-03-27 | Digital voltage compensation for power supply integrated circuits |
| US13/851,651 | 2013-03-27 | ||
| CN201310464431.9A CN104052262B (en) | 2013-03-15 | 2013-10-08 | Digital voltage for power IC compensates |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310464431.9A Division CN104052262B (en) | 2013-03-15 | 2013-10-08 | Digital voltage for power IC compensates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108199581A CN108199581A (en) | 2018-06-22 |
| CN108199581B true CN108199581B (en) | 2021-01-08 |
Family
ID=51504752
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310464431.9A Active CN104052262B (en) | 2013-03-15 | 2013-10-08 | Digital voltage for power IC compensates |
| CN201810150409.XA Active CN108199581B (en) | 2013-03-15 | 2013-10-08 | Power supply and method for providing an output voltage |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310464431.9A Active CN104052262B (en) | 2013-03-15 | 2013-10-08 | Digital voltage for power IC compensates |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN104052262B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9645626B2 (en) * | 2014-11-12 | 2017-05-09 | Qualcomm Incorporated | Circuits and methods providing supply voltage control based on transient load prediction |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1448819A (en) * | 2002-03-18 | 2003-10-15 | 英特塞尔美国公司 | DC-to-DC converter with fast override feedback control and associated methods |
| CN1543046A (en) * | 2003-04-16 | 2004-11-03 | 罗姆股份有限公司 | Power supply apparatus |
| CN1829055A (en) * | 2005-03-02 | 2006-09-06 | 富士通株式会社 | DC-DC converter, control device and method, power supply device and electronic equipment |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382916A (en) * | 1991-10-30 | 1995-01-17 | Harris Corporation | Differential voltage follower |
| US5594631A (en) * | 1994-04-20 | 1997-01-14 | The Boeing Company | Digital pulse width modulator for power supply control |
| US6472856B2 (en) * | 2001-03-09 | 2002-10-29 | Semtech Corporation | Bounded power supply voltage positioning |
| US7570036B2 (en) * | 2004-09-10 | 2009-08-04 | Primarion Corporation | Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators |
| TWI375806B (en) * | 2007-08-07 | 2012-11-01 | Himax Tech Ltd | Apparatus for testing driving circuit in display |
| US7928704B2 (en) * | 2007-08-24 | 2011-04-19 | Upi Semiconductor Corporation | Droop circuits and multi-phase DC-DC converters |
| US7908496B2 (en) * | 2007-09-29 | 2011-03-15 | Intel Corporation | Systems and methods for communicating voltage regulation information between a voltage regulator and an integrated circuit |
| US7821246B2 (en) * | 2007-12-28 | 2010-10-26 | Intel Corporation | Voltage regulator and method of calibrating the same |
| US8316256B2 (en) * | 2009-12-10 | 2012-11-20 | Nvidia Corporation | Method and system for supplying output voltage to graphics processing unit |
| TWI456882B (en) * | 2010-06-25 | 2014-10-11 | Richtek Technology Corp | Voltage regulator and control circuit and method therefor |
| US8791676B2 (en) * | 2011-09-30 | 2014-07-29 | Monolithic Power Systems, Inc. | Reference adjusting power supply for processor and control method thereof |
| CN102684495B (en) * | 2012-05-16 | 2015-02-18 | 杭州乐图光电科技有限公司 | Digital power supply control circuit, control method and digital power supply using circuit and method |
-
2013
- 2013-10-08 CN CN201310464431.9A patent/CN104052262B/en active Active
- 2013-10-08 CN CN201810150409.XA patent/CN108199581B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1448819A (en) * | 2002-03-18 | 2003-10-15 | 英特塞尔美国公司 | DC-to-DC converter with fast override feedback control and associated methods |
| CN1543046A (en) * | 2003-04-16 | 2004-11-03 | 罗姆股份有限公司 | Power supply apparatus |
| CN1829055A (en) * | 2005-03-02 | 2006-09-06 | 富士通株式会社 | DC-DC converter, control device and method, power supply device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104052262A (en) | 2014-09-17 |
| CN108199581A (en) | 2018-06-22 |
| CN104052262B (en) | 2018-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10250138B2 (en) | Digital voltage compensation for power supply integrated circuits | |
| CN105450024B (en) | Multi-stage amplifier | |
| US10498234B2 (en) | Voltage regulator with nonlinear adaptive voltage position and control method thereof | |
| US6208127B1 (en) | Methods and apparatus to predictably change the output voltage of regulators | |
| EP2887174B1 (en) | CC-CV method to control the startup current for LDO | |
| US7719243B1 (en) | Soft-start system and method for power converter | |
| US10756621B2 (en) | Voltage regulators with controlled output voltage and the method thereof | |
| US10261534B2 (en) | Method and system for an adaptive low-dropout regulator | |
| CN108352828B (en) | Digital pre-compensation for voltage slewing in a power converter | |
| US20120194157A1 (en) | Switching regulator performing output voltage changing function | |
| EP2449663B1 (en) | Power supply with dynamic input current suppression | |
| US8316256B2 (en) | Method and system for supplying output voltage to graphics processing unit | |
| CN108199581B (en) | Power supply and method for providing an output voltage | |
| US11018576B2 (en) | Method and device for decreasing the power supply voltage of a c-type USB receiver device supporting a USB power delivery mode | |
| CN210201551U (en) | Controller and USB source equipment | |
| CN112363558A (en) | Voltage regulating circuit | |
| EP3740834B1 (en) | Apparatus and method for minimizing voltage drop due to current surge at input to a voltage regulator upon turn-on of the voltage regulator | |
| US11409312B1 (en) | Non-linear load line for a multiphase voltage regulator | |
| CN112748757B (en) | DAC control logic for controlling the DAC | |
| CN111200430B (en) | Driver circuit system and related method thereof | |
| US9024595B1 (en) | Asymmetric transient response control | |
| US20220060111A1 (en) | Power supply circuit, load circuit, electronic circuit, method for supplying power and method for operating an electronic circuit | |
| CN112650339A (en) | DLDO control circuit | |
| CN114860014A (en) | Voltage regulating circuit | |
| JP2025052800A (en) | Switching Regulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |