CN108183729A - The channel interleaving method and system of power line carrier communication based on FPGA - Google Patents

Abstract

The invention belongs to the field of power line carrier communication, and discloses a channel interleaving method of power line carrier communication based on FPGA. The channel interleaving method of power line carrier communication based on FPGA performs interleaving of inspection codes, interleaving of information codes, and verification of information codes. Mixed interleaving and cyclic shifting of codes; after interleaving, the adjacent bits are allocated to different subcarriers for transmission, and the adjacent bits are mapped to relatively important and less important positions in the constellation diagram; at the same time, in the time domain Dimensionally discretize the information, transform the memory channel into a memoryless channel, and then cooperate with the error correction code to reduce the bit error rate. The present invention discretizes information in the time-domain dimension through multi-level interleaving processing, and can approximately convert a memory channel into a memoryless channel, and then cooperate with an error correction code to reduce the system bit error rate and improve system reliability.

Description

Channel interleaving method and system of FPGA-based power line carrier communication

technical field

The invention belongs to the field of power line carrier communication, in particular to an FPGA-based channel interleaving method and system for power line carrier communication.

Background technique

At present, the existing technologies commonly used in the industry are as follows:

In the past 20 years, low-voltage power line carrier communication has been widely used in power system monitoring, remote meter reading, home automation and other fields. At present, with the development of concepts such as smart grid, energy Internet, and "four networks in one", low-speed power line communication can no longer meet social needs.

Broadband power line carrier communication refers to a system with a bandwidth of 2 to 30 MHz and a transmission rate of more than 1 Mbps. The core of the physical layer of broadband power line carrier communication system is OFDM. The original intention of the power line design is only for power transmission, and does not consider the use of power lines for data transmission, not a dedicated communication channel. The low-voltage power line is connected with complicated electrical equipment, the network topology is complex, the equipment is randomly connected and switched out, and its channel characteristics are bad. The noise on the power line on the power line channel can be divided into colored background noise, burst noise, random pulse noise and periodic pulse noise, etc. Among them, the pulse noise has the greatest impact on the communication quality of the power line, which is considered to be the sudden change in the data transmission of the power line medium. The main reason for sending errors. The frequency selective fading and impulse noise of the power line channel will cause a series of bit errors, and the purpose of channel interleaving is to distribute the transmitted information bits, change the information structure to the greatest extent, and make the burst errors of the channel diffuse in time. Error-correcting codes can reduce burst errors, so it is of great significance to design a suitable channel interleaving method.

At present, the commonly used interleaving method is group interleaving. Group interleaving is to divide the output signal of the error correction code into m code groups evenly. Read from left to right. Nowadays, for the broadband power line carrier communication system, more and more applications are required to be provided. Therefore, it is required to increase the transmission rate of the power line carrier. In view of this, Turbo codes are also applied in the power line carrier communication system, and a channel interleaving method that is more adaptable to the system and has higher reliability is also required to meet the needs of the system.

In summary, the problems in the prior art are:

(1) At present, the channel characteristics of power lines are poor, prone to burst errors, and the system bit error rate is high.

(2) At present, the commonly used channel interleaving method is group interleaving, which can change the structure of information, but it only interleaves in one dimension in the time domain or frequency. For an m×n group interleaver, the period is m-bit interference If the transmission process is interrupted, the erroneous m bits will become continuous bits and enter the error correction code decoding after deinterleaving, which will inevitably lead to decoding failure, resulting in a higher bit error rate.

(3) In broadband power line communication, the bandwidth is large, the rate is high, and the number of available subcarriers is large. Packet interleaving cannot change the original structure of the information to the greatest extent. Adjacent data may still be in the same subcarrier due to insufficient interleaving. Channels or adjacent sub-channels, continuous errors will still occur. After continuous errors are caused, the error correction code cannot correct the error correctly, and the bit error rate of the system is high, which cannot meet the needs of broadband power line communication.

The difficulty and significance of solving the above technical problems:

Nowadays, with the development of concepts such as smart grid, energy Internet, and "four networks in one", broadband power line carrier communication systems are required to provide more and more applications. A high-speed broadband power line communication system has large bandwidth, high speed, and a large number of available subcarriers. Poor power line channel characteristics, high-speed requirements, and system complexity impose requirements on system performance. However, channel interleaving will inevitably bring system delay. To sum up the above factors, how to find a balance between delay and performance and improve system reliability is the difficulty in the design of channel interleaving methods. The existing packet interleaving method cannot fully disrupt the original information structure, and can still generate a series of bit errors, which is not suitable for the broadband power line channel environment.

The channel interleaving method proposed by the present invention has four levels of interleaving. Under the premise of introducing a small delay as much as possible, the original structure of the information is changed to the greatest extent, so that adjacent bits fall on different available subcarriers as much as possible and effectively separate the corresponding subcarriers. Adjacent bits are mapped to relatively important and less important positions in the constellation diagram, and after multi-level interleaving processing, the information is discretized in the time domain dimension, which can approximately convert the memory channel into a memoryless channel, which can effectively reduce the continuous The occurrence of errors can meet the needs of high-speed power line communication and realize high-speed transmission.

Contents of the invention

Aiming at the problems existing in the prior art, the present invention provides a channel interleaving method and system flow chart of FPGA-based power line carrier communication.

The present invention is achieved in this way, a channel interleaving method based on FPGA-based power line carrier communication, which performs interleaving of inspection codes, interleaving of information codes, mixed interleaving of information codes and inspection codes, and cyclic shifting; after the interleaving process, the phase The adjacent bits are allocated to different subcarriers for transmission, and the adjacent bits are mapped to relatively important and less important positions in the constellation diagram; at the same time, the information is discretized in the time domain dimension, and the channel with memory is transformed into memoryless channel, and then cooperate with the error correction code to reduce the bit error rate.

Further, the channel interleaving method of the FPGA-based power line carrier communication specifically includes:

Step 1, performing interleaving processing on the check code;

Step 2, interleaving the information code;

Step 3, performing mixed interleaving between the information code and the check code;

Step 4, perform cyclic shift processing.

Further, said step one specifically includes:

Output the first block (n-k)/4 bits of the check code to block 1, the second block (n-k)/4 bits to block 2, and the third block (n-k)/4 bits to block 3 , the fourth block (n-k)/4 bits is output to block 4; it is equivalent to storing the check code in a matrix of (n-k)/4 columns and 4 rows, where the first row represents block 1, and the first row The second line represents block 2, the third block represents block 3, and the fourth line represents block 4; when writing data, write data in row order;

When reading data, read the data of four rows at the same time by column, first read from column 0, add a read step S to the first address, and the order of the columns read in the first round is (0 ,2*S,3*S,...), the first round reads a total of ((n-k)/4)/S columns;

Then, carry out the second round, read the first address plus 1, start reading from the first column, add a read step S to the first address, and the order of the columns read in the second round is (1,2* S+1, 3*S+1, ...), the second round reads ((n-k)/4)/S columns in total, and so on, through S rounds of reading, all check codes are read out.

Further, said step two specifically includes:

Output the first block k/4 bits of the information code to block 1, the second block k/4 bits to block 2, the third block k/4 bits to block 3, and the fourth block k /4 bits are output to block 4; it is equivalent to storing the information code in a matrix of k/4 columns and 4 rows, where the first row represents block 1, the second row represents block 2, and the third block Represents block 3, and the fourth row represents block 4; when writing data, write data in row order;

When reading data, read the data of four rows simultaneously by column; wherein, T=k/4, for the interleaving of information code, start reading from an offset value offset column, first start reading from the offset column, Then add a reading step S to the first address, the order of the columns read in the first round is (offset, (offset+S) mod T, (offset+2*S) mod T, ...), the first A total of (k/4)/S columns are read in rounds;

Then, carry out the second round, read the first address plus 1, start reading from the first column, and then add a read step S to the first address, the order of the columns read in the second round is (offset+1 ,(offset+S+1)mod T,(offset+2*S+1)modT,...), the second round reads a total of (k/4)/S columns, and so on, through S rounds of reading Take, read all information codes.

Further, said step three specifically includes:

After the check code is interleaved, the output is (n-k)/4 bits, after the information code is interleaved, the output is k/4 bits, (n-k)/4 bits and k/4 bits are mixed and interleaved; the output result is the first 4 bits are the information code , followed by a 4-bit check code, and so on, to complete the interleaving process between the check code and the information code;

The serial-to-parallel conversion includes: converting the k-bit information code into k/4 data with a bit width of 4 bits after serial-to-parallel conversion, and converting the (n-k) bit check code into (n-k)/ 4 pieces of data with a bit width of 4 bits; output the n/4 pieces of data alternately, with the information code first, followed by the check code, and so on;

The fourth step specifically includes:

The processed data in the third step is numbered according to the cycle from 0 to 7, and the sequence is adjusted every two nibbles. For labels 0 and 1, they are not processed and directly output. For labels 2 and 3, they are cyclically shifted to the right by 1 bit. For labels 4 and 5, rotate right by 2 bits, and for labels 6 and 7, rotate right by 3 bits; then perform parallel-to-serial conversion and output.

Another object of the present invention is to provide a computer program for realizing the channel interleaving method of the FPGA-based power line carrier communication.

Another object of the present invention is to provide an information and data processing terminal for realizing the channel interleaving method of the FPGA-based power line carrier communication.

Another object of the present invention is to provide a computer-readable storage medium, including instructions, which, when run on a computer, cause the computer to execute the FPGA-based power line carrier communication channel interleaving method.

Another object of the present invention is to provide a channel interleaving system based on FPGA-based power line carrier communication including:

The check code interleaving unit uses the RAM and the ping-pong structure to interleave the check code;

The information code interleaving unit uses the RAM and the ping-pong structure to interleave the information code;

The hybrid interleaving unit is used for serial-to-parallel conversion, and performs hybrid interleaving between the information code and the check code;

The cyclic shift operation unit is used for performing a cyclic shift operation followed by a parallel-to-serial conversion.

Another object of the present invention is to provide an information data processing terminal equipped with the FPGA-based power line carrier communication channel interleaving system.

In summary, the advantages and positive effects of the present invention are:

The invention performs interleaving of inspection codes, interleaving of information codes, mixed interleaving of information codes and inspection codes, and cyclic shifting. After interleaving, adjacent bits are effectively allocated to different subcarriers for transmission, and adjacent bits are effectively mapped to relatively important and less important positions in the constellation diagram, which can effectively reduce the impact of frequency fading on the system. The present invention discretizes information in the time-domain dimension through multi-level interleaving processing, and can approximately convert a memory channel into a memoryless channel, and then cooperate with an error correction code to reduce the system bit error rate and improve system reliability.

For an m×n packet interleaver, if the period is m-bit interference affects the transmission process, the wrong m-bits will become continuous bits after de-interleaving and enter the error-correcting code decoding, which will inevitably lead to decoding failure. Compared with the m×n packet interleaver, the present invention has more advantages, and the technical comparison between packet interleaving and the present invention is shown in Table 1:

Table 1

Currently, an effective method is to use an Orthogonal Frequency Division Multiplexing (OFDM) system to transmit data using multiple carriers. The power line channel has frequency selectivity. When a certain frequency band has strong interference, data errors will occur on the subcarriers of this frequency band, and frequency selective fading will occur, resulting in errors in a series of bits. The FPGA-based channel interleaving method of the present invention can ensure that adjacent bits will fall on non-adjacent sub-carriers after OFDM modulation, and at the same time, adjacent bits can be mapped to relatively important and less important constellation diagrams superior. After interleaving, the original continuous bits are maximized. After de-interleaving, the error dispersion is still within the error correction range of the error correction code, thereby reducing the impact of fading channels on system performance.

Aiming at the poor transmission characteristics of the power line carrier communication channel, the present invention uses FPGA resources to propose a channel interleaving method, which can discrete channel burst errors in the time domain dimension, and approximately convert memory channels into memoryless channels, so that random errors can be corrected The error correction code can be used in the power line carrier communication system. Through the processing of channel interleaving, combined with the corresponding error correction code, the disadvantage of poor communication channel characteristics of power line carrier can be overcome, and the spectrum utilization rate can be greatly improved, so that the power line can be used for effective communication transmission.

The simulation experiment of the present invention shows that the input information code and the check code adopt special bits, the information code is 128 bits alternated with 0 and 1, and the check code is also 128 bits alternated with 0 and 1, parity_out is the interleaving result of the check code, and data_out is the information code The interleaving result, da_pa_out is the mixed interleaving result of the information code and the check code, and DP_ND is the final output result of the interleaving. The output clock CLK3 is twice that of the input clock CLK1. It can be seen that the interleaving result is first 64-bit 0, then 64-bit 1, then 64-bit 0, and then 64-bit 1. The result is consistent with the Matlab result. correct.

Description of drawings

FIG. 1 is a flowchart of a channel interleaving method for FPGA-based power line carrier communication provided by an embodiment of the present invention.

Fig. 2 is a schematic diagram of a channel interleaving system for FPGA-based power line carrier communication provided by an embodiment of the present invention.

Fig. 3 is a hardware implementation block diagram of a verification code interleaver provided by an embodiment of the present invention.

Fig. 4 is a hardware implementation block diagram of an information code interleaver provided by an embodiment of the present invention.

Fig. 5 is a hardware implementation block diagram of the information code and check code hybrid interleaver provided by the embodiment of the present invention.

FIG. 6 is a block diagram of cyclic shift hardware implementation provided by an embodiment of the present invention.

FIG. 7 is a diagram of an overall simulation result provided by an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In the prior art, the channel characteristics of the power line are poor, and burst errors are prone to occur; the bit error rate of the system is high.

The present invention will be further described below in conjunction with specific analysis.

As shown in Figure 1, the channel interleaving method based on the FPGA-based power line carrier communication provided by the embodiment of the present invention utilizes the Verilog program to realize channel interleaving, and the realization of the channel interleaving method mainly includes the following steps:

The first step is to interleave the check code.

In the second step, the information code is interleaved.

In the third step, mixed interleaving is performed on the information code and the check code.

The fourth step is to perform cyclic shift processing.

The FPGA implementation of the channel interleaving method of the power line carrier communication comprises the following steps:

Step 1, using RAM and ping-pong structure to interleave the check code.

Step 2, using RAM and ping-pong structure to interleave the information code.

Step 3, serial-to-parallel conversion, performing hybrid interleaving between the information code and the check code.

Step 4, perform a circular shift operation, and then perform a parallel-to-serial conversion.

Described step one specifically includes:

Assume that after channel coding, the information code and the check code are transmitted separately, the length of the information code is k bits, and the length of the check code is (n-k) bits. This design is mainly aimed at code rate 1/2. In this step, the interleaving process is performed on the (n-k) bit check code.

Output the first block ((n-k)/4 bits) of the verification code to block 1, the second block ((n-k)/4 bits) to block 2, and the third block ((n-k)/4 bits ) into block 3 and the fourth block ((n-k)/4 bits) into block 4. It is equivalent to storing the verification code in a matrix of (n-k)/4 columns and 4 rows, where the first row represents block 1, the second row represents block 2, the third block represents block 3, and the fourth row Represents block 4. When writing data, write data in row order. When reading data, read the data of four rows at the same time by column, first read from the 0th column, and then add a read step S to the first address, so that the order of the columns read in the first round is (0,2*S,3*S,...), the first round reads ((n-k)/4)/S columns in total; then, the second round is performed, and the first address is read plus 1, that is, from the first The column starts to be read, and then a read step S is added to the first address. The order of the columns read in the second round is (1,2*S+1,3*S+1,...), the second A total of ((n-k)/4)/S columns are read in rounds, and so on. After reading in S rounds, all check codes can be read out. Among them, the relevant parameters are shown in Table 1.

Step two specifically includes:

In this step, the interleaving process is performed on the k-bit check code. Output the first block (k/4 bits) of the information code to block 1, the second block (k/4 bits) to block 2, and the third block (k/4 bits) to block 3 , the fourth block (k/4 bits) is output into block 4. It is equivalent to storing the information code in a matrix of k/4 columns and 4 rows, where the first row represents block 1, the second row represents block 2, the third block represents block 3, and the fourth row represents the block Block 4. When writing data, write data in row order. When reading out the data, the data of the four rows are read out at the same time by column. For convenience of description, define T=k/4. For the interleaving of the information code, it is not to start reading from the 0th column, but to start reading from an offset value offset column, first start reading from the offset column, and then add a read step to the first address S, so the order of the columns read in the first round is (offset, (offset+S) mod T, (offset+2*S) mod T, ...), and the first round reads a total of (k/4)/S Then, carry out the second round, read the first address plus 1, that is, start reading from the first column, and then add a read step S to the first address, and the order of the columns read in the second round is ( offset+1, (offset+S+1)mod T, (offset+2*S+1)modT,...), the second round reads (k/4)/S columns in total, and so on, through S rounds Read, you can read all the information code. Among them, the relevant parameters are shown in Table 2.

Table 2

Information code (number of bits) offset value step size 128 16 4 576 72 16

Step three specifically includes:

After the check code is interleaved, the output is (n-k)/4 bits, after the information code is interleaved, the output is k/4 bits, and the two are mixed and interleaved. The output result should be that the first 4 bits are the information code, followed by the 4-bit check code, and so on to complete the interleaving process between the check code and the information code.

Using serial-to-parallel conversion, the k-bit information code is converted into k/4 data with a bit width of 4 bits after serial-to-parallel conversion, and the (n-k) bit inspection code is converted into (n-k)/4 bits after serial-to-parallel conversion Data with a width of 4 bits. The current processing is to output the n/4 data alternately, with the information code first, followed by the check code, and so on.

Using a simple dual-port distributed RAM (DRAM) with a bit width of 4 and a depth of n/2, write n/2 data regularly, and then read them sequentially. Specifically, the write address is generated sequentially, using a modulo n/2 counter, but the write content dina changes alternately, dina is the information code first, then the check code, and so on.

Step four specifically includes:

The processed data in the third step is numbered according to the cycle from 0 to 7, and the sequence is adjusted every two nibbles. For labels 0 and 1, they are not processed and directly output. For labels 2 and 3, they are cyclically shifted to the right by 1 bit. For labels 4 and 5, rotate right by 2 bits, and for labels 6 and 7, rotate right by 3 bits. Subsequent data are processed sequentially according to this rule. Then perform parallel-serial conversion output. The specific rules are shown in Table 3.

table 3

output nibble number shift mode 0 or 1 b0b1b2b3 2 or 3 b3b0b1b2 4 or 5 b2b3b0b1 6 or 7 b1b2b3b0

In the power line carrier communication, the current effective method is to use the Orthogonal Frequency Division Multiplexing (OFDM) system to transmit data by using multiple carriers. The FPGA-based channel interleaving method of the present invention can ensure that adjacent bits will fall on non-adjacent sub-carriers after OFDM modulation, and at the same time, adjacent bits can be mapped to relatively important and less important constellation diagrams , so as to alleviate the impact of fading channels on system performance.

As shown in Figure 2, an embodiment of the present invention provides an FPGA-based channel interleaving system for power line carrier communication including:

The check code interleaving unit uses the RAM and the ping-pong structure to interleave the check code;

The information code interleaving unit uses the RAM and the ping-pong structure to interleave the information code;

The hybrid interleaving unit is used for serial-to-parallel conversion, and performs hybrid interleaving between the information code and the check code;

The cyclic shift operation unit is used for performing a cyclic shift operation followed by a parallel-to-serial conversion.

The present invention will be further described below in conjunction with specific embodiments.

Assuming that the channel coding adopts a coding method with a length of 128 bits and a code rate of 1/2, in the output result, the information code and the check code are output in parallel.

As shown in Figure 1, the realization of the present invention needs to go through the following steps:

Step 1: Interleave the 128-bit check code.

Specifically, the implementation of common packet interleaving generally uses the read and write of RAM to adjust the order to realize the interleaving function, and adopts the method of "writing out of order, reading out in order" or "writing in order, reading out in order".

In the present invention, it is more convenient to adopt the method of "sequential writing, random reading". Using CLK1 as the clock, using a RAM with a bit width of 1 and a depth of 128, the input check code is stored in the RAM in sequence, that is, stored in the address 0 to address 127 of the RAM in sequence, and written into the address generating unit wadd Generator Can be generated by a modulo 128 counter. The read address adopts the method of "out-of-order read". When the read address enable is pulled high, the calculation of the read address is performed. Based on the above analysis, the hardware implementation block diagram of the check code interleaver design is shown in Figure 3.

The generation of RAM read address is the key and difficult point of the whole design. According to the idea of check code interleaving and the search of rules, the read address generating unit radd Generator can be designed. The core design is as follows:

wadd=cnt1+4cnt2+32cnt3\*MERGEFORMAT(1)

Among them, the bit width of cnt1 is 2, the bit width of cnt2 is 3, and the bit width of cnt3 is 2. The initial values of cnt1, cnt2 and cnt3 are all 0. The change of cnt3 is 0, 1, 2, 3, and then continue to cycle according to this rule. When cnt3 is 3, add 1 to cnt2, and the change of cnt2 is 0, 1, 2, 3, 4, 5, 6, 7, and then cnt2 continues to cycle according to this rule. When cnt2 is 7, cnt1 is increased by 1, and the change of cnt1 is 0, 1, 2, 3. At this time, the calculation of 128 read addresses is realized. At this time, the read address can be calculated according to the formula, and the key Verilog code is as follows:

When the read address calculation enable is pulled high, the calculation of the read address wadd starts. Through this code design, it can be calculated that the read address is 0, 32, 64, 96, 4, 36, 68, 100... 31, 63, 95, 127, which is consistent with the design idea.

Due to the design of "write out of order and read out sequentially", when a frame of data is not completely written, new data cannot be written, otherwise the read data may be affected by the newly written data. Influenced by the error, it will cause the problem of not being able to handle continuous data. Considering this problem, the solution is to use the pipeline structure, use the "ping-pong structure", use two simple dual-port RAMs with a bit width of 1 and a depth of 128, named RAM0 and RAM1, and write enable to RAM0 and RAM1 And read enable control, realize the following process: when writing data to RAM0, read RAM1 at the same time, when reading RAM0, write data to RAM1 at the same time, so that the continuous processing of data can be guaranteed. and no error is generated.

Step 2: Interleave the 128-bit information code.

The information code interleaving is very similar to the check code interleaving. The hardware implementation block diagram of the information code interleaver design is shown in Figure 4. The main difference is that the calculation of the RAM read address is slightly different. The core formula for calculating the read address of information code interleaving is still:

wadd=cnt1+4cnt2+32cnt3\*MERGEFORMAT(2)

However, due to the existence of an interleaving offset value of 16 in the information code interleaving, according to the design idea, its implementation is somewhat different from that of the check code interleaving. The bit width of cnt1 is 2, the bit width of cnt2 is 3, and the bit width of cnt3 is 2. The initial values of cnt1 and cnt3 are both 0, while the initial value of cnt2 is 4. The change of cnt3 is 0, 1, 2, 3, and then continue to cycle according to this rule. When cnt3 is 3, add 1 to cnt2, and the change of cnt2 is 4, 5, 6, 7, 0, 1, 2, 3, and then cnt2 continues to cycle according to this rule. When cnt2 is 3, cnt1 is added by 1, and the change of cnt1 is 0, 1, 2, 3. At this time, the calculation of 128 read addresses is realized.

Except that the initial value of cnt2 is different, other calculation read address codes are the same as check codes. Therefore, when the read address calculation enable is pulled high, the calculation of the read address wadd starts. Through this code design, it can be calculated that the read address is 16, 48, 80, 112...15, 47, 79, 111, which is consistent with the design idea. In order to deal with continuous data, the same "ping-pong structure" is used for processing.

Step 3: The information code and the check code are mixed and interleaved.

(3a) When the input clock is CLK1, use serial-to-parallel conversion to convert the 128-bit information code into 32 data with a bit width of 4 bits after serial-to-parallel conversion, and convert the 128-bit inspection code to 32 after serial-to-parallel conversion Data with a unit bit width of 4 bits. The current processing is to output these 64 data alternately, with the information code first, followed by the check code, and so on.

(3b) Using a simple dual-port distributed RAM (DRAM) with a bit width of 4 and a depth of 64, write 64 data regularly, and then read them sequentially. Specifically, the write address is generated sequentially, using a modulo 64 counter, but the write content dina changes alternately, dina is the information code first, then the check code, and so on. The processed data is 64 nibbles, which is convenient for the next stage of cyclic shift processing. The clock for writing DRAM and reading DRAM is CLK2, which is divided by two of CLK1.

Through the above analysis, the design of the information code and check code interleaver is shown in Figure 5.

Step 4: cyclic shift processing.

(4a) The input clock is CLK2, and the nibble shift processing is performed. For labels 0 and 1, the direct output is not processed, for labels 2 and 3, rotate right by 1 bit, for labels 4 and 5, rotate right by 2 bits, and for labels 6 and 7, rotate right by 3 bits. Subsequent data are processed sequentially according to this rule.

(4b) Parallel to serial conversion. Since the data output by channel interleaving is further used by the modulation module, and the modulation method is not fixed, it may be QPSK, 16QAM, etc. Therefore, the data output by information interleaving should be a serial bit stream. After the shifted data is converted to parallel and serial, a serial bit stream is output. The clock at the output is CLK3, whose frequency is four times that of CLK2 and twice that of CLK1.

According to the above analysis, the hardware implementation block diagram of cyclic shift is shown in Figure 6.

After the above four steps, the entire system of channel interleaving can be realized by using the writing and reading of the RAM in the FPGA, and using operations such as serial-to-parallel conversion, shift, and parallel-to-serial conversion. Utilizing these has the advantages of simple logic and small time delay.

The present invention will be further described below in combination with simulation experiments.

As shown in Figure 7, a Verilog simulation diagram is given. The figure is an intercepted simulated waveform. In order to verify whether it is correct or not, the input information code and the check code use special bits. The information code is 128 bits alternating with 0 and 1, and the check code is also 128 bits alternated with 0 and 1. parity_out is the check Code interleaving result, data_out is the result of information code interleaving, da_pa_out is the result of mixed interleaving of information code and check code, DP_ND is the final output result of interleaving. The output clock CLK3 is twice that of the input clock CLK1. It can be seen that the interleaving result is first 64-bit 0, then 64-bit 1, then 64-bit 0, and then 64-bit 1. The result is consistent with the Matlab result. correct.

The above is only a special case of the present invention, that is, the information code is 128 bits, the code rate is 1/2, and the check code is 128 bits. The realization of other cases is similar, and only some parameters need to be modified.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented wholly or partly in the form of a computer program product, said computer program product comprises one or more computer instructions. When the computer program instructions are loaded or executed on the computer, the processes or functions according to the embodiments of the present invention will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (eg coaxial cable, fiber optic, digital subscriber line (DSL) or wireless (eg infrared, wireless, microwave, etc.)). The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, a Solid State Disk (SSD)).

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (10)

1. A kind of 1. channel interleaving method of the power line carrier communication based on FPGA, which is characterized in that the electricity based on FPGA The channel interleaving method of powerline carrier communication is tested the mixing of the intertexture of code, the intertexture of information code, information code and check code Intertexture and cyclic shift；After interleaving treatment, adjacent bit is assigned in different sub-carrier and is transmitted, adjacent bit is reflected It is mapped in planisphere on relatively important and inferior important position；Meanwhile there will be memory to information discretization on time-domain dimension Channel is converted into memoryless channel, then coordinates the reduction bit error rate with error correcting code.
2. 2. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described The channel interleaving method of power line carrier communication based on FPGA specifically includes：

   Step 1 is interleaved check code processing；

   Step 2 is interleaved information code processing；

   Step 3 carries out mixing intertexture between information code and check code；

   Step 4 carries out cyclic shift processing.
3. 3. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 1 specifically includes：

   First piece of bit of (n-k)/4 of check code is output in block 1, second piece of bit of (n-k)/4 is output in block 2, Third block (n-k)/4 bit is output in block 3, and the 4th piece of bit of (n-k)/4 is output in block 4；It is equivalent to check code The matrix of 4 row of the row of (n-k)/4 is deposited into, wherein, the first row represents block 1, and the second row represents block 2, and third block represents Block 3, fourth line represent block 4；When data are written, data are sequentially written in by row；

   When reading data, the data of four rows are read simultaneously by row, is read since arranging the 0th first, one is added on first address A reading step-length S, the sequence for the row that the first round reads is (0,2*S, 3*S ... ...), and the first round reads altogether ((n-k)/4)/S Row；

   Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, plus a reading step-length on first address S, the sequence of row that the second wheel is read are (1,2*S+1,3*S+1 ... ...), and the second wheel reads altogether ((n-k)/4)/S row, with this Analogize, the reading taken turns by S reads one-hundred-percent inspection code.
4. 4. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 2 specifically includes：

   First piece of k/4 bit of information code is output in block 1, second piece of k/4 bit is output in block 2, third block k/4 Bit is output in block 3, and the 4th piece of k/4 bit is output in block 4；It is equivalent to information code being deposited into 4 row of k/4 row Matrix, wherein, the first row represents block 1, and the second row represents block 2, and third block represents block 3, and fourth line represents block 4； When data are written, data are sequentially written in by row；

   When reading data, the data of four rows are read simultaneously by row；Wherein, T=k/4, it is inclined from one for the intertexture of information code Shifting value offset row start to read, and are read since being arranged offset first, later plus a reading step-length on first address S, the sequence for the row that the first round reads is (offset, (offset+S) mod T, (offset+2*S) mod T ... ...), and first Wheel reads (k/4)/S row altogether；

   Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, later plus a reading on first address Step-length S, the sequence of row that the second wheel is read are (offset+1, (offset+S+1) mod T, (offset+2*S+1) mod T ... ...), the second wheel reads altogether (k/4)/S row, and so on, the reading taken turns by S reads all information code.
5. 5. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 3 specifically includes：

   It after check code interweaves, exports as the bit of (n-k)/4, after information code interweaves, exports as k/4 bits, the bit of (n-k)/4 and k/ 4 bits carry out mixing intertexture；It is information code that output result, which is preceding 4 bit, then 4 bit trial code, and so on, it completes to examine Interleaving process between code and information code；

   The serioparallel exchange, including：K bit information codes are become into the data that k/4 bit wide is 4 bits after serioparallel exchange, (n-k) bit trial code is become into the data that (n-k)/4 bit wide is 4 bits after serioparallel exchange；This n/4 data is handed over For output, information code then verifies that code preceding, and so on.
6. 6. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 4 specifically includes：

   By step 3 treated data, according to 0 to 7 numbering cycles, each two nibble adjustment sequence successively, for label For 0 and 1, direct output is not handled, for label 2 and 3, ring shift right 1, for label 4 and 5, ring shift right 2, for Label 6 and 7, ring shift right 3；And so on, carry out parallel-serial conversion output again later.
7. 7. a kind of channel interleaving method for realizing the power line carrier communication based on FPGA described in claim 1~6 any one Computer program.
8. 8. a kind of channel interleaving method for realizing the power line carrier communication based on FPGA described in claim 1~6 any one Information data processing terminal.
9. 9. a kind of computer readable storage medium, including instructing, when run on a computer so that computer is performed as weighed Profit requires the channel interleaving method of the power line carrier communication based on FPGA described in 1~6 any one.
10. 10. a kind of channel interleaving method of the power line carrier communication based on FPGA as described in claim 1 based on FPGA Power line carrier communication channel interleaving system, which is characterized in that the channel of the power line carrier communication based on FPGA Interlacing system includes：

    Check code interleave unit interweaves to check code using RAM and ping-pong structure；

    Information code interleave unit interweaves to information code using RAM and ping-pong structure；

    Interleave unit is mixed, for serioparallel exchange, mixing intertexture is carried out between information code and check code；

    Circulative shift operation unit, for carrying out circulative shift operation, parallel serial conversion later.