CN108173624A - A Partially Decoded Polar Code Serial Cancellation Decoding Circuit and Its Method - Google Patents

Abstract

The invention discloses a kind of polarization codes of Partial Decode serially to offset decoding circuit and its method, it is characterized in that including：Binary phase shift keying modulation module, likelihood ratio computing module, bit hard decision module；The binary phase shift keying modulation module generates initial likelihood ratio according to sequence is received；The likelihood ratio computing module includesRecurrence connects a calculation stages successively, and the bit hard decision module carries out symbol judgement output decoding result according to a pair of of likelihood ratio that final stage exports.The present invention only decodes an adjacent channel at least information bit in pairs, the number of likelihood ratio computing unit can be efficiently reduced while shortening the decoding period and reduces opening times, and then the overall power of decoder is reduced, entire decoder is finally allow to achieve the purpose that quick low-power consumption.

Description

A Partially Decoded Polar Code Serial Cancellation Decoding Circuit and Its Method

technical field

The invention belongs to the technical field of network communication, and in particular relates to a partial decoding polar code serial cancellation decoding circuit and method.

Background technique

Polar code (Polar Code) is the latest coding method in the coding field, and it is also the most concerned coding method. Its proposal is a major breakthrough in the coding field, and it is proposed based on the channel polarization theory. Polar codes have a deterministic construction method and are the only known channel coding method that can be rigorously proven to "reach" the channel capacity. Compared with other coding methods, the lower complexity and the error correction performance that can reach the Shannon limit will make polar codes an important candidate for error correction schemes in the next generation of digital communication and storage fields.

In the prior art, the decoding speed and power consumption of the polar code serial offset decoding circuit have been significantly improved, and basically all adjacent channels need to be decoded in pairs with fixed bits, which will bring The redundant calculation of the likelihood ratio calculation unit not only increases power consumption, but also brings decoding delay, reduces data throughput, and increases hardware overhead, and the traditional serial offset decoding algorithm completes one decoding The code needs 2N-2 decoding cycles, which is not applicable in some occasions where the real-time requirements of communication are relatively high. At present, most polar code serial offset decoding algorithms mainly focus on how to speed up the decoding speed, improve the data throughput rate or how to reduce power consumption, and pay little attention to the impact of the trade-off between the two on the performance of the entire decoder. . The decoding circuit of "A Stage-Reduced Low-Latency Successive Cancellation Decoder for Polar Codes" published by Liu Xing, Zhang Chuan and others at the IEEE international conference DSP (DigitalSignal Processing) in 2013 is relatively simple in the current serial offset decoding algorithm And fast circuits, in this article, the reduced-order processing of the likelihood ratio calculation is proposed, which greatly improves the decoding delay, reduces the decoding cycle from the traditional 2N-2 to N-2, and the data throughput rate doubled; but there are still the following problems: (1) the likelihood ratio calculation unit has redundant calculation problems, and the calculation amount is too large, resulting in increased power consumption; (2) the likelihood ratio reduction order serial offset decoding algorithm There is still room for reduction in the decoding cycle, and the cycle redundancy reduces the data throughput.

Contents of the invention

In order to overcome the problem that the existing polar code serial offset decoding algorithm does not unify the decoding speed and power consumption, the present invention proposes a partially decoded polar code serial offset decoding circuit and its method, aiming to speed up Decoding speed improves data throughput, reduces hardware overhead, avoids redundant calculation of likelihood ratio calculation units, reduces power consumption, and optimizes the overall decoding performance of the entire polar code serial decoder.

The technical scheme that the present invention adopts for achieving the above object is:

The characteristics of a partially decoded polar code serial cancellation decoding circuit of the present invention include: a binary phase shift keying modulation module, a likelihood ratio calculation module, and a bit hard decision module;

According to the channel polarization theory, fixed bits and information bits in the transmission channel are obtained; the binary phase shift keying modulation module receives the coded sequence {X ₁ , X ₂ ,...,X _i ,..., X _N } Calculate the initial likelihood ratio of each codeword Among them, X _i represents the i-th code, y _i represents the i-th channel, Indicates the initial likelihood ratio of the i-th code X _i , N is the code length of the polar code, i=1,2,...,N;

The likelihood ratio calculation module receives the initial likelihood ratio and before The stage is recursively calculated to get the first Two pairs of likelihood ratios for the stage; judging the Whether any pair of likelihood ratios in the stage is transmitted in fixed bits, and if so, then in the The stage does not calculate the corresponding likelihood ratio, and directly outputs fixed bits; otherwise, in the stage to calculate the corresponding likelihood ratio, and get the first A pair of likelihood ratios of the stage are output to the bit hard decision module;

The bit hard decision module receives the pair of likelihood ratios and outputs the decoded bits after symbol judgment; at the same time, the likelihood ratio calculation module receives the decoded bits fed back by the bit hard decision module for the likelihood ratio calculation.

A kind of polar code serial offset decoding method of partial decoding of the present invention is characterized in following steps:

Step 1. Obtain fixed bits and information bits in the transmission channel according to the channel polarization theory;

Step 2. After modulating the coded sequence {X ₁ ,X ₂ ,...,X _i ,...,X _N } in the transmission channel and adding additive white Gaussian noise, the received sequence {Y ₁ ,Y ₂ , …,Y _i ,…,Y _N }; then according to the received sequence {y ₁ ,y ₂ ,…,y _i ,…,y _N }, use formula (1) to get the initial likelihood ratio

In formula (1), δ ² is the variance, y _i is the codeword of the i-th code _Xi after interference, Indicates the initial likelihood ratio of the i-th code X _i , i=1, 2,..., N, where N is the code length of the polar code;

Step 3, first stage vs. the initial likelihood ratio Perform recursive calculation to get the first Two pairs of likelihood ratios for the stages;

Step 4, judge the first Whether any pair of likelihood ratios in the stage is transmitted in fixed bits, and if so, then in the The stage does not calculate the corresponding likelihood ratio, and directly outputs fixed bits; otherwise, in the stage to calculate the corresponding likelihood ratio, and get the first After a pair of likelihood ratios in the stage, go to step 5;

Step 5. Perform sign decision processing on the pair of likelihood ratios to obtain the decoded bits in the current cycle;

Step 6. Feedback the decoded bits to step 3 for calculation of the likelihood ratio of the next cycle.

Compared with the prior art, the beneficial technical effect of the present invention is reflected in:

1. The polar code serial offset decoding circuit and method of the present invention only perform pairwise decoding on at least one information bit of an adjacent channel, if the first Any pair of likelihood ratios in the stage is transmitted in fixed bits, then in the The stage does not calculate the corresponding likelihood ratio, and directly outputs fixed bits; otherwise, in the The stage calculates the corresponding likelihood ratio, and simplifies and optimizes the calculation structure of the likelihood ratio, thereby reducing the complexity of the likelihood ratio calculation.

2. The present invention can replace the final stage of the likelihood ratio calculation with a bit hard decision module without reducing the decoding accuracy, and only perform pairwise decoding on at least one information bit of the adjacent channel, which significantly speeds up The decoding speed is improved, and the decoding cycle is reduced from the traditional 2N-2 to approximately The real-time requirements of the decoder are enhanced, and the data throughput rate and decoding efficiency are improved.

3. The present invention simplifies the likelihood ratio calculation structure on the basis of the traditional offset decoding algorithm. If a pair of bits serially decoded is a fixed bit, it is not necessary to calculate the likelihood ratio, thereby effectively reducing the likelihood ratio. Compared with the calculation amount of the calculation unit, the power consumption of the entire decoder is greatly reduced.

4. The present invention aims at reducing power consumption and speeding up the decoding speed as the design goals, and uses part of the decoding algorithm to realize the unification of speed and power consumption, which not only speeds up the decoding speed, but also reduces power consumption, thereby improving the overall The decoding performance of the decoder.

Description of drawings

Fig. 1 is a structural diagram of a traditional serial offset decoding algorithm;

Fig. 2 is the structural diagram of partial decoding algorithm of the present invention;

Fig. 3 is a schematic diagram of the bit hard decision module of the present invention.

Detailed ways

In this embodiment, for the convenience of description, it is assumed that the polar code length N=8, based on the channel polarization, the information bits A=(4,6,7,8), and the fixed bits A ^c =(1,2 , 3, 5), the fixed bit transmission bit '0', the likelihood ratio calculation module is divided into two stages, stage 1, stage 2, as shown in Figure 2; assume that the encoded codeword sequence is V=( 0 0 0 1 0 1 1 1), perform binary phase shift keying modulation on the encoded sequence to obtain the modulated sequence S=(+1+1+1-1+1-1-1-1), and add the mean value to the modulated sequence μ=0, additive Gaussian white noise with variance δ ² =0.5 Obtain receiving sequence Y=(-0.5+2.2+1.8-1.2-0.2-0.9-1.2-1), calculate initial likelihood ratio according to formula (1);

As shown in Figure 2, a partial decoding polar code serial cancellation decoding circuit includes: a binary phase shift keying modulation module, a likelihood ratio calculation module, and a bit hard decision module;

According to the channel polarization theory, the fixed bits ^Ac =(1,2,3,5) and the information bits A=(4,6,7,8) in the transmission channel are obtained; among them, the binary phase shift keying modulation module Receive the code sequence {X ₁ ,X ₂ ,…,X _i ,…,X _N } in the transmission channel, and calculate the initial likelihood ratio of each codeword according to formula (1) Among them, X _i represents the i-th code, y _i represents the i-th channel, Indicates the initial likelihood ratio of the i-th code X _i , N is the code length of the polar code, i=1,2,...,N;

The likelihood ratio calculation module receives the initial likelihood ratio and before The stage is recursively calculated to get the first Two pairs of likelihood ratios for the stage; judging the Whether any pair of likelihood ratios in the stage is transmitted in fixed bits, and if so, then in the The stage does not calculate the corresponding likelihood ratio, and directly outputs fixed bits; otherwise, in the stage to calculate the corresponding likelihood ratio, and get the first A pair of likelihood ratios in the stage are output to the bit hard decision module; as shown in Figure 2, u ₁ u ₂ ... u ₈ represent coded bits, and the code length of the polar code is _N = ₈ . When decoding, since u ₁ u ₂ are a pair of adjacent fixed bits, stage 2 does not calculate the corresponding likelihood ratio, and directly outputs the decoded bits And the decoding is performed in pairs. For u ₃ u ₄ , u ₅ u ₆ , u ₇ u ₈ since their adjacent channels have at least one information bit, the corresponding likelihood ratio is calculated in the second stage, As shown in Figure 3, the pair of likelihood ratios obtained in stage 2 are input to the bit hard decision module, and the sign bits of the pair of likelihood ratios are XORed to obtain odd decoding bits, and the sign with a larger likelihood bit output as an even decoded bit;

The bit hard decision module receives a pair of likelihood ratios and performs sign judgment and then outputs the decoded bits. Using the decision function of the following formula, the pair of likelihood ratios in stage 2 are input to the bit hard decision module for symbol decision. If the likelihood ratio Then it is decoded as 0, otherwise it is decoded as 1;

At the same time, the likelihood ratio calculation module receives the decoding bits fed back by the bit hard decision module for the calculation of the likelihood ratio, as shown in Figure 2, the decoding output of the bit hard decision module Feedback input to the 4 g computing units of stage 1, Feedback is input to the 4th and 8th g computing units of stage 2.

In this embodiment, a partially decoded polar code serial cancellation decoding method is performed in the following steps:

Step 1. Obtain fixed bits and information bits in the transmission channel according to the channel polarization theory;

Step 2. After modulating the coded sequence {X ₁ ,X ₂ ,…,X _i ,…,X _N } in the transmission channel and adding additive white Gaussian noise, the received sequence {Y ₁ ,Y ₂ ,…, Y _i ,…,Y _N }; then according to the received sequence {y ₁ ,y ₂ ,…,y _i ,…,y _N }, use formula (1) to get the initial likelihood ratio

In formula (1), δ ² is the variance, y _i is the codeword of the i-th code _Xi after interference, Indicates the initial likelihood ratio of the i-th code X _i , i=1,2,...,N, N is the code length of the polar code; here it is assumed that the encoded codeword sequence is {0 0 0 1 01 1 1 }, carry out binary phase shift keying modulation on the encoded codeword to obtain the modulation sequence {+1+1+1-1+1-1-1-1}, and add the mean value μ=0 to the modulated sequence, and the variance is δ The additive Gaussian white noise of ² , obtains the receiving sequence Y, here adds the additive Gaussian white noise of mean value μ=0, variance δ ² =0.5 (taking noise samples) Then accept the sequence Y=(-0.5+2.2+1.8-1.2-0.2-0.9-1.2-1), calculate the likelihood ratio of the preliminary test according to formula (1);

Step 3, first stage-to-initial likelihood ratio Perform recursive calculation to get the first Two pairs of likelihood ratios for the stages;

Step 4, judge the first Whether any pair of likelihood ratios in the stage is transmitted in fixed bits, and if so, then in the The stage does not calculate the corresponding likelihood ratio, and directly outputs fixed bits; otherwise, in the stage to calculate the corresponding likelihood ratio, and get the first After a pair of likelihood ratios in the stage, go to step 5;

Step 5. Perform sign decision processing on the pair of likelihood ratios to obtain the decoded bits in the current cycle;

Step 6, feeding back the decoded bits to step 3 for the calculation of the likelihood ratio of the next cycle;

As shown in Figure 2, the coding sequence is (x ₁ ,x ₂ ,…x ₈ ), and the initial likelihood ratio generated after binary phase shift keying modulation is The number in the upper right corner of the likelihood ratio calculation unit f and g indicates which clock cycle it is turned on, and its entire SC decoding structure is similar to the DFT of the FFT butterfly diagram calculation sequence, 1), when T=1, The 4 groups of f factors in stage 1 receive the initial likelihood ratio; 2), when T=2, the 2 groups of g factors in stage 2 receive the output result of T=1, and transmit the obtained 2 calculated values to the bit hard decision module , decoding 3), when T=3, the 4 groups of g factors in stage 1 receive the initial test likelihood ratio; 4), when T=4, the 2 groups of f factors in stage 2 receive the output results of T=3, and the obtained 2 The calculated value is transmitted to the bit hard decision module, and the decoding 5), when T=5, the two groups of g factors in stage 2 receive the output result of T=3, and transmit the two calculated values obtained to the bit hard decision module for decoding

Formula (3) is f, for the receiving sequence, and for the receive sequence The upper and lower parts of Denotes subvectors with odd indices (u _k : 1≤k≤j; k odd), Represents a subvector with an even index (u _k :1≤k≤j; k even), sgn represents a sign function, and the sign Represents XOR operation, min means to go to the minimum value, '||' means to take the absolute value, in formula (4) that is g, Indicates the decoded bits.

In this embodiment, assuming that the code length of the polar code is N=8, the partially decoded polar code serial cancellation decoding algorithm is realized with Verilog HDL, and it is compared with the traditional serial cancellation decoding algorithm and the likelihood ratio reduction Decoding algorithm for comparison, as shown in Table 1;

Table 1 Performance comparison of three decoding algorithms

As shown in Figure 1, for the traditional serial offset decoding algorithm, the likelihood ratio calculation is divided into three stages: stage 1, stage 2, and stage3. It takes 14 cycles to complete a decoding, and the calculation unit is turned on 24 times. The calculation situation of the ratio calculation unit in each cycle is shown in Table 2;

Table 2 8-Bit traditional serial offset decoding cycle

As shown in Table 3, for the reduced-order decoding algorithm, the working conditions of the likelihood ratio calculation unit in each cycle are listed. It takes 6 cycles to complete a decoding, and the calculation unit is turned on 16 times;

Table 3 8-Bit reduced-order serial cancellation decoding cycle

As shown in Figure 2, the partial decoding system structure diagram only performs pairwise decoding on at least one information bit of the adjacent channel. In short, if the adjacent channel is a pair of fixed bits, no decoding is performed; As shown in Table 4, part of the decoding algorithm needs 5 cycles to complete a decoding, and the calculation unit is turned on 14 times. Compared with the traditional serial offset decoding, the hardware overhead of 10 likelihood ratio calculation units is reduced. The code cycle is reduced from the traditional 14 cycles to 5 cycles, and the data throughput rate is increased by about 2.3 times.

Table 4 8-Bit partial serial cancellation decoding cycle

As shown in Table 5, in this experiment, the partially decoded polar code serial cancellation decoding algorithm was implemented with Verilog HDL and the first-order Reduced-order serial cancellation decoding algorithm, ASIC adopts 180nm process, where code length N=8, fixed bit number K=4, code rate R=0.5, the resource consumption of some decoders is compared with that of reduced-order decoding The encoder is reduced by about 16%, and the power consumption is reduced by about 6%. As the code length N increases, there are more and more cases where the adjacent channel is a pair of fixed bits, so the longer the code length, the lower the power consumption will be.

Table 5 Comparison of partial decoding and reduced-order decoding measurement results, N=8, K=4, R=0.5

Claims (2)

1. a kind of polarization code of Partial Decode serially offsets decoding circuit, feature includes：Binary phase shift keying modulation module, Likelihood ratio computing module, bit hard decision module；

According to channel-polarization theory, fixed bit position and information bit position in transmission channel are obtained；The binary phase shift keying Modulation module receives the coded sequence { X in the transmission channel₁,X₂,…,X_i,…,X_NCalculate each code word it is initial seemingly So ratioWherein, X_iRepresent i-th of coding, y_iRepresent i-th of channel,Represent i-th of coding X_iInitial likelihood ratio, N be polarization code code length, i=1,2 ..., N；

The likelihood ratio computing module receives the initial likelihood ratio And precedingStage obtains through recursive calculationTwo pairs of likelihood ratios in stage；JudgeStage appoints Whether a pair of of likelihood ratio of meaning is transmitted in fixed bit position, if so, theStage does not count corresponding likelihood ratio It calculates, directly exports fixed bit；Otherwise,Stage calculates corresponding likelihood ratio, obtainsRank A pair of of likelihood ratio of section is simultaneously exported to the bit hard decision module；

The bit hard decision module receives the pair of likelihood ratio and carries out output decoding bit after symbol judgement；Meanwhile institute It states likelihood ratio computing module and receives the decoding bit of the bit hard decision module feedback for the calculating of likelihood ratio.

2. a kind of polarization code of Partial Decode serially offsets interpretation method, it is characterized in that carrying out as follows：

Step 1, according to channel-polarization theory, obtain fixed bit position and information bit position in transmission channel；

Step 2, to the coded sequence { X in the transmission channel₁,X₂,…,X_i,…,X_NBe modulated and add additive white gaussian After noise, obtain receiving sequence { Y₁,Y₂,…,Y_i,…,Y_N}；Further according to the reception sequence { y₁,y₂,…,y_i,…,y_N, profit Initial likelihood ratio is obtained with formula (1)

In formula (1), δ²For variance, y_iFor i-th of coding X_iCode word after being disturbed,Represent i-th of coding X_iIt is initial Likelihood ratio, i=1,2 ..., N, N are the code length of polarization code；

Step 3, precedingStage is to the initial likelihood ratioInto Row recursive calculation is obtained under current periodTwo pairs of likelihood ratios in stage；

Step 4 judgesWhether any pair of likelihood ratio in stage is transmitted in fixed bit position, if so, theStage does not calculate corresponding likelihood ratio, directly exports fixed bit；Otherwise,Stage is to corresponding Likelihood ratio calculated, obtainAfter a pair of of likelihood ratio in stage, step 5 is performed；

Step 5 carries out symbol judgement processing to the pair of likelihood ratio, obtains the decoding bit under current period；

Step 6 is decoded described in bit feedback to step 3, for the calculating of next cycle likelihood ratio.