CN108172565A - A kind of MOM capacitor and integrated circuit - Google Patents

Abstract

The application provides a kind of MOM capacitor and integrated circuit, the MOM capacitor include：Substrate；Shielded layer on substrate, shielded layer are flood structure；Positioned at shielded layer away from the cross layered more metal layers in one side of substrate and multilayer oxide layer；Every layer of metal layer includes multiple cross one another first interdigital structures and the second interdigital structure；The first interdigital structure and shielded layer short circuit in more metal layers in the metal layer of shielded layer；It insulate between the second interdigital structure and shielded layer in more metal layers in the metal layer of shielded layer.In the present invention shielded layer at least can between shielding metal leve and substrate apparent surface formed parasitic capacitance, so as to reduce some electrode of MOM capacitor relative to the parasitic capacitance of substrate, so that under homalographic, the capacitance bigger of MOM capacitor, increase the capacitance density of MOM capacitor so that MOM capacitor is more widely applied.

Description

A kind of MOM capacitor and integrated circuit

technical field

The invention relates to the technical field of manufacturing integrated circuit devices, in particular to an MOM capacitor and an integrated circuit.

Background technique

An integrated circuit (IC) usually includes various passive components, and a capacitor is a common passive component widely used in ICs in various applications. Two capacitor structures commonly used in the prior art are MIM (metal insulator metal, metal-insulator-metal) capacitors and MOM (metal oxide metal, metal-oxide-metal) capacitors. Typically, MIM capacitors include an insulator added between two layers of metal, while MOM capacitors consist of a large number of parallel "fingers" or electrodes formed on many metal layers.

In MIM capacitors, since the bottom plate shields the top plate, the parasitic capacitance is generally small. However, MIM capacitors require an additional mask during the manufacturing process, resulting in high manufacturing costs.

On the contrary, the production of MOM capacitors can usually easily generate metal layers through equipment, and with the development of process technology, the capacitance density gradually increases, and MOM capacitors are widely used. However, compared with the MIM capacitor, the parasitic capacitance of the two electrodes of the MOM capacitor is larger, so that the application of the MOM capacitor in the circuit is limited.

Contents of the invention

In view of this, the present invention provides a MOM capacitor and an integrated circuit to solve the problem of large parasitic capacitance between the two electrodes of the MOM capacitor in the prior art.

To achieve the above object, the present invention provides the following technical solutions:

A MOM capacitor, comprising:

Substrate;

a shielding layer located on the substrate, the shielding layer is a whole-layer structure;

A multi-layer metal layer and a multi-layer oxide layer cross-stacked on the side of the shielding layer away from the substrate; each layer of the metal layer includes a plurality of interdigitated first interdigitated structures and second interdigitated structures; The first interdigitated structures in the multilayer metal layers are electrically connected as the first electrode of the MOM capacitor, and the second interdigitated structures in the multilayer metal layers are electrically connected as the second electrode of the MOM capacitor. electrode;

The first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers is short-circuited with the shielding layer; the first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers The two-digit finger structure is insulated from the shielding layer.

Preferably, the projection of the multi-layer metal layer on the plane of the substrate is located within the projection of the shielding layer on the plane of the substrate.

Preferably, the shielding layer is a polysilicon layer.

Preferably, the polysilicon layer is a metal suicide polysilicon layer.

Preferably, the shielding layer is a metal layer.

Preferably, the edge of the projection of the shielding layer on the plane of the substrate is at least 2 microns wider than the edge of the projection of the multi-layer metal layer on the plane of the substrate.

Preferably, the edge of the projection of the shielding layer on the plane of the substrate is 2 microns wider than the edge of the projection of the multi-layer metal layer on the plane of the substrate.

The present invention also provides an integrated circuit, including: the MOM capacitor described in any one of the above.

Preferably, the integrated circuit is a charge pump.

Preferably, the charge pump is a cross-coupled charge pump.

It can be seen from the above-mentioned technical scheme that the MOM capacitor provided by the present invention forms a whole layer of shielding layer between the substrate and the multilayer metal layer, and the shielding layer can at least shield the metal layer and the substrate from forming on the opposite surface. The parasitic capacitance of the MOM capacitor reduces the parasitic capacitance of a certain electrode of the MOM capacitor relative to the substrate, thereby making the capacitance of the MOM capacitor larger under the same area, increasing the capacitance density of the MOM capacitor, and making the application of the MOM capacitor more efficient. widely.

The present invention also provides an integrated circuit. The integrated circuit includes the above-mentioned MOM capacitor. Since the parasitic capacitance of a certain terminal electrode of the MOM capacitor relative to the substrate becomes smaller, it can be applied in the integrated circuit, so that the integrated circuit The parasitic capacitance is reduced.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is a three-dimensional schematic diagram of a MOM capacitor in the prior art;

2 is a schematic cross-sectional view of a MOM capacitor in the prior art;

3 is a simplified equivalent circuit schematic diagram of a MOM capacitor in the prior art;

4 is a schematic cross-sectional view of the MOM capacitor provided in the embodiment of the present invention;

5 is a schematic diagram of a simplified equivalent circuit of the MOM capacitor provided in the embodiment of the present invention;

6 is a schematic cross-sectional view of another MOM capacitor provided in an embodiment of the present invention;

7 is a schematic cross-sectional view of another MOM capacitor provided in an embodiment of the present invention;

FIG. 8 is an equivalent circuit diagram of a charge pump without considering parasitic capacitance in the prior art;

Fig. 9a is an equivalent circuit diagram of a charge pump considering parasitic capacitance in the prior art;

FIG. 9b is an equivalent circuit diagram of a charge pump provided in an embodiment of the present invention;

Fig. 10 is a timing control diagram of switches in the equivalent circuit diagrams shown in Fig. 8, Fig. 9a and Fig. 9b;

11 is an equivalent circuit diagram of a cross-coupled charge pump without considering parasitic capacitance in the prior art;

Fig. 12a is an equivalent circuit diagram of a cross-coupled charge pump considering parasitic capacitance in the prior art;

FIG. 12b is an equivalent circuit diagram of a cross-coupled charge pump provided in an embodiment of the present invention;

FIG. 13 is a timing control diagram of clock signals in the equivalent circuit diagrams shown in FIG. 11 , FIG. 12 a , and FIG. 12 b.

Detailed ways

As mentioned in the background section, the parasitic capacitance of the MOM capacitor in the prior art is relatively large.

The inventors found that the reason for this phenomenon is that please refer to FIG. 1, which is a three-dimensional representation of a stacked metallization structure of a MOM capacitor 100. The MOM capacitor 100 is included in a plurality of metal layers M1-M6, wherein M1 is MOM The first layer of metal of the capacitor, M2 is the second layer of metal, Mn is the nth layer of metal, and each metal layer includes interdigitated fingers 110 and 120 . Interdigits 110 and 120 on different metal layers M1-M6 are connected by a plurality of vias and may be separated by an oxide layer (not shown in the figure). The fingers 110 in each metal layer are connected to each other to form the first electrode A of the MOM capacitor, and the fingers 120 in the multilayer metal layers are connected to each other to form the second electrode B of the MOM capacitor.

Please refer to FIG. 2 . FIG. 2 is a cross-sectional view of the MOM capacitor 100 . The capacitor in the MOM capacitor is a capacitor formed between metal sidewalls of the same layer. As shown in FIG. 2 , there is a large parasitic capacitance in the MOM capacitor, and the parasitic capacitance is mainly formed between the bottom and side surfaces of the fingers 110 and 120 and the upper surface of the substrate 01 . It should be noted that the first metal layer M1 is closest to the substrate, so the parasitic capacitance between it and the substrate O1 is the largest, and the metal layers M2...Mn above the first metal layer M1 are due to the barrier, relative to the parasitic capacitance of the substrate 01 is small, relative to the parasitic capacitance of the first metal layer M1 and the substrate 01 is negligible.

As shown in Figure 2, the parasitic capacitance of the first metal layer M1 to the substrate 01 includes two parts: one part is the parallel plate capacitance formed by the bottom surface of the first metal layer M1 and the substrate 01, and the other part is the first A sidewall capacitance is formed between the sidewall of the metal layer M1 and the substrate, and actually the capacitance of the parallel plate capacitance is larger than that of the sidewall capacitance. These two kinds of parasitic capacitances are collectively denoted as Cp1, and the parasitic capacitances of the first electrode A and the second electrode B to the substrate 01 are the same, each occupying Cp1/2, that is, in FIG. 3 , Cp=Cp1/2. Fig. 3 is a schematic diagram of a simplified equivalent circuit of Fig. 2, wherein, the capacitance Cmom is the MOM capacitance actually needed by the MOM capacitance, and Cp is the unwanted parasitic capacitance. It should be noted that the ground terminal in Fig. 3 is The substrate 01 in FIG. 2 is grounded during actual use, so the substrate is equivalent to a ground terminal. It can be known from the prior art that both electrodes have parasitic capacitance relative to the substrate, and the parasitic capacitance is relatively large.

Based on this, the present invention provides a kind of MOM capacitor, comprising:

Substrate;

a shielding layer located on the substrate, the shielding layer is a whole-layer structure;

A multi-layer metal layer and a multi-layer oxide layer cross-stacked on the side of the shielding layer away from the substrate; each layer of the metal layer includes a plurality of interdigitated first interdigitated structures and second interdigitated structures; The first interdigitated structures in the multilayer metal layers are electrically connected as the first electrode of the MOM capacitor, and the second interdigitated structures in the multilayer metal layers are electrically connected as the second electrode of the MOM capacitor. electrode;

The first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers is short-circuited with the shielding layer; the first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers The two-digit finger structure is insulated from the shielding layer.

The MOM capacitor provided by the present invention, by forming a whole layer of shielding layer between the substrate and the multilayer metal layer, the shielding layer can at least shield the parasitic capacitance formed on the opposite surface between the metal layer and the substrate, thereby reducing The parasitic capacitance of the MOM capacitor is reduced, so that under the same area, the capacitance of the MOM capacitor is larger, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is more extensive.

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a cross-sectional structure of a MOM capacitor provided in an embodiment of the present invention. The MOM capacitor includes:

substrate1;

A shielding layer 2 located on the substrate 1, the shielding layer 2 is a whole-layer structure;

Multi-layer metal layers (Mm...Mn) and multi-layer oxide layers (not shown in the figure) stacked cross-stacked on the side of the shielding layer 2 away from the substrate 1; each layer of the metal layer includes a plurality of The first interdigitated structure A0 and the second interdigitated structure B0 intersect each other; the first interdigitated structure in the multi-layer metal layer is electrically connected as the first electrode A of the MOM capacitor, and the multi-layer metal layer The second interdigitated structure in is electrically connected as the second electrode B of the MOM capacitor;

The first interdigitated structure A0 in the metal layer Mm closest to the shielding layer 2 in the multi-layer metal layers (Mm...Mn) is short-circuited with the shielding layer 2; the multi-layer metal layers (Mm... ... Mn) is insulated from the second interdigitated structure B0 in the metal layer Mm closest to the shielding layer 2 and the shielding layer 2 .

As shown in FIG. 4, the first interdigitated structure A0 in the lowermost metal layer Mm is directly electrically connected to the shielding layer 2, and the second interdigitated structure B0 in the lowermost metal layer Mm is connected to the shielding layer 2. Layer 2 is insulated to form a capacitor.

As shown in FIG. 5 , it is an equivalent circuit diagram of a MOM capacitor provided by an embodiment of the present invention, wherein the ground terminal is also the substrate 1 shown in FIG. 4 in this embodiment. The capacitance Cmom between the first electrode A and the second electrode B is the capacitance formed by the sidewalls of multiple interdigitated structures of the same layer in the MOM capacitance. The capacitance Cp2 formed between the shielding layer 2 and the second interdigitated structure B0 in FIG. 4 is also included between the first electrode A and the second electrode B. Since the first electrode A is directly connected to the shielding layer 2 , the parasitic capacitance between the shielding layer 2 and the substrate 1 is also the parasitic capacitance Cp3 between the first electrode A and the ground.

Comparing the equivalent circuit diagrams of FIG. 5 and FIG. 3, it can be seen that the MOM capacitor provided by the embodiment of the present invention shields the parasitic capacitance Cp between the second electrode B and the substrate 1 in FIG. 3 due to the existence of the shielding layer. , the parasitic capacitance disappears. A parallel parasitic capacitance Cp2 is also added between the first electrode A and the second electrode B. According to the principle of capacitance parallel connection, the capacitance value between the first electrode A and the second electrode B is increased, that is, the MOM capacitance is increased. the capacitance value. It should be noted that there is also a parasitic capacitance Cp3 between the first electrode A and the substrate, but in actual application, such as in the charge pump example shown below in the present invention, the parasitic capacitance of the first electrode A relative to the substrate Cp3 is acceptable. It only needs to reduce or eliminate the parasitic capacitance of the second electrode B.

It should be noted that the material of the shielding layer is not limited in this embodiment, as long as it has a certain conductivity, can form a parasitic capacitance with the metal layer on it, and can be short-circuited, so that the metal layer and the substrate The parasitic capacitance between the bottom can be reduced. Optionally in this embodiment, the shielding layer is a polysilicon layer or a metal layer with relatively low impedance.

In the integrated circuit manufacturing process, a multi-layer metal layer will be formed, pointing from the substrate to the direction away from the substrate, including the first metal layer M1, the second metal layer M2 ... the nth metal layer Mn, as described in this embodiment The shielding layer may be a certain layer structure in the multi-layer metal layers.

Please refer to FIG. 6. FIG. 6 shows that the first metal layer M1 in the integrated circuit is made into a whole-layer structure for forming the shielding layer 12 in the embodiment of the present invention. At this time, since the first metal layer M1 is a whole-layer structure , forming a parasitic capacitance Cp3 between it and the substrate 11 , and forming a parasitic capacitance Cp2 with the second interdigitated structure in the second metal layer M2 above it, which is directly short-circuited with the first interdigitated structure.

In addition, in this embodiment, other metal layers can also be used as the shielding layer. At this time, the metal layer between the shielding layer and the substrate does not exist, and cannot be used as the interdigitated structure of the MOM capacitor. In this way, the utilization rate of the metal layer is reduced.

For this reason, in another embodiment of the present invention, a polysilicon layer can also be added as a shielding layer between the multi-layer metal layer and the substrate. Make one layer of polysilicon layer, but adopt the polysilicon layer in the integrated circuit in the prior art as the shielding layer in this embodiment, for example, if there is a MOS transistor in the integrated circuit, then the polysilicon layer when making the gate of the MOS transistor gets final product Extending to the top of the MOM capacitor substrate described in this embodiment is used as a shielding layer, that is, the gate polysilicon layer that has no other effect in the prior art is used as a shielding layer of the MOM capacitor in this embodiment. In the manufacturing process, The manufacturing steps of the MOM capacitor in this embodiment are not added.

Please refer to FIG. 7 . FIG. 7 shows a structure in which a polysilicon layer is used as a shielding layer. At this time, the polysilicon layer 22 is located between the substrate 21 and the first metal layer M1 . Compared with the MOM capacitor shown in FIG. 5 , the metal layer of the MOM capacitor is not occupied in this embodiment, so that the capacitance of the MOM capacitor is larger.

The type of the polysilicon is not limited in this embodiment. Optionally, the polysilicon layer is metal silicided polysilicon (silicided poly-Si) with a small square resistance, so that the overall resistance of the shielding layer is small and the shielding effect is relatively high. it is good.

In the above embodiments of the present invention, the size of the shielding layer is not limited, as long as the shielding layer can shield the parasitic capacitance between the second finger structure in the metal layer and the substrate. It should be noted that when the shielding layer is small, the parasitic capacitance between the sidewall of the second interdigitated structure at the edge and the substrate may not be shielded, so that the second electrode of the MOM capacitor and the substrate The parasitic capacitance cannot be completely shielded.

In order to reduce the parasitic capacitance between the second electrode of the MOM capacitor and the substrate (including the parasitic capacitance formed by the bottom surface and the substrate, and the parasitic capacitance formed by the sidewall and the substrate), the multilayer metal layer described in this embodiment The projection on the plane of the substrate lies within the projection of the shielding layer on the plane of the substrate.

In order to avoid the excessive area of the shielding layer from affecting other devices in the integrated circuit, the edge of the projection of the shielding layer on the plane of the substrate in this embodiment is larger than that of the multi-layer metal layer on the substrate. The edges of the projection on the plane are extended by at least 2 microns. Preferably, during the manufacturing process, the edge of the projection of the shielding layer on the plane of the substrate can be expanded by 2 microns than the edge of the projection of the multi-layer metal layer on the plane of the substrate. In this implementation This is not limited in this example, and can be selected and designed according to the production of the actual integrated circuit and the components in the integrated circuit.

The MOM capacitor provided by the present invention, by forming a whole layer of shielding layer between the substrate and the multilayer metal layer, the shielding layer can at least shield the parasitic capacitance formed on the opposite surface between the metal layer and the substrate, thereby reducing The parasitic capacitance of the MOM capacitor is reduced, so that under the same area, the capacitance of the MOM capacitor is larger, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is more extensive.

The present invention also provides an integrated circuit, which includes the MOM capacitor described in all the above embodiments.

It should be noted that the specific structure of the integrated circuit is not limited in this embodiment, as long as the integrated circuit includes a MOM capacitor, the MOM capacitor with a shielding layer described in the above embodiments of the present invention can be used, thereby reducing one of the The parasitic capacitance of the electrode to the substrate increases the capacitance of the MOM capacitor.

In order to better illustrate the advantages of the MOM capacitor provided in the above embodiments of the present invention, in the embodiments of the present invention, the integrated circuit is used as a charge pump for description. The efficiency of the charge pump can be improved by using a MOM capacitor with a shield. details as follows:

Please refer to FIG. 8, FIG. 9a, FIG. 9b and FIG. 10, wherein FIG. 8 is an equivalent circuit diagram of a charge pump in the prior art, and FIG. 9a is an equivalent circuit diagram of a charge pump after considering parasitic capacitance, and Cmom is the MOM capacitance. Fig. 9b is the equivalent circuit diagram of the charge pump after shielding the parasitic capacitance of one electrode end of the MOM capacitor; Fig. 10 is the switch in the equivalent circuit diagram shown in Fig. 8, Fig. 9a and Fig. 9b and timing control chart.

Neglecting the switching loss, the efficiency of the charge pump shown in Figure 8 can reach 100% when the clock is ideal, and the output voltage is:

Vcpout=2*Vdd

In Figure 9a, the parasitic capacitance Cp of the MOM capacitor at the second electrode B terminal to ground will affect the charge pump efficiency:

During the high level period, the first electrode point A of the MOM capacitor is connected to the ground, the second electrode point B is charged to Vdd, and the total charge stored at the second electrode point B is:

Φ2 is a high level period, the first electrode A point of the MOM capacitor is connected to VDD, the second electrode B point is connected to Cpout, and the voltage across the parasitic capacitance Cp of the second electrode B point is determined by Vdd( During high level) to Vcpout ( is a high level period), the total charge at point B of the second electrode is:

The charge at point B is conserved, so:

which is,

(Cmom+Cp)*Vdd＝Cmom*(Vout–Vdd)+Cp*Vout

get

If Cp/Cmom=0.1, then Vout=1.91*Vdd, the efficiency of the charge pump is 95.5%.

It can be seen that the efficiency of the charge pump is affected by the parasitic capacitance of the second electrode B to ground.

The MOM capacitor structure with the shielding layer described in the above embodiment of the present invention is adopted in Fig. 9b, and the second electrode B terminal of the MOM capacitor has no parasitic capacitance to the ground, that is, Cp=0 in the above formula, and the charge pump efficiency is not high. Affected, and under the same area, more Cp2 between the first electrode A and the second electrode B is connected in parallel with the original MOM capacitance, so that the MOM capacitance density increases (wherein, the parasitic capacitance Cp3 of the A terminal to the ground does not affect the charge pump efficiency).

It can be seen that the use of the MOM capacitor with a shielding layer described in the embodiment of the present invention can improve the efficiency of the charge pump, increase the capacitance of the MOM capacitor, and increase the density of the MOM capacitor under the same area.

Another embodiment of the present invention also provides a cross-coupled charge pump, the structure of which is shown in Figure 11, Figure 12a, Figure 12b and Figure 13, wherein Figure 11 is an equivalent circuit diagram of a charge pump in the prior art, Figure 12a is the equivalent circuit diagram of the charge pump after considering the parasitic capacitance, and Cmom is the MOM capacitance. Fig. 12b is the equivalent circuit diagram of the charge pump after shielding the parasitic capacitance of one electrode end of the MOM capacitor; Fig. 13 is the timing control diagram of clock signals Clk1 and Clk2 in the equivalent circuit diagram shown in Fig. 11, Fig. 12a, and Fig. 12b;

Specifically, Figure 11 is a charge pump structure using two flying capacitors (flying capacitors refer to fast charging capacitors, which are capacitors C1 and capacitors C2 in Figure 11, and the capacitors between A and B in Figure 8 are also flying capacitors). In the embodiment, the switching transistor M1 and the switching transistor M3 are NMOS, and the switching transistors M2 and M4 are PMOS switching transistors as an example for illustration.

Neglecting switching losses, the charge pump efficiency can reach 100% under ideal clock conditions, and the output voltage is:

Vout=Vin+Vdd

Similarly, according to the principle of charge conservation, it can be deduced that in Figure 12a, when both nodes M and N have parasitic capacitance Cp to ground, the output voltage of the charge pump is:

The parasitic capacitance Cp affects the charge pump efficiency.

As shown in Figure 12b, the MOM capacitor structure with a shielding layer described in the above embodiment of the present invention can be used to shield the parasitics of the M and N points to the ground, but the clock access terminal Clk1 and the clock access terminal The parasitic capacitance of Clk2 to ground basically has no effect on the efficiency of the charge pump, and it is only necessary to increase the size of the inverter so that the inverter has sufficient driving capability.

Therefore, using the MOM capacitor with the shielding layer described in the embodiment of the present invention in this embodiment can improve the efficiency of the charge pump, increase the capacitance of the MOM capacitor, and increase the density of the MOM capacitor under the same area.

It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts in each embodiment, refer to each other, that is, Can.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A MOM capacitor, characterized in that, comprising: Substrate; a shielding layer located on the substrate, the shielding layer is a whole-layer structure; A multi-layer metal layer and a multi-layer oxide layer cross-stacked on the side of the shielding layer away from the substrate; each layer of the metal layer includes a plurality of interdigitated first interdigitated structures and second interdigitated structures; The first interdigitated structures in the multilayer metal layers are electrically connected as the first electrode of the MOM capacitor, and the second interdigitated structures in the multilayer metal layers are electrically connected as the second electrode of the MOM capacitor. electrode; The first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers is short-circuited with the shielding layer; the first interdigitated structure in the metal layer closest to the shielding layer among the multiple metal layers The two-digit finger structure is insulated from the shielding layer. 2 . The MOM capacitor according to claim 1 , wherein the projection of the multilayer metal layer on the plane of the substrate is located within the projection of the shielding layer on the plane of the substrate. 3 . 3. The MOM capacitor according to claim 2, wherein the shielding layer is a polysilicon layer. 4. The MOM capacitor according to claim 3, wherein the polysilicon layer is a metal suicide polysilicon layer. 5. The MOM capacitor according to claim 2, wherein the shielding layer is a metal layer. 6. The MOM capacitor according to any one of claims 2-5, wherein the edge of the projection of the shielding layer on the plane of the substrate is larger than that of the multilayer metal layer on the plane of the substrate. The edges of the projection on the plane are flared out by at least 2 microns. 7. The MOM capacitor according to claim 6, wherein the edge of the projection of the shielding layer on the plane of the substrate is larger than the projection of the multilayer metal layer on the plane of the substrate. The edge is spread out by 2 microns. 8. An integrated circuit, characterized by comprising: the MOM capacitor according to any one of claims 1-7. 9. The integrated circuit of claim 8, wherein the integrated circuit is a charge pump. 10. The integrated circuit of claim 9, wherein the charge pump is a cross-coupled charge pump.