CN108172253A - The driving circuit of memory and apply its memory - Google Patents
The driving circuit of memory and apply its memory Download PDFInfo
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- CN108172253A CN108172253A CN201711444707.1A CN201711444707A CN108172253A CN 108172253 A CN108172253 A CN 108172253A CN 201711444707 A CN201711444707 A CN 201711444707A CN 108172253 A CN108172253 A CN 108172253A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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Abstract
The present invention provides a kind of driving circuit of memory and applies its memory, the driving circuit of memory includes being connected to the first driving unit of the proximal end of inputoutput data signal wire and is connected to the second driving unit of the distal end of the inputoutput data signal wire, it can be respectively from the proximally and distally driving storage array of inputoutput data signal wire, to accelerate the write operation of memory.
Description
Technical field
The present invention relates to the driving circuit of semiconductor memory technologies field more particularly to a kind of memory and application its
Memory.
Background technology
Memory is higher and higher for clock frequency requirement, and correspondingly internal read-write operation is also required more rapidly.
It is the communication schematic diagram of memory commonly used in the prior art as shown in Figure 1.In the periphery design of memory, increasing can be passed through
Add assembly line or increase the size of driving tube to improve read or write speed.As shown in Fig. 2, memory 10 includes storage array 13, deposit
The storage unit 13A that storage array 13 includes multiple array distributions drives each storage by driving unit 11 and signal wire YIO '
Unit 13A.Longer signal wire YIO ' can become the bottleneck for improving read or write speed, even if the size of driving tube is increased two 3 times
As the limitation of resistance capacitance, the sequential of distal end (one end far from driving unit 11) is influenced.Another method be by
Storage array block splitting to improve read or write speed, but can increase chip size and production cost into smaller piece.
Invention content
The embodiment of the present invention provides a kind of driving circuit of memory and applies its memory, existing to solve or alleviate
One or more of technology technical problem.
As the one side of the embodiment of the present invention, the embodiment of the present invention provides a kind of driving circuit of memory, including：
First driving unit is connected to the proximal end of inputoutput data signal wire, for believing from the inputoutput data
The proximal end driving memory of number line；And
Second driving unit is connected to the distal end of the inputoutput data signal wire, for from the input and output number
The memory is driven according to the distal end of signal wire.
In some embodiments, the inputoutput data signal wire includes：
First inputoutput data signal wire is used for transmission the first inputoutput data signal；And
Second inputoutput data signal wire is used for transmission the second inputoutput data signal, wherein, first input
Outputting data signals and the second inputoutput data signal are Difference signal pair；
Second driving unit includes：
Sense amplifier is connected to the distal end of the first inputoutput data signal wire and the second input and output number
According to the distal end of signal wire, for the first inputoutput data signal and the second inputoutput data signal to be put respectively
Greatly；And
Feedback enhancing circuit is connected to the output terminal of the sense amplifier, for defeated according to the amplified first input
Go out data-signal to draw high the distal end of the first inputoutput data signal wire to output supply voltage or be pulled low to ground connection electricity
Pressure and for according to amplified second inputoutput data signal by the distal end of the second inputoutput data signal wire
It draws high to supply voltage or is pulled low to ground voltage, to drive the memory.
In some embodiments, second driving unit further includes prewired circuit, be connected to the sense amplifier and
Between the feedback enhancing circuit, for the sense amplifier to be made to be in equilibrium state before work.
In some embodiments, second driving unit further includes reset-set latch, is connected to described sensitive put
Between big device and the feedback enhancing circuit, for latching amplified first inputoutput data signal and amplified second
Inputoutput data signal.
In some embodiments, the feedback enhancing circuit includes：
First feedback enhancing sub-circuit, is connected to the reset-set latch and the first inputoutput data signal
Between the distal end of line, for the output according to the reset-set latch by the remote of the first inputoutput data signal wire
It draws high to supply voltage or is pulled low to ground voltage in end；And
Second feedback enhancing sub-circuit, is connected to the reset-set latch and the second inputoutput data signal
Between the distal end of line, for the output according to the reset-set latch by the remote of the second inputoutput data signal wire
It draws high to supply voltage or is pulled low to ground voltage in end.
In some embodiments, the sense amplifier includes cross coupled amplifier, and it is defeated to be connected to first input
Go out the distal end of data signal line and the distal end of the second inputoutput data signal wire, for respectively that the described first input is defeated
Go out data-signal and the second inputoutput data signal cross coupling amplification.
In some embodiments, the sense amplifier further includes：
The first transistor, the grid of the first transistor are connected to the remote of the first inputoutput data signal wire
End, the source electrode of the first transistor are connected to the cross coupled amplifier；And
Second transistor, the grid of the second transistor are connected to the remote of the second inputoutput data signal wire
End, the source electrode of the second transistor are connected to the cross coupled amplifier；
Wherein, the first transistor drain electrode and the drain electrode of the second transistor link together, when described first
When transistor and the second transistor are connected, the first transistor, the cross coupled amplifier and second crystal
Pipe is formed into a loop.
In some embodiments, the drain electrode of the first transistor is connected to amplification enable signal by the first phase inverter,
For making the drain electrode input of the drain electrode of the first transistor and the second transistor and the amplification enable signal reverse phase
Level signal.
In some embodiments, second driving unit includes：
First amplification feedback circuit is connected to the distal end of the inputoutput data signal wire, for defeated in the input
When going out the distal end output high level of data signal line, the distal end of the inputoutput data signal wire is drawn high to supply voltage；
And
Second amplification feedback circuit is connected to the distal end of the inputoutput data signal wire, for defeated in the input
When going out the distal end output low level of data signal line, the distal end of the inputoutput data signal wire is pulled low to ground voltage.
In some embodiments, the first amplification feedback circuit includes：
Logic NAND gate, there are two input terminals for tool, are connected to the distal end of the inputoutput data signal wire and put
Big enable signal and
PMOS transistor, the grid of the PMOS transistor are connected to the output terminal of the logic NAND gate, the PMOS
The source electrode of transistor is connected to supply voltage, and the drain electrode of the PMOS transistor is connected to the inputoutput data signal wire
Distally.
In some embodiments, the second amplification feedback circuit includes：
Second phase inverter is connected to the amplification enable signal；
Logic nor gate including two input terminals, is connected to distal end and the institute of the inputoutput data signal wire
State the second phase inverter output terminal and
NMOS transistor, the grid of the NMOS transistor are connected to the output terminal of the logic nor gate, the NMOS
The source electrode ground connection of transistor, the drain electrode of the NMOS transistor are connected to the distal end of the inputoutput data signal wire.
As the other side of the embodiment of the present invention, the present invention implements also to provide a kind of memory, including as described above
Driving circuit.
The embodiment of the present invention use above-mentioned technical proposal, can respectively from inputoutput data signal wire proximally and distally
Storage array is driven, to accelerate the write operation of memory.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature will be what is be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent the same or similar through the identical reference numeral of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the communication schematic diagram of memory of the prior art.
Fig. 2 is the structure diagram of memory of the prior art.
Fig. 3 is the structure diagram of the memory of embodiment one.
Fig. 4 is the circuit diagram of the second driving unit of the memory of embodiment one.
Fig. 5 is the structure diagram of the memory of embodiment two.
Fig. 6 is the circuit diagram of the second driving unit of the memory of embodiment two.
Reference sign：
The prior art：
10：Memory； 11：Driving unit； 13：Storage array；
13A：Storage unit； YIO′：Signal wire.
The embodiment of the present invention：
100：Memory；
110：First driving unit； 120：Second driving unit； 130：Storage array；
131：Storage unit； 140：Row decoding and row address control；
YIO1：First inputoutput data signal wire； YIO2：Second inputoutput data signal wire；
YIO1_near、YIO2_near：Proximal end； YIO1_far、YIO2_far：Distally；
121：Sense amplifier； 1211：Cross coupled amplifier；
1212：The first transistor； 1213：Second transistor；
122：Feedback enhancing circuit； 1221：First feedback enhancing sub-circuit；
1222：Second feedback enhancing sub-circuit；
123：Prewired circuit； 124：RS latch；
125：First phase inverter； A、B、C、D：Port；
121A、121B、122A、122D、123A、123B、123C：PMOS transistor；
121C、121D、122B、122C：NMOS transistor；
122E：Third phase inverter； 122F：4th phase inverter；
G1、G2：Grid； S1、S2：Source electrode； D1、D2：Drain electrode；
SenseEn：Amplify enable signal；
VDD：Supply voltage； V1：Preset voltage；
200：Memory；
210：First driving unit； 220：Second driving unit；
YIO：Inputoutput data signal wire；
YIO_near：Proximal end； YIO_far：Distally；
221：First amplification feedback circuit； 222：Second amplification feedback circuit；
221A：Logic NAND gate； 221B：PMOS transistor；
222A：Second phase inverter； 222B：Logic nor gate； 222C：NMOS transistor；
G3、G4：Grid； S3、S4：Source electrode； D3、D4：Drain electrode；
A1、A2、B1、B2、：Input terminal； A3、B3、E：Output terminal.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be based on orientation shown in the drawings or
Position relationship is for only for ease of the description present invention and simplifies description rather than instruction or imply that signified device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are only used for description purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, " multiple " are meant that two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or integral；Can be that machinery connects
It connects or is electrically connected, can also be communication；It can be directly connected, can also be indirectly connected by intermediary, it can be with
It is the interaction relationship of connection inside two elements or two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature it " on " or it " under "
It can be in direct contact including the first and second features, it is not to be in direct contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " including fisrt feature
Right over second feature and oblique upper or fisrt feature level height is merely representative of higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " right over second feature and oblique upper or be merely representative of including fisrt feature
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.
Embodiment one
The memory 100 of the embodiment of the present invention is illustrated in figure 3, including the first driving unit 110, the second driving unit
120th, storage array 130, a plurality of inputoutput data signal wire and row decoding and row address control 140.The embodiment of the present invention
In, inputoutput data signal wire includes the first inputoutput data signal wire YIO1 and the second inputoutput data signal wire
YIO2 is respectively used to the first inputoutput data signal of transmission and the second inputoutput data signal, wherein, the first input and output
Data-signal and the second inputoutput data signal are Difference signal pair.
Storage array 130 includes multiple storage units 131, multiple 131 array distributions of storage unit, and storage unit 131 is
It is used to store the unit of byte in memory 100.A plurality of first inputoutput data signal wire YIO1 and the second input and output number
It is connected according to signal wire YIO2 by multiple along the storage unit 131 of straight line genesis analysis.
First driving unit 110 is connected to the proximal end YIO1_near and of the first inputoutput data signal wire YIO1
The proximal end YIO2_near of two inputoutput data signal wire YIO2, for proximally driving storage array 130, into line storage
100 read-write operation.
Second driving unit 120 is connected to the distal end YIO_far and second of the first inputoutput data signal wire YIO1
The distal end YIO2_far of inputoutput data signal wire YIO2, for driving storage array 130 from distal end, into line storage 100
Read-write operation.
The circuit diagram of the second driving unit 120 of the embodiment of the present invention is illustrated in figure 4, the second driving unit 120 includes
Sense amplifier 121, prewired circuit 123, reset-set (RS) latch 124 and feedback enhancing circuit 122.
The sense amplifier 121 of the embodiment of the present invention preferably includes cross coupled amplifier 1211, cross coupled amplifier
1211 include P type metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS)
Transistor is to 121A and 121B and NMOS transistor to 121C and 121D.Wherein, PMOS transistor is to the grid of 121A and 121B
Pole and NMOS transistor are to the grid cross-couplings of 121C and 121D, for by the first inputoutput data signal of distal end and the
It is exported after the amplification of two inputoutput data signals from port A and port B.It should be noted that the sensitive of the embodiment of the present invention is put
Big device 121 is not limited to cross coupled amplifier, as long as can be by the first inputoutput data signal of distal end and second
The amplification output of inputoutput data signal.
Sense amplifier 121 further includes the first transistor 1212 and second transistor 1213, wherein, the first transistor 1212
Grid G 1 be connected to the distal end YIO1_far of the first inputoutput data signal wire YIO1, source electrode or drain electrode (such as source S 1)
Cross coupled amplifier 1211 is connected to, drain electrode or source electrode (such as drain D 1) are connected to amplification by the first phase inverter 125 and make
Energy signal SenseEn, for that will be exported after the first micro- amplification of inputoutput data signal to cross coupled amplifier 1211.
The grid G 2 of second transistor 1213 is connected to the distal end YIO2_far of the second inputoutput data signal wire YIO2,
Source electrode or drain electrode (such as source S 2) are connected to cross coupled amplifier 1211, and drain electrode or source electrode (such as drain D 2) are connected to and put
Big enable signal SenseEn, for will be exported after the second micro- amplification of inputoutput data signal to cross coupled amplifier 1211.
Amplification enable signal SenseEn is to be used to control the signal whether sense amplifier 121 works in memory.When
When one inputoutput data signal and the second inputoutput data signal are differed by more than equal to 100 millivolts, amplify enable signal
When SenseEn exports low level signal, sense amplifier 121 is started to work.
In the present embodiment, the first transistor 1212 and second transistor 1213 all select N-type metal-oxide semiconductor (MOS)
(Negative channel Metal Oxide Semiconductor, NMOS) transistor.
Prewired circuit 123 is connected to the output terminal (port A and port B) of sense amplifier 121, including three PMOS crystal
Pipe 123A, 123B and 123C, wherein PMOS transistor 123C are coupled between port A and port B, the source of PMOS transistor 123A
Pole or drain electrode are connected to preset voltage V1 (for example, V1=VDD/2, wherein, VDD is the supply voltage that storage array 130 works),
Drain electrode or source electrode are connected to port A, and the source electrode of PMOS transistor 123B or drain electrode are connected to preset voltage V1, and drain electrode or source electrode connect
Port B is connected to, and the grid of PMOS transistor 123A, 123B and 123C link together, and is connected to the enabled letter of amplification
Number SenseEn.In the present embodiment, PMOS transistor 123A, 123B and 123C are pmos type, but this is not to prewired circuit
The restriction of 123 composition form.
When the first inputoutput data signal and the second inputoutput data signal difference are less than 100 millivolts, amplification makes
Can signal SenseEn output high level signal, sense amplifier 121 starts to work not yet, PMOS transistor 123A, 123B and
123C is connected under the control of amplification enable signal SenseEn, can make the output terminal (port A and port B) of sense amplifier 121
It is shorted together, and is shorted to preset voltage V1, sense amplifier 121 is made to be in equilibrium state before work；It is put when sensitive
When big device 121 works, PMOS transistor 123A, 123B and 123C are disconnected under the control of amplification enable signal SenseEn, that is, are held
Mouth A and port B is directly connected in next stage circuit respectively.
Two input terminals of RS latch 124 are connected to port A and port B, two output terminals (port C and ports
D) it is connected to feedback enhancing circuit 122.When sense amplifier 121 works, RS latch 124 is configured in sensitive for latching
The output signal of amplifier 121 inputs for latching amplified first inputoutput data signal and amplified second
Outputting data signals, and export and give feedback enhancing circuit 122.
It should be noted that prewired circuit 123 and RS latch 124 can increase respectively in connection with sense amplifier 121 and feedback
Forceful electric power road 122 is implemented, and can also be implemented in combination with sense amplifier 121 and feedback enhancing circuit 122, can not also be implemented,
That is sense amplifier 121 and feedback enhancing circuit 122 is directly connected to.
In the present embodiment, feedback enhancing circuit 122 includes the first feedback enhancing sub-circuit 1221 and second and feeds back enhancer
Circuit 1222, the first feedback enhancing sub-circuit 1221 are connected to 124 and first inputoutput data signal wire YIO1 of RS latch
Distal end YIO1_far between, when RS latch 124 port C export high level, port D output low level when, third reverse phase
Device 122E exports low level, PMOS transistor 122A conductings, and NMOS transistor 122B ends, the first inputoutput data signal
The distal end YIO1_far of line YIO1 is pulled to supply voltage VDD, conversely, the port C when RS latch 124 exports low level,
When port D exports high level, NMOS transistor 122B conductings, PMOS transistor 122A cut-offs, the first inputoutput data signal
The distal end YIO1_far of line YIO1 is pulled low to ground voltage.
Second feedback enhancing sub-circuit 1222 is connected to 124 and second inputoutput data signal wire YIO2's of RS latch
Between the YIO2_far of distal end, when the port C of RS latch 124 exports high level, and port D exports low level, NMOS transistor
122C is connected, the 4th phase inverter 122F output high level, PMOS transistor 122D cut-offs, the second inputoutput data signal wire
The distal end YIO2_far of YIO2 is pulled low to ground voltage, conversely, the port C when RS latch 124 exports low level, port D
When exporting high level, PMOS transistor 122D conductings, NMOS transistor 122C cut-offs, the second inputoutput data signal wire YIO2
Distal end YIO2_far be pulled to supply voltage VDD.
Second driving unit 120 according to embodiments of the present invention, when the first inputoutput data signal of distal end and second
When inputoutput data signal differential is more than or equal to 100mv, amplification enable signal SenseEn enables sense amplifier 121 and starts
Work, exports after the first inputoutput data signal and the second inputoutput data signal are amplified respectively；Feedback enhancing circuit
122 by the remote of the distal end YIO1_far of the first inputoutput data signal wire YIO1 and the second inputoutput data signal wire YIO2
End YIO2_far draws high rapidly to supply voltage VDD or is pulled low to ground voltage, so as to drive storage array from distal end, accelerates number
According to being written in storage array.
First driving unit of the embodiment of the present invention can proximally drive memory, and the second driving unit can drive from distal end
Dynamic memory, so as to improve the write operation speed of memory.The row operating interval time (time of cas to cas delay,
TCCD) for reflecting the read or write speed of memory, the technical solution of the embodiment of the present invention can improve tCCD.
Embodiment two
The memory 200 of the embodiment of the present invention is illustrated in figure 5, including the first driving unit 210, the second driving unit
220th, storage array 130, a plurality of inputoutput data signal wire YIO and row decoding and row address control 140.
First driving unit 210 is connected to the proximal end YIO_near of inputoutput data signal wire YIO, for defeated from inputting
Go out the proximal end YIO_near driving storage arrays 130 of data signal line YIO, thus the read-write operation into line storage 200.
Second driving unit 220 is connected to the distal end YIO_far of inputoutput data signal wire YIO, for defeated from inputting
Go out the distal end YIO_far driving storage arrays 130 of data signal line YIO, into the read-write operation of line storage 200.
As shown in fig. 6, the second driving unit 220, which includes the first amplification feedback circuit 221 and second, amplifies feedback circuit
222.First amplification feedback circuit 221 includes logic NAND gate 221A and PMOS transistor 221B, wherein, logic NAND gate 221A
There are two input terminal A1 and A2 for tool, are connected to the distal end YIO_far of inputoutput data signal wire YIO and the enabled letter of amplification
Number SenseEn；The grid G 3 of PMOS transistor 221B is connected to the output terminals A 3 of logic NAND gate 221A, and source S 3, which is connected to, deposits
The operating voltage VDD of array 130 is stored up, drain D 3 is connected to the distal end YIO_far of inputoutput data signal wire YIO.
Second amplification feedback circuit 222 includes the second phase inverter 222A, logic nor gate 222B and NMOS transistor 222C,
Wherein, the second phase inverter 222A is connected to amplification enable signal SenseEn；Logic nor gate 222B tools there are two input terminal B1 and
B2 is connected to the output terminal E of the distal end YIO_far and the second phase inverter 222A of inputoutput data signal wire YIO；NMOS
The grid G 4 of transistor 222C is connected to the output terminal B3 of logic nor gate 222B, and source S 4 is grounded, and drain D 4 is connected to input
The distal end YIO_far of outputting data signals line YIO.
When amplification enable signal SenseEn is high level, the distal end YIO_far of inputoutput data signal wire YIO is exported
During high level, logic NAND gate 221A output low levels, PMOS transistor 221B conductings, inputoutput data signal wire YIO's
Distal end YIO_far is quickly pulled up operating voltage VDD.
When amplification enable signal SenseEn is high level, the distal end YIO_far of inputoutput data signal wire YIO is exported
During low level, the second phase inverter 222A output low levels, logic nor gate 222B exports high level, and NMOS transistor 222C is led
Logical, the distal end YIO_far of inputoutput data signal wire YIO is pulled down to rapidly ground voltage.
That is, when amplifying enable signal SenseEn output high level, the second driving unit 220 is enabled, from defeated
Enter the distal end YIO_far driving storage arrays 130 of outputting data signals line YIO, accelerate write operation.
The memory that above example provides includes the first driving unit and the second driving unit, respectively from input and output number
According to the proximally and distally driving storage array of signal wire, to accelerate the write operation of memory, improve the tCCD of memory.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (12)
1. a kind of driving circuit of memory, which is characterized in that including：
First driving unit is connected to the proximal end of inputoutput data signal wire, for from the inputoutput data signal wire
Proximal end driving memory；And
Second driving unit is connected to the distal end of the inputoutput data signal wire, for believing from the inputoutput data
The distal end of number line drives the memory.
2. driving circuit according to claim 1, which is characterized in that the inputoutput data signal wire includes：
First inputoutput data signal wire is used for transmission the first inputoutput data signal；And
Second inputoutput data signal wire is used for transmission the second inputoutput data signal, wherein, first input and output
Data-signal and the second inputoutput data signal are Difference signal pair；
Second driving unit includes：
Sense amplifier is connected to the distal end of the first inputoutput data signal wire and second inputoutput data letter
The distal end of number line, for respectively amplifying the first inputoutput data signal and the second inputoutput data signal；
And
Feedback enhancing circuit is connected to the output terminal of the sense amplifier, for according to amplified first input and output number
It is believed that number the distal end of the first inputoutput data signal wire is drawn high to output supply voltage or is pulled low to ground voltage, with
And for the distal end of the second inputoutput data signal wire to be drawn high according to amplified second inputoutput data signal
To supply voltage or ground voltage is pulled low to, to drive the memory.
3. driving circuit according to claim 2, which is characterized in that second driving unit further includes prewired circuit,
It is connected between the sense amplifier and the feedback enhancing circuit, for making the sense amplifier before work in flat
Weighing apparatus state.
4. driving circuit according to claim 2, which is characterized in that second driving unit further includes reset-set lock
Storage is connected between the sense amplifier and the feedback enhancing circuit, for latching amplified first input and output
Data-signal and amplified second inputoutput data signal.
5. driving circuit according to claim 4, which is characterized in that the feedback enhancing circuit includes：
First feedback enhancing sub-circuit, is connected to the reset-set latch and the first inputoutput data signal wire
Between distal end, the distal end of the first inputoutput data signal wire is drawn for the output according to the reset-set latch
Up to supply voltage or it is pulled low to ground voltage；And
Second feedback enhancing sub-circuit, is connected to the reset-set latch and the second inputoutput data signal wire
Between distal end, the distal end of the second inputoutput data signal wire is drawn for the output according to the reset-set latch
Up to supply voltage or it is pulled low to ground voltage.
6. driving circuit according to claim 2, which is characterized in that the sense amplifier amplifies including cross-couplings
Device is connected to the distal end of the first inputoutput data signal wire and the distal end of the second inputoutput data signal wire,
For respectively by the first inputoutput data signal and the second inputoutput data signal cross coupling amplification.
7. driving circuit according to claim 6, which is characterized in that the sense amplifier further includes：
The first transistor, the grid of the first transistor are connected to the distal end of the first inputoutput data signal wire, institute
The source electrode for stating the first transistor is connected to the cross coupled amplifier；And
Second transistor, the grid of the second transistor are connected to the distal end of the second inputoutput data signal wire, institute
The source electrode for stating second transistor is connected to the cross coupled amplifier；
Wherein, the first transistor drain electrode and the drain electrode of the second transistor link together, when the first crystal
When pipe and second transistor conducting, the first transistor, the cross coupled amplifier and the second transistor shape
Into circuit.
8. driving circuit according to claim 7, which is characterized in that the drain electrode of the first transistor passes through the first reverse phase
Device is connected to amplification enable signal, for making the drain electrode input of the drain electrode of the first transistor and the second transistor and institute
State the level signal of amplification enable signal reverse phase.
9. driving circuit according to claim 1, which is characterized in that second driving unit includes：
First amplification feedback circuit is connected to the distal end of the inputoutput data signal wire, in the input and output number
When exporting high level according to the distal end of signal wire, the distal end of the inputoutput data signal wire is drawn high to supply voltage；And
Second amplification feedback circuit is connected to the distal end of the inputoutput data signal wire, in the input and output number
When exporting low level according to the distal end of signal wire, the distal end of the inputoutput data signal wire is pulled low to ground voltage.
10. driving circuit according to claim 9, which is characterized in that the first amplification feedback circuit includes：
Logic NAND gate, there are two input terminals for tool, and the distal end and amplification for being connected to the inputoutput data signal wire make
Can signal and
PMOS transistor, the grid of the PMOS transistor are connected to the output terminal of the logic NAND gate, the PMOS crystal
The source electrode of pipe is connected to supply voltage, and the drain electrode of the PMOS transistor is connected to the remote of the inputoutput data signal wire
End.
11. driving circuit according to claim 10, which is characterized in that the second amplification feedback circuit includes：
Second phase inverter is connected to the amplification enable signal；
Logic nor gate including two input terminals, is connected to the distal end and described of the inputoutput data signal wire
The output terminal of two phase inverters and
NMOS transistor, the grid of the NMOS transistor are connected to the output terminal of the logic nor gate, the NMOS crystal
The source electrode ground connection of pipe, the drain electrode of the NMOS transistor are connected to the distal end of the inputoutput data signal wire.
12. a kind of memory, which is characterized in that including driving circuit described in claim 1.
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| CN201711444707.1A CN108172253A (en) | 2017-12-27 | 2017-12-27 | The driving circuit of memory and apply its memory |
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| CN201711444707.1A CN108172253A (en) | 2017-12-27 | 2017-12-27 | The driving circuit of memory and apply its memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111627474A (en) * | 2020-05-29 | 2020-09-04 | 西安紫光国芯半导体有限公司 | Transmission data bus driving circuit and method, and electronic device |
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| CN107039055A (en) * | 2015-11-25 | 2017-08-11 | 美光科技公司 | Semiconductor device with single-ended main I/O lines |
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