CN108153276A - DCS performance testing devices and method based on SOPC - Google Patents

Abstract

The invention discloses a SOPC-based DCS performance test device and method, and relates to the field of test equipment for power systems. The device includes a CPU module, a CAN interface; and an SOE signal output module connected to the CPU module through the PLB high-speed peripheral interface; and at least one of the following four modules connected to the CPU module through the CAN bus through the CAN interface One module: an analog quantity acquisition module, a digital quantity acquisition module, a key phase acquisition module, and an analog quantity output module, wherein at least one module in the four modules is related to the SOE signal output module interconnected via the backplane. The method includes the steps of data acquisition control, internal bus data exchange and processing; and the steps of providing visualized configuration configuration, data monitoring and analysis, and realizing CAN network driving and data driving. The device covers the main performance index test of DCS, and can be used for channel accuracy test, channel verification, redundancy switching test, channel anti-jitter test and SOE function test for DCS.

Description

SOPC-based DCS performance testing device and method

technical field

The invention relates to performance testing equipment of a power electronic system, in particular to a device and a method for performance testing of a DCS in the power electronics industry.

Background technique

DCS (Distributed Control System) is an important control system of a power plant, which is responsible for the process control task of the generating set. The reliability of DCS directly affects the operating safety of the generating set. Since DCS is a typical power electronic system, its reliability will gradually decline with the increase of the operation time, which will bring safety hazards to the operation of the unit. DCS performance index test includes DCS channel accuracy test, channel verification, redundancy switching test, channel anti-shake test and SOE (Sequence Of Event, time sequence recording) function test, etc.; currently, there is no comprehensive test for DCS performance index Portable instruments and equipment, but it is not only inconvenient to carry, but also it is difficult for multiple devices to achieve data synchronization Acquisition, simulation output and testing can easily cause data errors and distortions, affecting the performance evaluation of DCS.

Contents of the invention

For the above problems, the present invention provides a DCS performance testing device based on SOPC (System-on-a-Programmable-Chip, i.e. System-on-a-Programmable-Chip), which can overcome the above shortcomings and integrate data acquisition, high-frequency Signal output, signal analysis, equipment monitoring and other fields of technology, with high-speed data processing, high-speed bus, high-speed signal acquisition and processing and high-speed SOE signal test functions, so as to realize the performance index test and evaluation of DCS.

A DCS performance testing device based on SOPC, comprising a CPU module, a CAN interface; and an SOE signal output module connected to the CPU module through the PLB high-speed peripheral interface; and connected to the CPU module through the CAN bus through the CAN interface At least one of the following four modules: analog acquisition module, digital acquisition module, key phase acquisition module, analog output module, wherein at least one of the four modules The component is interconnected with the SOE signal output module through the backplane.

Further, the DCS performance testing device further includes a time synchronization unit connected to the CPU module through a serial port, the time synchronization unit includes a GPS signal receiver, and a GPS antenna connected to the GPS signal receiver.

Further, the CPU module includes an SOPC chip, and an on-chip peripheral expansion part connected to the SOPC chip through an OPB (on-chip peripheral bus), and a clock that generates clocks for the SOPC chip and the on-chip peripheral expansion part The on-chip peripheral expansion part includes an acquisition control logic unit, a control register, a data cache RAM block and a time counter.

Further, the analog acquisition module is used to acquire 1-5V voltage or 4-20MA DC signal, including sequentially connected V/I converters, anti-aliasing filters, operational amplifiers, A/D converters and digital An isolation unit, wherein the digital isolation unit is connected to the CPU module through the CAN bus.

Further, the digital quantity acquisition module is mainly used to acquire on-site digital switching quantity signals, including a high-speed optocoupler isolation unit, an amplification and shaping circuit, a pulse counting unit and a data latch circuit connected in sequence, wherein the data latch circuit passes through The CAN bus is connected to the CPU module.

Further, the key-phase acquisition module is mainly used to acquire the rotational speed signal, including a high-frequency filter, a level comparison unit, a level change unit, a high-speed optocoupler isolation unit and a data latch circuit connected in sequence, wherein the data The latch circuit is connected to the CPU module through the CAN bus.

Further, the analog output module is used to simulate and output 1-5V voltage or 4-20MA DC signal, including digital isolation units, D/A converters, amplification and shaping circuits and I/V converters connected in sequence, wherein The digital isolation unit is connected with the aforementioned CPU module through the CAN bus.

Further, the SOE signal output module is used to simulate and output high-speed switching signal. It includes a digital isolation circuit connected to the CPU module through a PLB high-speed data exchange bus, and an amplification and shaping circuit and a level change unit sequentially connected to the digital isolation circuit.

Further, the CPU module is connected with the host computer through the USB extension port to realize data exchange, and connected with the peripheral devices through the VGA and RS232 interfaces to realize the human-machine data transmission with the user.

The present invention also provides a DCS performance testing method based on SOPC, comprising: the steps of data acquisition control, internal bus data exchange and processing, and the steps of data acquisition control, internal bus data exchange and processing are realized based on hardware programming language and the steps of providing visual configuration configuration, data monitoring and analysis, and realizing CAN network driving and data driving, the steps of providing visual configuration configuration, data monitoring and analysis functions, and realizing CAN network driving and data driving are Based on the embedded operating system, using the interface of the MiniGUI graphical environment, it is designed with C language.

The invention can complete the test of the DCS performance index and provide guarantee for the safe and stable operation of the generating set. The device covers the main performance index test of DCS, and can be used for channel accuracy test, channel verification, redundancy switching test, channel anti-jitter test and SOE function test for DCS. Compared with the existing performance test device, this The DCS performance testing device proposed by the invention has the following advantages: ① It has the functions of high-speed acquisition of analog signals, high-speed acquisition of digital signals, key-phase signal acquisition, high-frequency signal simulation output, and signal analysis and processing functions. ② Synchronous sampling and simulation output of various types of signals can be realized through a unified clock pulse, which facilitates data analysis and processing in one coordinate system. ③Highly integrated single-chip processing greatly improves the stability and anti-interference ability of the device, the system is flexible, and the functions can be upgraded and expanded. ④Compared with the traditional embedded design scheme, the software-hardware collaborative design scheme using SOPC not only saves the cost, but also reduces the area of the circuit board, thereby reducing the volume of the device and improving portability.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Fig. 1 is a structural representation of the present invention;

Fig. 2 is the structural representation of CPU module;

Fig. 3 is the structural representation of analog quantity acquisition module;

Fig. 4 is the structural representation of digital quantity acquisition module;

Fig. 5 is the structural representation of key phase acquisition module;

Fig. 6 is a structural schematic diagram of an analog output module;

Fig. 7 is the structural representation of SOE signal output module;

Fig. 8 is the main content of DCS performance test method;

FIG. 9 is a flow chart of the Linux operating system data packet receiving function.

Detailed ways

As shown in Figure 1, the DCS performance testing device includes a CPU module 1 and a CAN interface, and an SOE signal output module 6 connected to the CPU module 1 through the PLB high-speed peripheral interface, and a SOE signal output module 6 connected to the CPU module 1 through the CAN bus. One or more (can be equal to four) of the following four modules: analog quantity acquisition module 2, digital quantity acquisition module 3, key phase acquisition module 4, analog quantity output module 5, wherein, One or more of the four modules are interconnected with the SOE signal output module 6 through the backplane. During work, CPU module 1 realizes with one or more modules in four modules (namely analog quantity acquisition module 2, and/or digital quantity acquisition module 3, and/or key phase acquisition module 3) through standard CAN bus The data transmission of the module 4 and/or the analog output module 5) is realized through the PLB high-speed peripheral interface and the SOE signal output module. The DCS performance testing device also includes a GPS signal receiver 71 of the time synchronization unit 7 connected to the CPU module 1 through a serial port, and the time synchronization unit 7 also includes a GPS antenna 72 connected with the GPS signal receiver 71 . When working, the GPS signal receiver 71 sends the time synchronization signal received by the GPS antenna 72 to the CPU module 1 through the serial port, and also provides a unified 1PPS (pulse per second, 1 time per second) signal to the CPU module 1 at the same time, To generate synchronous sampling pulses to realize synchronous sampling and output of signals. After completing data collection and analysis, CPU module 1 connects peripherals such as LCM (touch screen) and keyboard through VGA and RS232 interfaces to realize human-machine data transmission with the user, and can exchange data with the host computer through the USB expansion port. The upper computer performs data processing, drawing curves, building models, etc., and conducts comprehensive test and evaluation for DCS performance.

As shown in Figure 2, CPU module 1 includes an SOPC chip 11 and an on-chip peripheral expansion part connected to the SOPC chip by OPB, and a clock 16 for generating clocks for the SOPC chip 11 and the on-chip peripheral expansion part. The SOPC chip is preferably Xilinx Virtex 2P40. Since the DCSSOE channel function test and the controller clock synchronization test require a relatively high signal output rate, the PLB (processor local bus) high-speed peripheral interface is used to connect with the SOE signal output module to realize data transmission, and the signal resolution can be achieved. Reach more than 0.05ms.

The on-chip peripheral expansion part completes data transmission through OPB, including acquisition control logic unit 12, control register 13, data cache RAM block 14, and time counter 15. The on-chip peripheral expansion part is connected to the analog quantity acquisition module 2, the digital quantity acquisition module 3, the key phase acquisition module 4, and the analog quantity output module 5 through the standard CAN bus to realize data transmission. The fundamental wave and the amplitude and phase of each harmonic are comprehensively analyzed and processed by the SOPC chip in the form of a modular program, and stored in the data cache RAM block. The on-chip peripheral expansion part also realizes data transmission with the peripherals such as LCM and keyboard and the host computer through the on-chip peripheral interfaces RS232, VGA, USB, etc.

The clock for sampling and data analysis of the CPU module is uniformly generated by the clock 16 .

As shown in Figure 3, the analog quantity acquisition module 2 is used for collecting 1-5V voltage or 4-20MA direct current signal, comprises the V/I converter 21, anti-aliasing filter 22, operational amplifier 23, A/ The D converter 24 and the digital isolation unit 25, wherein the digital isolation unit 25 is connected to the CPU module 1 through the CAN bus. When working, the current signal directly enters the anti-aliasing filter 22 for filtering, and the voltage signal is first converted into a DC signal by the V/I converter 21 and then enters the anti-aliasing filter 22 for filtering, and then connected to the non-inverting input terminal of the operational amplifier 23, The output of the operational amplifier 23 is connected to the A/D converter 24. The A/D converter can adopt the AD7705 chip, which has signal conditioning, 1mw power consumption, and dual-channel 16-bit precision, which can ensure the accuracy of analog quantity acquisition. After the digital signal converted by A/D is isolated and processed by the digital isolation unit 25, it is transmitted to the CPU module through the CAN bus.

As shown in Figure 4, the digital quantity acquisition module 3 is mainly used to acquire the on-site digital switching quantity signal, including a high-speed optocoupler isolation unit 31, an amplification and shaping circuit 32, a pulse counting unit 33 and a data latch circuit 34 connected in sequence, wherein The data latch circuit 34 is connected to the CPU module 1 through the CAN bus. When working, after the digital signal passes through the high-speed optocoupler isolation unit 31, the signal is converted into a clear and identifiable digital signal through the amplification and shaping circuit 32, and then counted and calculated by the pulse counting unit 33, and the data is locked by the data latch circuit 34 stored, and transmitted to the CPU module 1 through the standard CAN interface for data processing.

As shown in Figure 5, the key phase acquisition module 4 is mainly used to collect the rotational speed signal, including a high-frequency filter 41, a level comparison unit 42, a level change unit 43, a high-speed optocoupler isolation unit 44 and a data lock connected in sequence. storage circuit 45, wherein the data latch circuit 45 is connected to the CPU module 1 through the CAN bus. The high-frequency filter 41 is preferably an RC filter. During work, after the key-phase signal is filtered by the high-frequency filter 41, it is sent to the level comparison unit 42 for comparison with the comparison level set up to obtain a pulse square wave signal, and then the square wave is electrically controlled by the level change unit 43. The processed square wave signal passes through the high-speed optocoupler isolation unit 44 and the data latch circuit 45, and then is transmitted to the CPU module 1 through the standard CAN interface for data processing.

As shown in Figure 6, the analog output module 5 is used to emulate output 1-5V voltage or 4-20MA DC signal, including digital isolation unit 51, D/A converter 52, amplification and shaping circuit 53 and I/O converter connected in sequence. The V converter 54, wherein the digital isolation unit 51 is connected with the aforementioned CPU module 1 through the CAN bus. The A/D converter 52 preferably adopts the DAC8775 chip. The DAC8775 has a small package ratio, a low signal-to-noise ratio, and 16-bit channel precision, which can ensure the accuracy of analog simulation output. During work, the analog output module 5 receives the digital signal sent by the CPU module 1 through the standard CAN bus, and sends it to the D/A converter 52 after passing through the digital isolation unit 51, and the analog signal converted by the D/A converter 52 After the quantitative signal passes through the amplification and shaping circuit 53, one path is converted into a standard 4-20MA DC signal output, and the other path is converted into a standard 1-5V voltage signal output through the I/V converter 54.

As shown in FIG. 7, the SOE signal output module 6 is used to simulate and output high-speed switching signal. It includes a digital isolation circuit 61 connected to the CPU module 1 through a PLB high-speed data exchange bus, and an amplification and shaping circuit 62 and a level change unit 63 sequentially connected to the digital isolation circuit 61 . The 5V TTL signal generated by the CPU module 1 is transmitted to the digital isolation circuit 61 through the PLB high-speed data exchange bus, and the isolated signal is connected to the amplification and shaping circuit 62 to convert the signal into a clear and identifiable signal, and then pass through the level change unit The adjustable resistor in 63 changes the level of the signal to adapt to the requirements of different DCS on the SOE signal.

As shown in Figure 8, the DCS performance test method comprises: the steps of data acquisition control, internal bus data exchange and processing described in the steps of data acquisition control, internal bus data exchange and processing are realized based on hardware programming language; and providing visual The steps of configuration configuration, data monitoring and analysis, and realization of CAN network drive and data drive, the steps of providing visual configuration configuration, data monitoring and analysis functions, and realization of CAN network drive and data drive are realized based on an embedded operating system For example, the Linux system uses the interface of the MiniGUI graphical environment and uses C language to design.

The steps specifically include the following:

Data acquisition, control and processing: establish shared memory, manage system configuration information, real-time data, provide continuous and independent online data acquisition control, signal processing, internal bus data exchange, and perform data processing through device reading and writing and kernel device driver configuration exchange.

Operation process and resource configuration: process management, inter-process communication, memory management, implementation of file system, provision of I/O interface and management of other resources, external storage adopts DDR storage module.

Data-driven: In the system kernel space, map the cached storage space to a character device, respond to device interruptions, establish a data exchange buffer storage, provide the interface between the underlying program and the operating system, and complete the data exchange between the user space and the kernel space.

Data communication interface configuration: realize the data exchange between this system and other systems, and the system provides serial port, USB, VGA and other ways to transmit data.

System configuration configuration and monitoring analysis: Based on the MiniGUI graphical environment, configure visualized system parameters (including unit, channel, measuring point information configuration, etc.), and display various real-time data monitoring charts and historical trend analysis charts on the host computer.

CAN network driver: run in the system kernel space, complete the data exchange between user space and kernel space; and realize CPU module and analog quantity acquisition module, digital quantity acquisition module, key phase acquisition module, analog quantity through CAN network Data transmission of the output module.

Fig. 9 is a flow chart of the Linux operating system data packet receiving function, which is the core link of the data drive. The data packet reception in the Linux system is realized through interrupts. The controller will generate an interrupt signal when there is a data packet to be received, and its interrupt processing subroutine completes the data packet reception by calling the data packet receiving function. Different from the data sending buffer, the data receiving buffer in the controller is a ring structure. The data packet contains three parts: the byte-long header, data and CRC check sequence. Each byte of the 4-byte long header indicates whether There are low and high bytes of data, data status, data length. When the first byte of the header is 01H, it means that there is data to be read. At this time, the function is called to apply for the data buffer to store the received data, and according to the information contained in the header of the data packet, it is checked whether the data has been read and correct. When the header of the data packet read is 00H, it indicates that the data has been read, complete the reading of the data packet and wait for the next reading.

In the description of the embodiments of the present invention, unless otherwise specified and limited, the terms "connection" and "connection" should be understood in a broad sense, such as: it can be an electrical connection or a mechanical connection; it can be a detachable connection , can also be fixedly connected, or connected as a whole; can be directly connected, can also be connected through an intermediate interface, or communicate within the two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

Claims (10)

1. A DCS performance testing device based on SOPC, comprising a CPU module (1) and a CAN interface; and An SOE signal output module (6) connected to the CPU module (1) through a PLB high-speed peripheral interface; and At least one of the following four modules connected to the CPU module through the CAN interface via the CAN bus: analog quantity acquisition module (2), digital quantity acquisition module (3), key phase acquisition module ( 4), analog output module (5); Wherein, at least one of the four modules is interconnected with the SOE signal output module (6) through a bottom plate. 2. the performance testing device of DCS as claimed in claim 1, is characterized in that, described DCS performance testing device also comprises the timing unit (7) that is connected with described CPU module (1) by serial port, described pair Time unit (7) comprises GPS signal receiver (71), and the GPS antenna (72) that is connected with GPS signal receiver (71), and described GPS signal receiver (71) communicates with described CPU module ( 1) connect. 3. The DCS performance testing device according to claim 1 or 2, characterized in that the CPU module (1) includes an SOPC chip (11), and an on-chip chip connected to the SOPC chip (11) through OPB Peripheral expansion part, and a clock (16) that generates clocks for the SOPC chip and the on-chip peripheral expansion part, the on-chip peripheral expansion part includes an acquisition control logic unit (12), a control register (13), and a data buffer RAM block (14) and time counter (15). 4. The DCS performance testing device according to claim 1 or 2, wherein the analog acquisition module (2) is used to collect 1~5V voltage or 4~20MA DC signal, including sequentially connected V/ I converter (21), anti-aliasing filter (22), operational amplifier (23), A/D converter (24) and digital isolation unit (25), wherein the digital isolation unit (25) is connected by CAN bus The CPU module (1). 5. The DCS performance test device according to claim 1 or 2, characterized in that, the digital quantity acquisition module (3) includes a high-speed optocoupler isolation unit (31), an amplification and shaping circuit (32), A pulse counting unit (33) and a data latch circuit (34), wherein the data latch circuit (34) is connected to the CPU module (1) through a CAN bus. 6. The DCS performance testing device according to claim 1 or 2, characterized in that, the key-phase acquisition module (4) includes a high-frequency filter (41), a level comparison unit (42), A level change unit (43), a high-speed optocoupler isolation unit (44) and a data latch circuit (45), wherein the data latch circuit (45) is connected to the CPU module (1) through a CAN bus. 7. The DCS performance test device according to claim 1 or 2, characterized in that the analog output module (5) is used to simulate and output 1-5V voltage or 4-20MA DC signal, including sequentially connected digital An isolation unit (51), a D/A converter (52), an amplification and shaping circuit (53) and an I/V converter (54), wherein the digital isolation unit (51) communicates with the CPU module ( 1) connected. 8. The DCS performance test device according to claim 1 or 2, characterized in that, the SOE signal output module (6) is used to simulate and output high-speed switching signals, including communicating with the CPU through the PLB high-speed data exchange bus A digital isolation circuit (61) connected to the module (1), and an amplification and shaping circuit (62) and a level change unit (63) sequentially connected to the digital isolation circuit (61). 9. The DCS performance testing device according to claim 1 or 2, characterized in that, the CPU module (1) is connected to the host computer through a USB extension port, and is connected to peripherals through a VGA and RS232 interface. 10. A performance testing method of DCS based on SOPC, comprising: Steps of data acquisition control, internal bus data exchange and processing; And visualized configuration configuration, data monitoring and analysis, and the steps to realize CAN network drive and data drive; Wherein, the steps of data acquisition control, internal bus data exchange and processing are realized based on hardware programming language; the steps of providing visual configuration configuration, data monitoring and analysis functions and realizing CAN network drive and data drive are based on implemented by an embedded operating system.