CN108152719B - Scan cell for dual port memory applications - Google Patents

Abstract

Various embodiments described herein relate to a scanning unit. The scan cell may include an input stage having a plurality of multiplexers and latches arranged to receive a scan input signal, a first address signal, and a second address signal, and to provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a select enable signal. The scan cell may comprise an output stage having a plurality of latches arranged to receive the scan-in signal, the first address signal or the second address signal from the input stage and to provide the scan-in signal, the first address signal or the second address signal as a scan-out signal based on a second clock signal and a third clock signal.

Description

Scan cell for dual port memory applications

Technical Field

The present disclosure relates to the field of electronics, and in particular, to a scan cell for dual port memory applications.

Background

This section is intended to provide information relevant to understanding the various techniques described herein. As the title of this section suggests, this is a discussion of related art and it is by no means an indication that it is prior art. In general, the related art may or may not be considered prior art. Accordingly, it should be understood that any statement in this section should be read in this light, and not as any admission as to prior art.

In modern circuit design, chains of scan cells and related structures are used to test Integrated Circuits (ICs) by providing a means for observing the output of flip-flops. In a full scan design, Automatic Test Pattern Generation (ATPG) provides a simpler combinatorial test application. In some current memory macro designs, the embedded scan chain may not be present on the address pins and control pins.

For ATPG overlays on these pins, there are some techniques that can be used at the system-on-chip (SoC) level. One example technique may generate a sequential ATPG pattern based on Random Access Memory (RAM). This technique may have drawbacks in the runtime of the ATPG tool for generating patterns as well as increasing ATPG pattern counts, which may result in increased test time and test cost. Another technique may add the observation scan cells to the drivers of the input pins of the memory macro. Unfortunately, this technique may result in additional hardware cost at the SoC level.

Disclosure of Invention

Drawings

Implementations of various technologies are described herein with reference to the accompanying drawings. It should be understood, however, that the drawings illustrate only various implementations described herein and are not meant to limit embodiments of the various techniques described herein.

Fig. 1 shows a diagram of a dual port memory circuit according to embodiments described herein.

FIG. 2 shows a diagram of a dual pump memory circuit according to embodiments described herein.

FIG. 3 shows a block diagram of an internal scan chain according to embodiments described herein.

4A-4C illustrate various diagrams of timing for implementing a dual pump memory circuit, according to embodiments described herein.

Fig. 5 shows a process flow diagram of a method for implementing a scan cell in a dual port memory according to embodiments described herein.

Detailed Description

Various embodiments described herein are directed to various schemes and techniques for implementing a scan cell in a dual port memory application. For example, various embodiments described herein are directed to circuit schemes and/or techniques for providing full scan in a memory macro with a pseudo-dual port, and the ability to implement full test coverage of shadow logic (shadow logic) coupled to two ports of the pseudo-dual port memory. Static and dynamic failures can be supported by exploiting the actual path inside the memory macro to provide lower hardware cost at the SoC level. In some cases, the schemes and techniques described herein may introduce scan chains on address and control pins of the memory macro to avoid the disadvantages of certain alternative techniques employed in modern designs. A pseudo-dual port (dual pump) memory may have two ports (dual ports) for memory operations controlled by a single clock. Each input in some designs may have latches controlled by an auxiliary clock from an external clock, and a complete scan chain may be added by introducing one or more latches into the circuit.

Various embodiments described herein provide a dual pump scan cell design with unique circuit characteristics that uses innovative scanning techniques for scan viewing. Under a customized timing pulse and data usage model, there is no standard ATPG test solution for scanning that minimizes latch count or actual timing of the match by reusing the actual internal timing pulse. Various schemes and/or techniques described herein address these issues by defining circuits to address ATPG test requirements with minimal design impact and added logic. In addition, embedded scan control registers are added for a simpler user/designer experience.

Thus, various embodiments for implementing a scan cell in a dual port memory application will now be described with reference to FIGS. 1-5.

Fig. 1 shows a diagram of a dual port memory circuit 100 according to embodiments described herein. Memory circuit 100 may be implemented as an Integrated Circuit (IC) using various types of memory, such as Random Access Memory (RAM) and/or any other type of memory, including any type of volatile and non-volatile memory. The memory circuit 100 may be implemented as an IC having a dual rail memory architecture. The memory circuit 100 may be integrated with various types of computing circuitry and/or various related components on a single chip. Alternatively, the memory circuit 100 may be implemented in embedded systems for a variety of electronic and mobile applications.

As shown in FIG. 1, the circuit 100 may include a dual Port memory macro for a first Port (Port _ A) and a second Port (Port _ B). The first port (port _ a) may comprise a multiplexer MA, a first latch L1A and a second latch L2A arranged to receive a first address (Addr _ a) signal, a Signal In (SI) signal and a Scan Enable (SE) signal. The first multiplexer MA may receive a first address (Addr _ a) signal and a Signal Input (SI). The first multiplexer MA may provide a first address (Addr _ a) signal or Signal Input (SI) to the first latch L1A based on the Scan Enable (SE) signal. The first latch L1A may receive and provide a first address (Addr _ A) signal or Signal Input (SI) to the second latch L2A based on a first clock (CLK _ A) signal. In addition, the second latch L1B may receive and provide the first address (Addr _ a) signal or Signal Input (SI) as the Signal Output (SO) based on the first clock (CLK _ a) signal. In some cases, the output signal of the first latch L1A may be used for the first memory row decoder (MRD _ a).

Similarly, the second port (port _ B) may comprise a multiplexer MB, a first latch L1B and a second latch L2B arranged to receive a second address (Addr _ B) signal, a Signal Input (SI) signal and a Scan Enable (SE) signal. The second multiplexer MB may receive a second address (Addr _ B) signal and a Signal Input (SI). The second multiplexer MB may provide a second address (Addr _ B) signal or Signal Input (SI) to the first latch L1B based on the Scan Enable (SE) signal. The first latch L1B may receive and provide a second address (Addr _ B) signal or Signal Input (SI) to the second latch L2B based on a second clock (CLK _ B) signal. Further, the second latch L2B may receive and provide a second address (Addr _ B) signal or Signal Input (SI) as a Signal Output (SO) based on a second clock (CLK _ B) signal. In some cases, the output signal of the first latch L1B may be used for the second memory row decoder (MRD _ B).

In some embodiments, the basic scan cell may include a D flip-flop (DFF) of a scan Multiplexer (MUX). Generally, DFFs are positive edge (posedge) triggered memory devices. Internally, some DFFs may be provided with a ph2D latch (e.g., the latch is open when the clock is low) and a ph 1D latch (e.g., the latch is open when the clock is high). The output Q of the DFF may be used as a Scan Out (SO) signal. As shown in FIG. 1, each port (Port _ A, Port _ B) may be configured as a MUX-DFF scan cell with a Multiplexer (MUX), a ph2D latch, and a ph 1D latch.

With respect to capture and address input in a RAM macro, a simple memory can be described to handle a single traffic per rising edge of the clock. For example, to capture address inputs during scan-based testing, a ph1 latch may be added to the existing data path (MRD _ A, MRD _ B), as shown in fig. 1. The ph2 latch may be a functional latch that holds the address value when the bit cells in the data path are processed (i.e., memory bit cell traffic is initiated when the clock is high). A ph1 latch may be added for DFT _ OC to provide an efficient scan DFF for addressing. In this case, each Port unit (Port _ A, Port _ B) in fig. 1 may be referred to as a RAM address observation unit.

With respect to capture and address input in a dual Port RAM macro, as shown in fig. 1, the dual Port memory (Port _ A, Port _ B) differs in that it has two unique ports capable of performing operations. For scan observation, there are only two scan observation cells (Port _ A, Port _ B) per address Port/clock (CLK _ A, CLK _ B). Thus, each different Port (Port _ A, Port _ B) can be considered as its own independent entity.

Dual port memories may have some drawbacks, such as having double the number of rows/word lines, sense amplifiers, etc., which may result in slower access times and larger areas. Current design techniques may allow traffic to occur outside of a single shared clock (occur off of a single shared clock). However, various embodiments provided herein may utilize two separate asynchronous clocks. To do this, the memory may receive two sets of inputs and the memory should manage and execute one transaction at a time. This can be achieved by the circuit and timing diagram of fig. 2 provided below. In the example of fig. 2, the input clock may generate two internal traffic events by generating two internal GTP clocks. The circuit may select Addr _ a and then Addr _ B for its first operation.

This can be controlled by the mux _ sel signal.

Fig. 2 shows a schematic diagram of a dual pump circuit 200 according to embodiments described herein.

When used in various types of memory applications, the circuit 200 may be implemented as an Integrated Circuit (IC), for example, a scan cell for Random Access Memory (RAM) and/or any other type of memory, including any type of volatile and non-volatile memory. The circuit 200 may be implemented as an IC having a dual rail memory architecture (e.g., a dual port memory architecture). Further, the circuit 200 may be integrated with various types of computing circuitry and/or various related components on a single chip. Alternatively, the circuit 200 may be implemented in an embedded system for various electronic and mobile applications.

As shown in fig. 2, the circuit 200 may include an input stage 202 having a plurality of multiplexers M1, M2, and a latch L1, the input stage 202 arranged to receive a Scan Input (SI) signal, a first address (Addr _ a) signal, and a second address (Addr _ B) signal. The multiplexers M1, M2 and latch L1 may be arranged to provide a Scan Input (SI) signal, a first address (Addr _ a) signal or a second address (Addr _ B) signal based on a Scan Enable (SE) signal, a first clock (ph2B _ clk) signal and a select enable (mux _ sel) signal. The select enable (mux _ sel) signal may include a multiplexer select control signal.

The multiplexers M1, M2 may include a first multiplexer M1 and a second multiplexer M2. The first multiplexer M1 may receive a Scan In (SI) signal and a first address (Addr _ a) signal. The first multiplexer M1 may provide a Scan Input (SI) signal or a first address (Addr _ a) signal to the second multiplexer M2 based on a Scan Enable (SE) signal. The latches L1 may include a first latch L1 that may receive a second address (Addr _ B) signal and provide the second address (Addr _ B) signal to a second multiplexer M2 based on a first clock (ph2B _ clk) signal. In addition, the second multiplexer M2 may receive a Scan In (SI) signal or a first address (Addr _ a) signal from the first multiplexer M1 and a second address (Addr _ B) signal from the first latch L1. The second multiplexer M2 may provide a scan-in (SI) signal, a first address (Addr _ a) signal, or a second address (Addr _ B) signal to the output stage 204 based on the select enable signal. In some embodiments, as shown in fig. 2, first latch L1 may be referred to as a ph2b latch.

The first address (Addr _ a) signal may reference a first Port (Port _ a) memory address from a dual Port memory circuit, device or component, and the second address (Addr _ B) signal may reference a second Port (Port _ B) memory address from the dual Port memory circuit, device or component. The select enable (mux _ sel) signal may include an observation control signal (observation _ control) that may be used to select either the first Port (Port _ a) memory address or the second Port (Port _ B) memory address during a scan capture mode of operation of circuit 200 (e.g., a scan cell). In some embodiments, the Scan Enable (SE) signal may be different from the select enable (mux _ sel) signal.

The circuit 200 may comprise an output stage 204 having a plurality of latches L2, L3 arranged to receive a scan-in (SI) signal, a first address (Addr _ a) signal or a second address (Addr _ B) signal from an input stage 202. The plurality of latches L2, L3 may be arranged to provide a Scan In (SI) signal, a first address (Addr _ a) signal, or a second address (Addr _ B) signal as a Scan Out (SO) signal based on the second clock (ph2ab _ clk) signal and the third clock (ph1_ clk/GTP) signal. As shown in fig. 2, the second latch L2 may be referred to as a ph2ab latch, and the third latch L3 may be referred to as a ph1 latch. Further, the second clock (ph2ab _ clk) signal may be different from the first (ph2b _ clk) clock signal, and the third clock (ph1_ clk/GTP) signal may be different from the first clock (ph2b _ clk) signal and the second clock (ph2ab _ clk) signal. Furthermore, in some cases, the output signal of the second latch L2 may be used for Row Decoding (RD) in memory applications.

The plurality of latches L2, L3 may include a second latch L2 and a third latch L3. The second latch L2 may receive a Scan Input (SI) signal, a first address (Addr _ a) signal, or a second address (Addr _ B) signal from the second multiplexer M2. The second latch L2 may provide a Scan In (SI) signal, a first address (Addr _ a) signal, or a second address (Addr _ B) signal to the third latch L3 based on the second clock (ph2ab _ clk) signal. The third latch L3 may receive a Scan Input (SI) signal, a first address (Addr _ a) signal, or a second address (Addr _ B) signal from the second latch L2. The third latch L3 may provide the Scan In (SI) signal, the first address (Addr _ a) signal, or the second address (Addr _ B) signal as the Scan Out (SO) signal based on the third clock (ph1_ clk/GTP) signal.

Referring to fig. 2, the first latch L1 (i.e., the ph2b latch) may be controlled by a first clock (ph2b _ clk) signal, the second latch L2 (i.e., the ph2ab latch) may be controlled by a second clock (ph2ab _ clk) signal, and the third latch L3 (i.e., the ph1 latch) may be controlled by a third clock (ph1_ clk/GTP) signal. Fig. 2 shows a timing diagram 210 in functional mode with respect to an external clock CLK.

The input clock generates two internal traffic events by generating two internal GTP clocks. Addr _ a is then selected for its operation, followed by Addr _ B. This can be controlled by the mux _ sel signal. To support scan observability, a ph1 latch was added. To save area, a single ph1 latch is added to the circuit to complete scan FF (ph2/ph1 pair). The ph1 latch may capture the last address port processed through the multiplexer. The ph2B clock holds Addr _ B data until the second dual pump operation can be performed. When the ph2 clock is low, the ph2 latch opens and passes the data.

In the task operating mode, the input for the second address (Addr _ B) signal may be selected at the end of a clock cycle. In the test mode of operation, the first clock (ph2b _ clk) signal is shown in timing diagram 210. The select enable (mux _ sel) signal (i.e., the mux control signal) may be generated using the following equation:

mux_sel＝functional&！dftrambyp|(dftrambyp&(SE|DFT_OC))

in some cases, ph2ab _ clk may only have the first pulse if the values of DFT _ OC and DFTRAMBYP are 1. In other modes, ph2ab _ clk may have double pulses as shown in timing diagram 210, which may be similar to the functional mode of operation. DFT _ OC may be an internally generated signal using a scannable hold flip-flop (D ═ Q). In various embodiments, the testing in functional mode is accurate with respect to the timing of the manner in which the circuit is used.

FIG. 3 shows a block diagram of an internal scan chain 300 according to embodiments described herein. In some embodiments, the internal scan chain 300 refers to an architecture diagram that may be used to generate the DFT _ OC signal.

As shown in FIG. 3, the internal scan chain 300 may include a series of control chains of D flip-flops A [0], A [1],. A [10], and then the following update _ control flip-flop DFT _ OC. Some of the advantages of the internally generated DFT _ OC signal are obtained by adding a scannable hold flip-flop DFT _ OC at the end of the internal (control) scan chain 300 in a memory application (rather than through an external pin). For example, full scan control of the DFT _ OC signal from the ATPG tool can be achieved without using external pins. In another example, the scan value of DFT _ OC may be maintained during scan capture, which allows for high-speed transfer testing (at-speed transfer testing) to be performed without timing conflicts between the DFT _ OC signal and the dual pump clock, which may allow for no tradeoff between test coverage and static or dynamic fault testing. Furthermore, full coverage of the address signals Addr _ a and Addr _ B and matching timing of the two ports can be achieved, area reduction with only one L3 latch (i.e., ph1 latch) can be achieved, and no additional pins are required for user selection input during scan capture.

The DFT _ OC flip-flop may be referred to as an oberve _ control flip-flop. During scan load/unload, the value of the test that selects Addr _ a or Addr _ B is loaded. This value is maintained during the scan capture sequence by assigning D to Q. Thus, in some cases, the following equation may be applied:

mux_sel＝functional&！dftrambyp|(dftrambyp&(SE|observe_control))

ph1_clk＝GTP&(DFTRAMBYP？(SE|(obs_controlopl_enable：op2_enable))：1’b1)

observe_control＝scanable hold flop(D＝Q)

4A-4C illustrate various diagrams of timing for implementing a dual pump memory circuit, according to embodiments described herein.

In particular, FIG. 4A illustrates a timing diagram 400A for scan shifting to test the loading/unloading of the circuit 200 in FIG. 2. In fig. 4A, a scan shift sequence for SI is shown, where the assert _ control is set to logic 1 (1). Note that the Scan Out (SO) path is double pumped through the ph1 latch. This issue is not considered because the output of the ph2ab latch is stable for both pulses. Furthermore, during scan shift, timing and other functional behaviors are not matched.

FIG. 4B shows a timing diagram 400B of scan capture of Addr _ A with the circuit 200 of FIG. 2. In fig. 4B, the scan capture of Addr _ a is shown as indicated by the observe _ control signal, which is set to logic 1 (1). Note that Addr _ a is transferred when SE goes low as indicated by logic 1 (1). Further, ph1_ clk may then capture the observed value into the scan latch, as shown in fig. 4B with the second pump number 2. When the assert control is set to logic 1(1) during the functional capture clock, the second ph1 clk pulse is inhibited.

FIG. 4C shows a timing diagram 400C for scan capture of Addr _ B with the circuit 200 in FIG. 2. In fig. 4C, the scan capture of Addr _ B is shown as indicated by the observe _ control signal, which is set to logic zero (1). Note that ph2B _ clk goes low after the last scan shift to allow Addr _ B to propagate. Note that SE becomes low, allowing mux _ sel to follow the assert _ control value as a low level. Note that only the second ph1_ clk pulse toggles, and the first ph1_ clk pulse is suppressed by the low value of assert _ control.

In various embodiments, the schemes and/or techniques described herein provide for scanning observation in dual pump memory applications. For example, the circuits described herein may use only one ph1 latch to save area. The circuitry described herein may override mux _ sel to select the SI path during scan shift (during loading/unloading of test vectors) by the SE (scan enable) signal. The circuitry described herein may use the assert _ control signal to select either Addr _ a or Addr _ B during scan capture. The circuits described herein may be controlled by flip-flops added to the internal scan chain, as shown in FIG. 3. The circuits described herein may use internal control flip-flops that may be set by the ATPG tool to select a desired address path during a scan capture cycle (where a loaded test vector is executed). The circuits described herein may use embedded flip-flops that are transparent to the user/designer. The circuits described herein may use tools that may be utilized as needed to obtain test coverage. The circuits described herein may use retention flip-flops whose timing is excluded from design considerations. The circuitry described herein may use a ph1 latch clock controlled by the assert _ control signal during scan capture. If Addr _ B is observed, only the second pulse of ph1 is transmitted. If Addr _ A is observed, the clock is only the first ph1 pulse. This may result in testing each Addr _ a/B path with a ph2 latch matching the functional timing requirements-for example, the hold timing for each port may be correctly tested.

In various implementations, the schemes and techniques described herein utilize latching of address signals. However, it will be understood by those skilled in the art that the various schemes and techniques described herein may also be extended to non-address signals.

Fig. 5 illustrates a process flow diagram of a method 500 for implementing a scan cell in a dual port memory according to embodiments described herein.

It should be appreciated that even though the method 500 may indicate a particular order of execution of the operations, in some cases, various particular portions of the operations may be executed in a different order and on a different system. In some other cases, additional operations and/or steps may be added to method 500 and/or omitted from method 500. Furthermore, the method 500 may be implemented in hardware and/or software. If implemented in hardware, the method 500 may be implemented with various circuit components, as described above with reference to FIGS. 1-4C. If implemented in software, the method 500 may be implemented as a program or software instruction process that may be configured to implement a scan cell in a dual port memory application as described herein. Further, if implemented in software, the various instructions associated with implementing the method 500 may be stored or recorded in various types of memory. For example, a computer, server, or various other types of computing devices having a processor and a memory may be configured to perform method 500.

Referring to fig. 5, a method 500 may be used to implement a scan cell in a dual port memory. In some implementations, the method 500 may provide a first multiplexer to receive a scan input signal, receive a first address signal, and the first multiplexer may provide either the scan input signal or the first address signal based on a scan enable signal. At block 520, method 500 may provide a first latch to receive a second address signal and provide the second address signal based on a first clock signal.

At block 520, method 500 may provide a second multiplexer to receive the scan input signal or the first address signal from the first multiplexer, to receive the second address signal from the first latch, and the second multiplexer may provide the scan input signal, the first address signal, or the second address signal based on a select enable signal. The scan enable signal may be different from the select enable signal. The selection enable signal may include a multiplexer selection control signal.

At block 540, method 500 may provide a second latch to receive the scan-in signal, the first address signal, or the second address signal from the second multiplexer, and the second latch may provide the scan-in signal, the first address signal, or the second address signal based on a second clock signal. The second clock signal may be different from the first clock signal.

At block 550, method 500 may provide a third latch to receive the scan-in signal, the first address signal, or the second address signal from the second latch, and the third latch may provide the scan-in signal, the first address signal, or the second address signal as a scan-out signal based on a third clock signal. The third clock signal may be different from the first clock signal and the second clock signal.

Various embodiments of a scanning unit are described herein. The scan cell may include an input stage having a plurality of multiplexers and latches arranged to receive a scan input signal, a first address signal, and a second address signal, and to provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a select enable signal. The scan cell may comprise an output stage having a plurality of latches arranged to receive the scan-in signal, the first address signal or the second address signal from the input stage and to provide the scan-in signal, the first address signal or the second address signal as a scan-out signal based on a second clock signal and a third clock signal.

Various implementations of integrated circuits are described herein. The integrated circuit may include a first multiplexer that receives a scan input signal, receives a first address signal, and provides either the scan input signal or the first address signal based on a scan enable signal. The integrated circuit may include a first latch that receives a second address signal and provides the second address signal based on a first clock signal. The integrated circuit may include a second multiplexer that receives the scan input signal or the first address signal from the first multiplexer, receives the second address signal from the first latch, and provides the scan input signal, the first address signal, or the second address signal based on a select enable signal. The integrated circuit may include a second latch that receives the scan input signal, the first address signal, or the second address signal from the second multiplexer and provides the scan input signal, the first address signal, or the second address signal based on a second clock signal. The integrated circuit may include a third latch that receives the scan-in signal, the first address signal, or the second address signal from the second latch and provides the scan-in signal, the first address signal, or the second address signal as a scan-out signal based on a third clock signal.

Various implementations of methods are described herein. The method may include providing a first multiplexer to receive a scan input signal, receiving a first address signal, and providing either the scan input signal or the first address signal based on a scan enable signal. The method may include providing a first latch to receive a second address signal and providing the second address signal based on a first clock signal. The method may include providing a second multiplexer to receive the scan input signal or the first address signal from the first multiplexer, receiving the second address signal from the first latch, and providing the scan input signal, the first address signal, or the second address signal based on a select enable signal. The method may include providing a second latch to receive the scan input signal, the first address signal, or the second address signal from the second multiplexer, and providing the scan input signal, the first address signal, or the second address signal based on a second clock signal. The method may include providing a third latch to receive the scan-in signal, the first address signal, or the second address signal from the second latch, and providing the scan-in signal, the first address signal, or the second address signal as a scan-out signal based on a third clock signal.

It should be noted that the claimed subject matter is not limited to the implementations and illustrations provided herein, but includes modified forms of those implementations including portions of the implementations according to the claims and combinations of elements of different implementations. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail as not to unnecessarily obscure details of the embodiments.

It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. Both the first and second elements are elements, respectively, but they are not considered to be the same elements.

The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to be limiting of the disclosure provided herein. As used in the description of the present disclosure and the appended claims provided herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and/or" refers to and includes any and all possible combinations of one or more of the associated listed items. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term "if," depending on the context, may be interpreted to mean "when.. or" at.. or "in response to determining" or "in response to detecting. Similarly, the phrase "if it is determined" or "if [ stated condition or event ] is detected" may be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [ stated condition or event ] or" in response to detecting [ stated condition or event ] ", depending on the context. The terms "upper" and "lower"; "higher" and "lower"; "upward" and "downward"; "lower" and "upper"; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of the various techniques described herein.

While the foregoing is directed to implementations of the various techniques described herein, other and further implementations may be devised in light of the disclosure herein, which may be determined by the claims that follow.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (18)

1. A scanning unit, comprising:

an input stage having a first multiplexer and a second multiplexer arranged in series, the input stage having a first latch coupled to the second multiplexer, wherein the first multiplexer is configured to provide a scan input signal or a first address signal to the second multiplexer based on a scan enable signal, and wherein the second multiplexer is configured to receive a second address signal from the first latch based on a first clock signal and provide the scan input signal, the first address signal, or the second address signal based on a select enable signal; and

an output stage having a second latch and a third latch, wherein the third latch is configured to obtain an output signal from the second latch, wherein the second latch is configured to receive the scan-in signal, the first address signal, or the second address signal from the input stage and to provide the scan-in signal, the first address signal, or the second address signal as the output signal to the third latch based on a second clock signal,

wherein the third latch is configured to provide the scan-in signal, the first address signal, or the second address signal as a scan-out signal based on a third clock signal, an

Wherein at least one of the second clock signal and the third clock signal is a dual pump clock signal.

2. The scan cell of claim 1, wherein the first multiplexer receives the scan input signal, receives the first address signal, and provides either the scan input signal or the first address signal to the second multiplexer based on the scan enable signal.

3. The scan cell of claim 2, wherein the first latch receives the second address signal and provides the second address signal to the second multiplexer based on the first clock signal.

4. The scan cell of claim 3, wherein the second multiplexer receives the scan-in signal or the first address signal from the first multiplexer, receives the second address signal from the first latch, and provides the scan-in signal, the first address signal, or the second address signal to the output stage based on the select enable signal.

5. The scan cell of claim 4, wherein the second latch receives the scan-in signal, the first address signal, or the second address signal from the second multiplexer and provides the scan-in signal, the first address signal, or the second address signal to the third latch based on the second clock signal.

6. The scan cell of claim 5, wherein the third latch receives the scan-in signal, the first address signal, or the second address signal from the second latch and provides the scan-in signal, the first address signal, or the second address signal as the scan-out signal based on the third clock signal.

7. The scan cell of claim 1, wherein the first address signal references a first port memory address from a dual port memory component, and wherein the second address signal references a second port memory address from the dual port memory component.

8. The scan cell of claim 7, wherein the select enable signal comprises an observation control signal used to select the first port memory address or the second port memory address during a scan capture mode of operation of the scan cell.

9. The scan cell of claim 1, wherein the first clock signal is different from the second clock signal.

10. The scan cell of claim 1, wherein the third clock signal is different from the first clock signal.

11. The scan cell of claim 1, wherein the scan enable signal is different from the select enable signal.

12. The scan cell of claim 1, wherein the select enable signal comprises a multiplexer select control signal.

13. An integrated circuit, comprising:

a first multiplexer that receives a scan input signal, receives a first address signal, and provides the scan input signal or the first address signal based on a scan enable signal;

a first latch to receive a second address signal and to provide the second address signal based on a first clock signal;

a second multiplexer that receives the scan input signal or the first address signal from the first multiplexer, receives the second address signal from the first latch, and provides the scan input signal, the first address signal, or the second address signal based on a select enable signal;

a second latch that receives the scan input signal, the first address signal, or the second address signal from the second multiplexer and provides the scan input signal, the first address signal, or the second address signal based on a second clock signal; and

a third latch receiving the scan input signal, the first address signal, or the second address signal from the second latch and providing the scan input signal, the first address signal, or the second address signal as a scan output signal based on a third clock signal,

wherein at least one of the second clock signal and the third clock signal is a dual pump clock signal.

14. The integrated circuit of claim 13, wherein the scan enable signal is different from the select enable signal.

15. The integrated circuit of claim 13, wherein the select enable signal comprises a multiplexer select control signal.

16. A method of implementing a scan cell for a memory, comprising:

providing a first multiplexer to receive a scan input signal, receive a first address signal, and provide either the scan input signal or the first address signal based on a scan enable signal;

providing a first latch to receive a second address signal and provide the second address signal based on a first clock signal;

providing a second multiplexer to receive the scan input signal or the first address signal from the first multiplexer, to receive the second address signal from the first latch, and to provide the scan input signal, the first address signal, or the second address signal based on a select enable signal;

providing a second latch to receive the scan-in signal, the first address signal, or the second address signal from the second multiplexer and to provide the scan-in signal, the first address signal, or the second address signal based on a second clock signal; and

providing a third latch to receive the scan-in signal, the first address signal, or the second address signal from the second latch and to provide the scan-in signal, the first address signal, or the second address signal as a scan-out signal based on a third clock signal,

wherein at least one of the second clock signal and the third clock signal is a dual pump clock signal.

17. The method of claim 16, wherein the second clock signal is different from the first and third clock signals.

18. The method of claim 16, wherein the scan enable signal is different from the select enable signal, and the select enable signal comprises a multiplexer select control signal.

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