CN108122761A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and its forming method, the forming method comprising: providing a base, the base including a substrate and a fin located on the substrate; forming a gate structure; forming a source-drain doped region; forming a precursor spacer on the sidewall of the structure facing the source-drain doping region; forming a dummy sidewall located on the sidewall of the precursor spacer; forming a dielectric layer; performing thinning treatment on the precursor spacer to expose the A part of the sidewall of the gate structure, and the remaining precursor sidewall is used to form a corner sidewall; the dummy sidewall is removed to form a vacuum sidewall between the gate structure and the dielectric layer. The technical side of the invention is beneficial to improving the performance degradation of the on-resistance and on-current performance of the transistor, and is beneficial to improving the performance of the formed semiconductor structure.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently being widely used. Therefore, as the component density and integration of semiconductor devices increase, the size of transistors is also getting smaller and smaller. The problems of short channel effect and gate leakage current in small size make the performance of transistor worse, so it faces a series of difficulties to improve performance by shrinking the physical size of traditional transistors.

Group III-V semiconductor materials (eg, InGaAs) have become a hotspot of current research due to their excellent electron transport properties. In order to solve the difficulty that the physical size of traditional semiconductor devices cannot be further reduced, the prior art proposes a technical solution of using III-V semiconductor materials to form transistor channels, so as to improve the performance of transistors.

However, in the prior art, the semiconductor structure performance of III-V semiconductor materials as channel materials still needs to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its forming method to improve the performance of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

providing a base, the base including a substrate and a fin on the substrate; forming a gate structure on the fin, the gate structure spanning the fin and covering a portion of the fin The surface of the top and part of the sidewall; forming source-drain doped regions in the fins on both sides of the gate structure; forming a precursor sidewall on the sidewall of the gate structure facing the source-drain doped region; forming a Dummy sidewalls of the precursor sidewalls; forming a dielectric layer on the substrate exposed by the gate structure, the precursor spacers, and the dummy spacers, the dielectric layer exposing the gate structure, the The precursor sidewall and the dummy sidewall; the precursor sidewall is thinned to expose part of the sidewall of the gate structure, and the remaining precursor sidewall is used to form a corner sidewall; remove the A dummy spacer, forming a vacuum spacer between the gate structure and the dielectric layer.

Optionally, in the step of forming the precursor sidewall, the material of the precursor sidewall is silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or One or more of boron carbonitride.

Optionally, the step of forming the precursor spacer includes: forming a sidewall material layer on the gate structure and the substrate; removing the spacer material layer on the gate structure and the substrate, forming A precursor spacer located on a sidewall of the gate structure.

Optionally, the step of removing the spacer material layer on the gate structure and the substrate includes: performing a first plasma treatment on the gate structure and the spacer material layer on the substrate; Part of the material treated by plasma is removed in a manner to form the precursor sidewall.

Optionally, after forming the precursor spacer and before forming the dummy spacer, the forming method further includes: performing a second plasma treatment on a part of the precursor spacer far away from the substrate; performing a second plasma treatment on the precursor spacer The step of thinning treatment includes: removing part of the material treated by plasma by wet method.

Optionally, in the step of forming the precursor spacer, the material of the precursor spacer is silicon nitride; one or both of the step of the first plasma treatment and the step of the second plasma treatment The first step includes: plasma treatment with H2 or He plasma.

Optionally, in the step of plasma treatment using _H2 or He plasma, the process parameters include: the process gas pressure is in the range of 2mTorr to 100mTorr, the flow rate of _H2 or He is in the range of 50sccm to 500sccm, and the process temperature is 0°C to the range of 100°C.

Optionally, in the step of forming the precursor sidewall, the material of the precursor sidewall is silicon nitride; Part of the material processed by the body.

Optionally, in the step of forming the vacuum sidewall, along the direction perpendicular to the surface of the substrate, the ratio of the size of the vacuum sidewall to the size of the corner sidewall is in the range of 5:4 to 5:1.

Optionally, in the step of forming the doped source and drain regions, along the extending direction of the fin, the distance between the doped source and drain regions is greater than the size of the gate structure; the step of forming a precursor spacer includes: The precursor spacer is formed on the fin between the source-drain doped region and the gate structure.

Optionally, in the step of forming the dummy sidewall, the material of the dummy sidewall is polysilicon.

Optionally, the step of removing the dummy sidewall includes: removing the dummy sidewall by means of chemical diffusion etching.

Optionally, the step of removing the dummy sidewall by chemical diffusion etching includes: using NH ₃ to remove the dummy sidewall.

Optionally, in the step of providing the substrate, the material of the fin is a III-V semiconductor material.

Optionally, in the step of providing the base, the material of the fins is InGaAs.

Correspondingly, the present invention also provides a semiconductor structure, including:

A base, the base includes a substrate and a fin on the substrate; a dielectric layer on the base; a gate structure on the fin in the dielectric layer, the gate structure spans the The fin and covers the surface of part of the top and part of the side wall of the fin; the source and drain doped regions located in the fins on both sides of the gate structure; located on the side of the gate structure facing the source and drain doped regions corner spacers on the walls; vacuum spacers between the gate structure and the dielectric layer.

Optionally, the material of the corner sidewall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or boron carbonitride kind.

Optionally, along a direction perpendicular to the surface of the substrate, the ratio of the dimension of the vacuum sidewall to the dimension of the corner sidewall is in the range of 5:4 to 5:1.

Optionally, the material of the fin is a III-V semiconductor material.

Optionally, the distance between the source-drain doped region is greater than the size of the gate structure; the corner sidewall is located on the fin between the source-drain doped region and the gate structure .

Compared with the prior art, the technical solution of the present invention has the following advantages:

The technical solution of the present invention forms a corner sidewall on the sidewall of the gate structure facing the source-drain doped region, and the dielectric constant of the material of the corner sidewall is greater than that of a vacuum, so the setting of the corner sidewall The average dielectric constant of the corner sidewall and the vacuum sidewall can be effectively increased, which is not only beneficial to maintain a small fringe capacitance, but also helps to improve the degradation of transistor on-resistance and on-current performance. It is beneficial to improve the performance of the formed semiconductor structure.

Description of drawings

1 to 13 are structural schematic diagrams corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.

Detailed ways

It can be seen from the background art that in the prior art, there is a problem of poor performance in the semiconductor structure in which the Group III-V semiconductor material is used as the channel material. Combining the characteristics of III-V semiconductor materials to analyze the reasons for their poor performance:

The channel formed by III-V semiconductor materials will have more significant quantum confinement effect and sub-band splitting phenomenon. Therefore, with the decrease of the channel length, the semiconductor structure of the III-V group semiconductor material as the channel material is prone to the degradation of the electrical isolation performance of the gate dielectric layer and the increase of the gate tunneling current.

In order to suppress gate leakage, in a semiconductor structure in which group III-V semiconductor materials are used as channel materials, a thicker gate dielectric layer needs to be provided. In order to improve the effect of increasing the thickness of the gate dielectric layer on device performance, a vacuum spacer structure is introduced into the semiconductor structure, that is, air is used to electrically insulate the gate structure and the dielectric layer.

However, due to the small dielectric constant of air (K _vacuum = 1), the setting of the vacuum sidewall will reduce the fringing capacitance (Fringing Capacitance) of the device, but at the same time cause the degradation of the on-resistance and on-current performance of the transistor, affecting Properties of the formed semiconductor structures.

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including:

providing a base, the base including a substrate and a fin on the substrate; forming a gate structure on the fin, the gate structure spanning the fin and covering a portion of the fin The surface of the top and part of the sidewall; forming source-drain doped regions in the fins on both sides of the gate structure; forming a precursor sidewall on the sidewall of the gate structure facing the source-drain doped region; forming a Dummy sidewalls of the precursor sidewalls; forming a dielectric layer on the substrate exposed by the gate structure, the precursor spacers, and the dummy spacers, the dielectric layer exposing the gate structure, the The precursor sidewall and the dummy sidewall; the precursor sidewall is thinned to expose part of the sidewall of the gate structure, and the remaining precursor sidewall is used to form a corner sidewall; remove the A dummy spacer, forming a vacuum spacer between the gate structure and the dielectric layer.

The technical solution of the present invention forms a corner sidewall on the sidewall of the gate structure facing the source-drain doped region, and the dielectric constant of the material of the corner sidewall is greater than that of a vacuum, so the setting of the corner sidewall The average dielectric constant of the corner sidewall and the vacuum sidewall can be effectively increased, which is not only beneficial to maintain a small fringe capacitance, but also helps to improve the degradation of transistor on-resistance and on-current performance. It is beneficial to improve the performance of the formed semiconductor structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1 to FIG. 13 , schematic structural diagrams corresponding to each step of an embodiment of a method for forming a semiconductor structure according to the present invention are shown.

As shown in FIGS. 1 to 3 , a base is provided, and the base includes a substrate 100 and a fin 130 on the substrate 100 .

1 is a schematic diagram of a three-dimensional structure of the substrate, and FIG. 2 is a schematic diagram of a cross-sectional structure along line AA in FIG. 1 ; and FIG. 3 is a schematic diagram of a cross-sectional structure along line BB in FIG. 1 .

The substrate 100 is used to provide a process operation platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate, or a silicon-germanium substrate, a silicon-carbon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or III-V compound substrates, such as gallium nitride substrates or gallium arsenide substrates. The material of the substrate can be selected suitable for process requirements or easily integrated.

The fin portion 130 is used for providing a channel of the FinFET.

In this embodiment, the material of the fin portion 130 is a group III-V semiconductor material. Specifically, the material of the fin portion 130 is InGaAs. In other embodiments of the present invention, the material of the fins may also be other III-V semiconductor materials. Group III-V semiconductor materials are ideal channel materials for transistors due to their high low-field electron mobility, which is beneficial to reducing the channel length of transistors and improving the integration of semiconductor structures.

The steps of forming the substrate 100 and the fins 130 include: providing a substrate 100; forming a fin material layer on the substrate 100; forming a patterned fin mask on the fin material layer layer; using the fin mask layer as a mask to etch the fin material layer to form the fin 130 .

The fin material layer is used for etching to form the fin 130 .

In this embodiment, the material of the fin portion 130 is InGaAs. Therefore, the material of the fin material layer is also InGaAs, which can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

It should be noted that, in this embodiment, the base further includes an oxide layer 110 located between the substrate 100 and the fin 130 . The oxide layer 110 is used to provide a good interface foundation for the fin material layer, so as to improve the quality of the formed fin material layer. Therefore, after providing the substrate 100 and before forming the fin material layer, the forming method further includes: forming an oxide layer on the substrate 100 .

The fin mask layer is used to define the size and position of the fin 130 .

The step of forming the fin mask layer includes: forming a mask material layer on the fin material layer; forming a pattern layer on the mask material layer; using the pattern layer as a mask, etching the The mask material layer is exposed to expose the fin material layer to form the fin mask layer.

The pattern layer is used to pattern the mask material layer to define the size and position of the fins.

In this embodiment, the pattern layer is a patterned photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the pattern layer can also be a mask formed by a multiple patterning mask process, so as to reduce the feature size of the fins and the distance between adjacent fins, and improve the integration of the formed semiconductor structure. Spend. The multiple patterned mask process includes: self-aligned double patterned (Self-aligned Double Patterned, SaDP) process, self-aligned triple patterned (Self-aligned triple patterned) process, or self-aligned quadruple patterned ( Self-aligned Double Double Patterned, SaDDP) process.

Continuing to refer to FIGS. 1 to 3 , a gate structure is formed on the fin 130 , the gate structure straddles the fin 130 and covers part of the top and part of the sidewall of the fin 130 .

In this embodiment, the gate structure is a dummy gate structure 121 for occupying a space position for a subsequently formed metal gate structure. In other embodiments of the present invention, the gate structure may also be a gate structure of a formed semiconductor structure.

In this embodiment, the dummy gate structure 121 may be a stack structure, including a dummy oxide layer on the substrate and a dummy gate on the dummy oxide layer. The material of the dummy gate is polysilicon, and the material of the dummy oxide layer may be silicon oxide and silicon oxynitride.

In other embodiments of the present invention, the material of the dummy gate can also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon. In other embodiments of the present invention, the dummy gate structure can also be a single-layer structure, and the material can be selected from polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or One or more of other materials such as amorphous carbon.

The step of forming the dummy gate structure 121 includes: forming a dummy gate material layer on the substrate; forming a dummy gate mask layer on the dummy gate material layer, using the dummy gate mask layer as a mask, and engraving The dummy gate material layer is etched to form the dummy gate structure 121 .

Continuing to refer to FIG. 1 to FIG. 3 , source and drain doped regions 131 are formed in the fins 130 on both sides of the gate structure.

Specifically, in this embodiment, the gate structure is a dummy gate structure 121 . Therefore, the step of forming the doped source and drain regions 131 includes: forming the doped source and drain regions 131 in the fins 130 on both sides of the dummy gate structure 121 .

In this embodiment, the semiconductor structure is an NMOS transistor, so the doping ions in the source-drain doping region 131 are N-type ions, such as P, As or Sb. In other embodiments of the present invention, the semiconductor structure may also be a PMOS transistor, so the doping ions in the source and drain doping regions are P-type ions, such as B, Ga or In.

In this embodiment, along the extending direction of the fin portion 130, the distance between the source-drain doped region 131 is greater than the size of the dummy gate structure 121, that is, the semiconductor structure has a bottom-exposed source region/ The structure of the drain area (gate-to-source/drain underlap). This structure is beneficial to reduce the fringe capacitance of the drain terminal in the formed semiconductor structure, thereby improving the performance of the formed semiconductor structure. Therefore, part of the fin portion 130 used to form a channel between the source-drain doped region 131 is not covered by the dummy gate structure 121 , that is, the dummy gate structure 121 exposes part of the source-drain doped region 131 between the fins 130 for forming the channel.

The step of forming the source-drain doped region 131 in this embodiment includes: forming the source-drain doped region 131 by ion implantation into the fins 130 on both sides of the dummy gate structure 121 . However, in other embodiments of the present invention, the source-drain doped region may also be formed in the fin by means of epitaxial growth.

Referring to FIG. 4 to FIG. 7 , a precursor spacer 144 is formed on the sidewall of the gate structure facing the source-drain doped region 131 .

4 and 6 are schematic cross-sectional structure diagrams corresponding to FIG. 2 ; FIG. 5 and FIG. 7 are schematic cross-sectional structural diagrams corresponding to FIG. 3 .

In this embodiment, the gate structure is a dummy gate structure 121 . Therefore, the step of forming the precursor spacer 144 includes: forming the precursor spacer 144 on the sidewall of the dummy gate structure 121 facing the source-drain doped region 131 .

The precursor spacer 144 is used to occupy space for the formation of subsequent vacuum sidewalls, and is also used to etch to form corner sidewalls. In addition, in this embodiment, the gate structure is a dummy gate structure 121 , so the precursor spacer 144 is also used to define the size and position of the subsequently formed gate structure.

In this embodiment, the distance between the source-drain doped region 131 is greater than the size of the gate structure. Therefore, the step of forming the precursor spacer 144 includes: forming the precursor spacer 144 on the fin portion 130 between the source-drain doped region 131 and the gate structure.

The precursor spacer 144 is made of silicon nitride. In other embodiments of the present invention, the material of the precursor sidewall can also be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or boron carbonitride various

The step of forming the precursor spacer 144 includes: forming a sidewall material layer 143 on the gate structure and the substrate; The precursor spacer 144 of the sidewall of the gate structure.

In this embodiment, the step of forming the precursor spacer 144 includes: as shown in FIG. 4 , forming a sidewall material layer 143 on the dummy gate structure 121 and the substrate; as shown in FIG. 5 , removing the The spacer material layer on the dummy gate structure 121 and the substrate forms a precursor spacer 144 on the sidewall of the dummy gate structure 121 .

The step of removing the spacer material layer 143 on the gate structure and the substrate includes: performing a first plasma treatment 210 on the gate structure and the spacer material layer 143 on the substrate; Part of the material after the first plasma treatment 210 is removed in a manner to form the precursor spacer 144 .

Specifically, the step of removing the sidewall material layer 143 on the dummy gate structure 121 and on the substrate includes: performing a first plasma treatment 210 on the dummy gate structure 121 and the sidewall material layer 143 on the substrate ; Removing part of the material treated by the first plasma by wet method to form the precursor spacer 144 .

Wherein, in this embodiment, the material of the precursor spacer is silicon nitride. Therefore, in the step of the first plasma treatment 210, H2 _or He plasma is used for ion plasma treatment, and the process parameters include: the process gas pressure is in the range of 2mTorr to 100mTorr, and the flow rate of _H2 or He gas is in the range of 50sccm to 500sccm The flow rate of Ar gas is in the range of 0sccm to 200sccm, and the process temperature is in the range of 0°C to 100°C; the step of removing part of the plasma-treated material by wet etching includes: using hydrofluoric acid to remove the plasma-treated Part of the material processed by body, wherein the hydrofluoric acid is dilute hydrofluoric acid, that is, the concentration of hydrofluoric acid is in the range of 1/2000 to 1/100 by volume percentage.

The combination of plasma treatment and wet etching has a higher etching selectivity for the sidewall material layer 143, so it can effectively reduce the impact of the process steps of forming the precursor sidewall 144 on the substrate. The influence of other semiconductor structures is beneficial to improve the yield rate and the performance of the formed semiconductor structure.

Referring to FIG. 8 and FIG. 9 together, a dummy spacer 145 located on a sidewall of the precursor spacer 144 is formed.

8 is a schematic cross-sectional structure corresponding to FIG. 6 , and FIG. 9 is a schematic cross-sectional structure corresponding to FIG. 7 .

The dummy sidewalls 145 are used to occupy space for subsequent formation of vacuum sidewalls.

Specifically, in this embodiment, the material of the dummy sidewall 145 is polysilicon. The step of forming the dummy spacer 145 includes: forming a dummy spacer material layer on the surface of the substrate, the dummy gate structure 121 (as shown in FIG. 6 ) and the precursor spacer 144; removing the substrate, The dummy gate structure 121 and the dummy spacer material layer on the precursor spacer 144 , and the remaining dummy spacer material layer on the sidewall of the precursor spacer 144 are used to form the dummy spacer 145 .

It should be noted that, as shown in FIG. 7 , after forming the precursor spacer 144 and before forming the dummy spacer 145 , the forming method further includes: performing a second Plasma treatment 220 .

The second plasma treatment 220 is used to provide a process basis for the subsequent formation of corner sidewalls, thereby reducing the impact of the formation of the corner sidewalls on other semiconductor structures on the substrate.

Specifically, in the step of the second plasma treatment 220, H ₂ or He plasma is used for ion plasma treatment, and the process parameters include: the process gas pressure is in the range of 2 mTorr to 100 mTorr, and the H ₂ or He gas flow rate is in the range of 50 sccm to 100 mTorr. In the range of 500sccm, the Ar gas flow rate is in the range of 0sccm to 200sccm, and the process temperature is in the range of 0°C to 100°C.

It should be noted that, in this embodiment, the steps of the first plasma treatment 210 and the second plasma treatment 220 are both processed in the same manner. This approach is only an example, and in other embodiments of the present invention, the first plasma treatment step and the second plasma treatment step are also treated in different ways.

Continuing to refer to FIG. 8 and FIG. 9, a dielectric layer 150 is formed on the base exposed by the gate structure, the precursor spacer 144 and the dummy spacer 145, and the dielectric layer 150 exposes the gate structure, the The precursor spacer 144 and the dummy spacer 145 .

The dielectric layer 150 is used to realize the electrical isolation between adjacent semiconductor structures, and is also used to define the size and position of the subsequent vacuum spacers.

In this embodiment, the dielectric layer 150 is an interlayer dielectric layer made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

The step of forming the dielectric layer 150 includes: on the exposed substrate of the dummy gate structure 121, the precursor spacer 144 and the dummy spacer 145 by chemical vapor deposition (for example: fluid chemical vapor deposition) and other methods forming a dielectric material layer, the dielectric material layer covering the dummy gate structure 121; removing the dielectric material layer higher than the dummy gate structure 121, exposing the dummy gate structure 121, the precursor spacer 144 and the dummy gate structure 121; Side wall 145.

It should be noted that, in this embodiment, the gate structure is a dummy gate structure 121, so continue to refer to FIG. 8 and FIG. 9, after forming the dielectric layer 150, remove the dummy gate structure 121 (as shown in FIG. 6 (shown) to form an opening and form a metal gate structure 120 within the opening.

In this embodiment, the semiconductor structure has a "high-K metal gate" structure; therefore, the step of removing the dummy gate structure 121 is used to form a metal gate structure.

The dummy gate structure 121 spans the fin portion 130 and covers part of the top and sidewall surfaces of the fin portion 130 , so the bottom of the opening formed by removing the dummy gate structure 121 exposes the top and the sidewall of the fin portion 130 . part of the sidewall surface. Therefore, the metal gate structure 120 formed in the opening also crosses the fin portion 130 and covers part of the top and sidewall surfaces of the fin portion 130 .

The metal gate structure 120 includes a gate dielectric layer (not shown in the figure) on the substrate and a gate electrode (not shown in the figure) on the gate dielectric layer.

The gate dielectric layer is used to realize electrical isolation between the formed gate structure and the channel in the substrate. The material of the gate dielectric layer is a high-K dielectric material. Wherein, the high-K dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer is HfO ₂ . In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

The gate electrode layer is used as an electrode to realize electrical connection with an external circuit. In this embodiment, the material of the gate electrode layer is W. In other embodiments of the present invention, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti and the like.

It should be noted that, since the material of the fin portion 130 is InGaAs, compared with the technical solution in which the material of the fin portion is other semiconductor materials, in this embodiment, the thickness of the gate dielectric layer is larger, so that the The gate dielectric layer has a larger equivalent oxide thickness (Equivalent Oxide Thickness) to suppress gate leakage current. Specifically, in this embodiment, the thickness of the gate dielectric layer is arrive within range.

Referring to FIG. 10 and FIG. 11 , the precursor spacer 144 (as shown in FIG. 8 and FIG. 9 ) is thinned to expose part of the sidewall of the gate structure, and the remaining precursor spacer 144 is used for Corner side walls 141 are formed.

In this embodiment, the gate structure is a metal gate structure 120, so the step of thinning includes: thinning the precursor sidewall 144 to expose part of the sidewall of the metal gate structure 120 , forming the corner side wall 141 .

Wherein, FIG. 10 is a schematic cross-sectional structure corresponding to FIG. 8 ; FIG. 11 is a schematic cross-sectional structure corresponding to FIG. 9 .

The corner spacer 141 is used together with the subsequently formed vacuum spacer to realize electrical isolation between the gate structure and other semiconductor structures.

The dielectric constant of the material of the corner sidewall 141 is greater than the dielectric constant of vacuum, so the setting of the corner sidewall 141 is conducive to improving the problem of transistor on-resistance and on-current performance degradation, and is conducive to reducing delay (delay) The appearance of the phenomenon is beneficial to improve the performance of the formed semiconductor structure.

The material of the precursor spacer 144 (as shown in FIG. 8 and FIG. 9 ) is silicon nitride, that is to say, the material of the corner spacer 141 is silicon nitride. The dielectric constant of silicon nitride is 7.5, so the formation of the corner spacer 141 of silicon nitride material is beneficial to improve the degradation of on-resistance and on-current performance of the transistor.

In this embodiment, part of the material of the precursor spacer 144 away from the substrate 100 is subjected to the second plasma treatment 220 (as shown in FIG. 6 and FIG. 7 ), so the precursor spacer 144 is thinned. The steps include: removing part of the plasma-treated material by a wet method.

The step of removing the part of the material treated by the plasma includes: using hydrofluoric acid to remove the part of the material after the second plasma treatment 220 . Specifically, in the step of using hydrofluoric acid to remove part of the material, the concentration of the hydrofluoric acid is in the range of 1/2000 to 1/100 by volume percentage. It should be noted that the volume percentage refers to the volume percentage of HF and water.

It should be noted that, in this embodiment, the step of removing the part of the material treated by the first plasma and the step of removing the part of the material treated by the second plasma are all removed in the same manner. In other embodiments of the present invention, the step of removing the part of the material treated by the first plasma and the step of removing the part of the material treated by the second plasma can also be removed in different ways.

After the plasma treatment, the etching rate of the precursor spacer 144 is relatively high by wet etching, so a combination of plasma treatment and wet etching is used to remove part of the material of the precursor spacer 144 , can effectively reduce the impact of the thinning process on other semiconductor structures on the substrate, which is beneficial to improving the yield rate and the performance of the formed semiconductor structure.

It should be noted that, as shown in FIG. 11 , in this embodiment, the precursor spacer 144 (as shown in FIG. 10 ) is located between the source-drain doped region 131 and the gate structure 120, so the The corner spacer 141 is also located between the source-drain doped region 131 and the gate structure 120 . This approach is beneficial to optimize the performance of the on-resistance and capacitance of the formed semiconductor structure, thereby improving the delay problem.

Referring to FIG. 12 and FIG. 13 , the dummy spacer 145 is removed, and a vacuum spacer 142 is formed between the gate structure and the dielectric layer 150 .

The vacuum spacer 142 is used to improve the problem of reduced conduction current in the formed semiconductor structure, and to improve the influence of a relatively thick gate dielectric layer on the formed semiconductor structure. The dielectric constant of the vacuum spacer 142 is low, which is beneficial to reduce the fringing capacitance of the formed semiconductor structure.

The step of removing the dummy spacer 145 includes: removing the dummy sidewall 145 by means of chemical diffusion etching. After removing the dummy spacer 145 , a gap is formed between the metal gate structure 120 , the corner spacer 141 and the dielectric layer 150 , and the gap is used to form the vacuum spacer 142 .

In this embodiment, the step of removing the dummy spacers 145 by means of chemical diffusion etching includes: removing the dummy sidewalls 145 with NH ₃ . Specifically, the dummy sidewall 145 is removed by chemical diffusion etching with NH ₃ using a Frontier machine. Since the material of the dummy sidewall 145 is polysilicon, the etching rate of the polysilicon material is relatively high in this way of etching, so removing the dummy sidewall 145 in this way can effectively reduce the formation of the vacuum. The impact of the sidewall 142 process on other semiconductor structures is beneficial to the improvement of yield rate and device performance.

It should be noted that, in the direction perpendicular to the surface of the substrate, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 should not be too large or too small.

In the direction perpendicular to the surface of the substrate, if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too large, that is, the size of the vacuum sidewall 142 is too large and the size of the corner sidewall 141 is too small , then the average dielectric constant of the vacuum sidewall 142 and the corner sidewall 141 is small, which will affect the function of improving the on-resistance and conduction current performance degradation; the size of the vacuum sidewall 142 is the same as that of the corner sidewall 141 If the size ratio of the vacuum sidewall 142 is too small and the size of the corner sidewall 141 is too large, then the average dielectric constant of the vacuum sidewall 142 and the corner sidewall 141 will be large, which will also affect the improvement of conduction. function of on-resistance and on-current performance degradation issues. Specifically, in this embodiment, in the step of forming the vacuum sidewall 142, along the direction perpendicular to the surface of the substrate, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is 5:4 to the range of 5:1.

Correspondingly, the present invention also provides a semiconductor structure, as shown in FIG. 13 , including:

A base, the base includes a substrate 100 and a fin 130 on the substrate 100; a dielectric layer 150 on the base; a gate structure on the fin 130 in the dielectric layer 150, the The gate structure spans the fin 130 and covers the surface of part of the top and part of the sidewall of the fin; the source and drain doped regions 131 in the fin 130 on both sides of the gate structure; The structure faces the corner spacer 141 on the sidewall of the source-drain doped region 131 ; and the vacuum spacer 142 between the gate structure and the dielectric layer 150 .

The substrate 100 is used to provide a process operation platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate, or a silicon-germanium substrate, a silicon-carbon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or III-V compound substrates, such as gallium nitride substrates or gallium arsenide substrates. The material of the substrate can be selected suitable for process requirements or easily integrated.

The fin portion 130 is used for providing a channel of the FinFET.

In this embodiment, the material of the fin portion 130 is a group III-V semiconductor material. Specifically, the material of the fin portion 130 is InGaAs. In other embodiments of the present invention, the material of the fins may also be other III-V semiconductor materials. Group III-V semiconductor materials are ideal channel materials for transistors due to their high low-field electron mobility, which is beneficial to reducing the channel length of transistors and improving the integration of semiconductor structures.

It should be noted that, in this embodiment, the base further includes an oxide layer 110 located between the substrate 100 and the fin 130 . The oxide layer 110 is used to provide an interface basis for the formation of the fin material, so as to improve the quality of the fin 130 .

The dielectric layer 150 is used to realize the electrical isolation between adjacent semiconductor structures, and is also used to define the size and position of the subsequent vacuum spacers.

In this embodiment, the dielectric layer 150 is an interlayer dielectric layer made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

The gate structure is used to control the turn-on and cut-off of the channel in the semiconductor structure.

In this embodiment, the semiconductor structure has a “high-K metal gate” structure, so the gate structure is a metal gate structure 120 . The metal gate structure 120 includes a gate dielectric layer (not shown in the figure) on the substrate and a gate electrode (not shown in the figure) on the gate dielectric layer.

The gate dielectric layer is used to realize electrical isolation between the formed gate structure and the channel in the substrate. The material of the gate dielectric layer is a high-K dielectric material. Wherein, the high-K dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the gate dielectric layer is HfO ₂ . In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

The gate electrode layer is used as an electrode to realize electrical connection with an external circuit. In this embodiment, the material of the gate electrode layer is W. In other embodiments of the present invention, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti and the like.

It should be noted that, since the material of the fin portion 130 is InGaAs, compared with the technical solution in which the material of the fin portion is other semiconductor materials, in this embodiment, the thickness of the gate dielectric layer is larger, so that the The gate dielectric layer has a larger equivalent oxide thickness (Equivalent Oxide Thickness) to suppress gate leakage current. Specifically, in this embodiment, the thickness of the gate dielectric layer is arrive within range.

The source-drain doped region 131 is used to form a source region or a drain region of the semiconductor structure.

In this embodiment, the semiconductor structure is an NMOS transistor, so the dopant ions in the source-drain doped region 131 are N-type ions, such as P, As or Sb. In other embodiments of the present invention, the semiconductor structure may also be a PMOS transistor, so the doping ions in the source and drain doping regions are P-type ions, such as B, Ga or In.

In this embodiment, along the extending direction of the fin portion 130, the distance between the source-drain doped region 131 is greater than the size of the dummy gate structure 121, that is, the semiconductor structure has a bottom-exposed source region/ The structure of the drain area (gate-to-source/drain underlap). This structure is beneficial to reduce the fringe capacitance of the drain terminal in the formed semiconductor structure, thereby improving the performance of the formed semiconductor structure. Therefore, part of the fin 130 used to form a channel between the source-drain doped region 131 is not covered by the metal gate structure 120, that is, the metal gate structure 120 exposes a part of the source-drain doped region. 131 between fins 130 for forming channels.

The corner spacers 141 are used together with the vacuum spacers 142 to realize electrical isolation between the gate structure and other semiconductor structures.

The dielectric constant of the material of the corner sidewall 141 is greater than the dielectric constant of vacuum, so the setting of the corner sidewall 141 is conducive to improving the problem of transistor on-resistance and on-current performance degradation, and is conducive to reducing delay (delay) The appearance of the phenomenon is beneficial to improve the performance of the formed semiconductor structure.

In this embodiment, the material of the corner sidewall 141 is silicon nitride. The dielectric constant of silicon nitride is 7.5, so the corner spacer 141 made of silicon nitride material is beneficial to improve the degradation of on-resistance and on-current performance of the transistor.

In other embodiments of the present invention, the material of the corner sidewall can also be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or boron carbonitride various

In this embodiment, the distance between the source-drain doped region 131 is greater than the size of the gate structure, so the corner spacer 141 is located between the source-drain doped region 131 and the gate structure on the fins 130 of the

The vacuum spacer 142 is used to improve the problem of reduced conduction current in the formed semiconductor structure, and to improve the influence of a relatively thick gate dielectric layer on the formed semiconductor structure. The dielectric constant of the vacuum spacer 142 is low, which is beneficial to reduce the fringing capacitance of the formed semiconductor structure.

It should be noted that, in the direction perpendicular to the surface of the substrate, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 should not be too large or too small.

In the direction perpendicular to the substrate surface, if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too large, that is, the size of the vacuum sidewall 142 is too large and the size of the corner sidewall 141 is too small , then the average dielectric constant of the vacuum sidewall 142 and the corner sidewall 141 is small, which will affect the function of improving the on-resistance and conduction current performance degradation; the size of the vacuum sidewall 142 is the same as that of the corner sidewall 141 If the size ratio of the vacuum side wall 142 is too small, and the size of the corner side wall 141 is too large, then the average dielectric constant of the vacuum side wall 142 and the corner side wall 141 will be large, which will also affect the improvement of conduction. function of on-resistance and on-current performance degradation issues. Specifically, in this embodiment, in the step of forming the vacuum sidewall 142, along the direction perpendicular to the surface of the substrate, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is 5:4 to the range of 5:1.

In summary, the technical solution of the present invention forms a corner sidewall on the sidewall of the gate structure facing the source-drain doped region, and the dielectric constant of the material of the corner sidewall is greater than that of a vacuum, so the corner sidewall The setting of the wall can effectively increase the average dielectric constant of the corner sidewall and the vacuum sidewall, which not only helps to maintain a small fringe capacitance, but also helps to improve the transistor on-resistance and on-current performance degradation problem, which is beneficial to improve the performance of the formed semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: providing a base comprising a substrate and a fin on the substrate; forming a gate structure on the fin, the gate structure spanning the fin and covering a portion of the top and a portion of the sidewall surface of the fin; forming source and drain doped regions in the fins on both sides of the gate structure; forming a precursor spacer on the sidewall of the gate structure facing the source-drain doped region; forming a dummy sidewall located on a sidewall of the precursor sidewall; forming a dielectric layer on the substrate where the gate structure, the precursor spacer and the dummy spacer are exposed, the dielectric layer exposing the gate structure, the precursor spacer and the dummy spacer; Thinning the precursor sidewalls to expose part of the sidewalls of the gate structure, and the remaining precursor sidewalls are used to form corner sidewalls; The dummy spacer is removed to form a vacuum spacer between the gate structure and the dielectric layer. 2. The forming method according to claim 1, wherein in the step of forming the precursor sidewall, the material of the precursor sidewall is silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, carbon One or more of silicon oxynitride, silicon oxynitride, boron nitride or carbon boron nitride. 3. The forming method according to claim 1, wherein the step of forming the precursor sidewall comprises: forming a spacer material layer on the gate structure and the substrate; removing the sidewall material layer on the gate structure and the substrate to form a precursor spacer on the sidewall of the gate structure. 4. The forming method according to claim 3, wherein the step of removing the sidewall material layer on the gate structure and on the substrate comprises: performing a first plasma treatment on the gate structure and the sidewall material layer on the substrate; The precursor sidewall is formed by removing part of the plasma-treated material in a wet method. 5. The forming method according to claim 1, wherein after forming the precursor spacer and before forming the dummy spacer, the forming method further comprises: performing a first step on the part of the precursor spacer far away from the substrate Two plasma treatment; The step of performing thinning treatment on the precursor sidewall includes: removing part of the plasma-treated material by wet method. 6. The forming method according to claim 4 or 5, wherein in the step of forming the precursor sidewall, the material of the precursor sidewall is silicon nitride; One or both of the steps of the first plasma treatment and the second plasma treatment include: plasma treatment with _H2 or He plasma. 7. The forming method according to claim 6, characterized in that, in the step of using _H2 or He plasma for plasma treatment, the process parameters include: process gas pressure within the range of 2mTorr to 100mTorr, _H2 or He flow rate In the range of 50 sccm to 500 sccm, the process temperature is in the range of 0°C to 100°C. 8. The forming method according to claim 4 or 5, wherein in the step of forming the precursor sidewall, the material of the precursor sidewall is silicon nitride; The step of removing the part of the plasma-treated material by wet method includes: using hydrofluoric acid to remove the part of the plasma-treated material. 9. The forming method according to claim 1, wherein in the step of forming the vacuum sidewall, along the direction perpendicular to the surface of the substrate, the difference between the dimension of the vacuum sidewall and the dimension of the corner sidewall The ratio is in the range of 5:4 to 5:1. 10. The forming method according to claim 1, wherein in the step of forming the doped source and drain regions, along the extending direction of the fin, the distance between the doped source and drain regions is greater than that of the gate the size of the structure; The step of forming a precursor spacer includes: forming the precursor spacer on the fin between the source-drain doped region and the gate structure. 11. The forming method according to claim 1, wherein in the step of forming the dummy spacer, the material of the dummy sidewall is polysilicon. 12. The forming method according to claim 1 or 11, wherein the step of removing the dummy spacer comprises: removing the dummy spacer by means of chemical diffusion etching. 13 . The forming method according to claim 12 , wherein the step of removing the dummy sidewall by chemical diffusion etching comprises: using NH ₃ to remove the dummy sidewall. 14 . 14 . The forming method according to claim 1 , wherein in the step of providing the substrate, the material of the fin is a III-V semiconductor material. 15. The forming method according to claim 1 or 14, wherein in the step of providing the substrate, the material of the fin is InGaAs. 16. A semiconductor structure, characterized in that, comprising: a base comprising a substrate and a fin on the substrate; a dielectric layer on the substrate; a gate structure located on the fin in the dielectric layer, the gate structure straddling the fin and covering the surface of part of the top and part of the sidewall of the fin; Source and drain doped regions located in the fins on both sides of the gate structure; a corner sidewall located on the sidewall of the gate structure facing the source-drain doped region; A vacuum spacer between the gate structure and the dielectric layer. 17. The semiconductor structure according to claim 16, wherein the material of the corner sidewall is silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, nitride One or more of boron or carbon boron nitride. 18. The semiconductor structure according to claim 16, wherein in a direction perpendicular to the substrate surface, the ratio of the size of the vacuum sidewall to the size of the corner sidewall is in the range of 5:4 to 5:1 Inside. 19. The semiconductor structure according to claim 16, wherein the material of the fin is a III-V semiconductor material. 20. The semiconductor structure according to claim 16, wherein the distance between the source and drain doped regions is greater than the size of the gate structure; The corner sidewall is located on the fin between the source-drain doped region and the gate structure.