CN108122737A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN108122737A CN108122737A CN201711379402.7A CN201711379402A CN108122737A CN 108122737 A CN108122737 A CN 108122737A CN 201711379402 A CN201711379402 A CN 201711379402A CN 108122737 A CN108122737 A CN 108122737A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 230000001105 regulatory effect Effects 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 32
- 230000006835 compression Effects 0.000 claims description 13
- 238000007906 compression Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 11
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 6
- 230000002708 enhancing effect Effects 0.000 claims description 6
- 238000003851 corona treatment Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 150000002222 fluorine compounds Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 114
- 230000008569 process Effects 0.000 description 13
- 239000010408 film Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000574 ganglionic effect Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 150000002927 oxygen compounds Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000002194 amorphous carbon material Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Inorganic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
Abstract
This disclosure relates to a kind of semiconductor device and its manufacturing method.The manufacturing method of the semiconductor device includes：Substrate is provided；Stress regulating course is formed on substrate；And form hard mask layer on stress regulating course；Wherein, the stress regulating course stress opposite to substrate application with hard mask layer.
Description
Technical field
This disclosure relates to semiconductor applications, it particularly relates to semiconductor device and its manufacturing method.
Background technology
With the rapid development of super large-scale integration, the characteristic size (critical dimension, CD) of chip
Less and less, correspondingly, the density of the functional unit on limited usable area is increasing.For example, reduction transistor size is permitted
Perhaps the quantity of the logical device included on microprocessor and memory device is increased, so as to manufacture the production with bigger complexity
Product.
But continuously improving with characteristic size, the required precision of semiconductor fabrication process is also correspondingly increased.Example
Such as, in the production process, the reduction of characteristic size and the increase of depth-to-width ratio (aspect ratio, AR) come to process bands such as etchings
Huge challenge.In this case, increase becomes the common selection of industry for the thickness of the hard mask layer of etching.
The content of the invention
One purpose of the disclosure is to provide a kind of novel semiconductor device and its manufacturing method, particularly, is related to and changes
The accuracy of the characteristic size of kind semiconductor device.
According to the disclosure in a first aspect, providing a kind of method for manufacturing semiconductor device, this method includes：Lining is provided
Bottom；Stress regulating course is formed on substrate；And form hard mask layer on stress regulating course；Wherein, stress regulating course with it is hard
Mask layer applies substrate opposite stress.
According to the second aspect of the disclosure, a kind of semiconductor device is provided, which includes：Substrate；It is formed
Stress regulating course on substrate；And it is formed in the hard mask layer on stress regulating course；Wherein, stress regulating course and hard mask
Layer applies substrate opposite stress.
By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
Referring to the drawings, according to following detailed description, the disclosure can be more clearly understood, wherein：
Fig. 1 is the schematic sectional view for showing the semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is the flow chart for the manufacturing method for showing the semiconductor device according to an embodiment of the present disclosure.
Fig. 3 A to 3F are the schematic cross-sectionals for showing semiconductor device corresponding with the part steps of method shown in Fig. 2
Figure.
Fig. 4 A and 4B is illustrated respectively according in the prior art and the semiconductor device according to an embodiment of the present disclosure
The composition of stress and the schematic sectional view of influence.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
Come the part for representing same section or there is identical function, and omit its repeated explanation.In the present specification, using similar mark
Number and letter represent similar terms, therefore, once be defined in a certain Xiang Yi attached drawing, then in subsequent attached drawing be not required pair
It is further discussed.
In order to make it easy to understand, position, size and scope of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes
Position, size and scope etc..Therefore, disclosed invention is not limited to position, size and scope disclosed in attached drawing etc. etc..
Specific embodiment
Present inventors appreciate that on traditional semiconductor device, the presence of hard mask layer may produce substrate
Raw compression (compressive stress) so that substrate deforms upon.In the case where characteristic size further reduces, firmly
The thickness of mask layer accordingly increases, and the compression of substrate can also be increased so that the deformation of substrate is more notable.This deformation meeting
Directly affect subsequent process.For example, after photoetching, patterning and etching, may existing characteristics size occur
The situation of deviation, this will influence the yield of product.
Therefore, the compression generated by thick hard mask layer is avoided or eliminated, has important meaning for the yield for improving product
Justice.
Present inventor proposes a kind of method that stress generated to hard mask layer compensates.This method is suitble to
For solving the substrate deformation problems faced in etch process.Advantageously, semiconductor can be improved using the technology of the disclosure to fill
The accuracy for the characteristic size put.In addition, those skilled in the art are understood that, although example described below is to be directed to cover firmly
The compression that mold layer generates compensates, but the present invention is readily applicable to the situation that hard mask layer applies substrate tensile stress.
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that：Unless in addition have
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
It is illustrative to the description only actually of at least one exemplary embodiment below, is never used as to the disclosure
And its application or any restrictions that use.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely illustrative, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
Fig. 1 is the schematic sectional view for showing the semiconductor device according to an embodiment of the present disclosure.
As shown in Figure 1, semiconductor device 100 includes substrate 101.The example of the material of substrate 101 can include but unlimited
In unitary semi-conducting material (such as, silicon or germanium etc.), compound semiconductor materials (such as carborundum, SiGe, GaAs, phosphatization
Gallium, indium phosphide, indium arsenide and/or indium antimonide) or its combination.In other embodiments, on substrate or insulator
The various compound substrates such as silicon (SOI), silicon germanium on insulator.It will be understood by those of skill in the art that for substrate 101 without spy
Other limitation, but can be made choice according to practical application.
Although not illustrating, on substrate 101/in can also be already formed with other components or layer, for example, gate structure,
Other components and/or interlevel dielectric layer that contact hole, lower metal line and through hole etc. are formed in earlier processing step etc..
Particularly, at least a portion needs in substrate 101 or the component or layer that have been formed on substrate 101 are etched.
As shown in Figure 1, semiconductor device 100 further includes the stress regulating course 104 to be formed on the substrate 101 and and is formed
Hard mask layer 106 on stress regulating course 104.
Stress regulating course 104 and hard mask layer 106 all apply stress to substrate 101.Also, stress regulating course 104 and hard
The stress that mask layer 106 applies substrate 101 is opposite.In general, stress regulating course 104 answers 101 application of substrate
Stress types and size that power type and size can apply substrate 101 according to hard mask layer 106 determine, to reduce as far as possible
Even offset the stress that hard mask layer 106 applies substrate 101.
In some embodiments, stress regulating course 104 applies tensile stress (tensile stress) to substrate 101.Stress
The example of the material of regulating course 104 can include but is not limited to：Silicon nitride, carborundum, SiGe etc. or its combination.For example, one
In a little embodiments, stress regulating course 104 can carry out it by cvd nitride silicon thin film and/or carborundum films and then
Ultraviolet light irradiate or nitrogen atmosphere under corona treatment the methods of prepare.It it will be understood by those of skill in the art that should
Power regulating course 104 is not limited to above example, but can be the arbitrary structure for being suitable for generating substrate stress.
The stress types and stress intensity that stress regulating course 104 applies substrate 101 can be by changing preparation condition
Technological parameters is waited to control.For example, in some embodiments, stress types that stress regulating course 104 applies substrate 101 with
And stress intensity can be changed by selecting suitable depositing operation and/or adjusting the technological parameter of depositing operation.Alternatively,
In some embodiments, the stress intensity applied to substrate 101 can be controlled by changing the thickness of stress regulating course 104.
For example, in some embodiments, can be formed by repeatedly cyclically performing the modes such as thin film deposition and/or corona treatment
Stress regulating course 104 with predetermined thickness.In Fig. 1, the thickness of stress regulating course 104 is represented with H2.Preferably, in some realities
It applies in example, the thickness H2 of stress regulating course 104 isIt is understood by those skilled in the art that stress tune
The numerical value of the thickness H2 of ganglionic layer 104 is without being limited thereto.
Hard mask layer 106 is mainly used for shifting the pattern of photoresist, and then the pattern is transferred to lining in etching process
On bottom 101.In general, as technology node further reduces (for example, reach 20nm and following), the thickness of hard mask layer 106
Degree can increase, and the compression applied to substrate 101 also can accordingly increase.
The material of traditional hard mask layer 106 generally can include but is not limited to：The oxidation of active metal or active metal
Object, nitride, fluoride, carbide, boride or its combination.Particularly, in some embodiments, may be employed by amorphous
The hard mask layer 106 that carbon is formed.Compared to other hard mask layers, amorphous carbon hard mask layer has many advantages：Preferably
Light transmittance is easy to be aligned in photoetching；Hardness is larger, and etching selectivity is higher；It is easily removed, to promoting photoetching, etch process
Level has very big help, thus is widely used in recent years in semiconductor fabrication process.
In some embodiments, hard mask layer 106 can be formed by deposition and/or the method for spin coating.For example,
In some embodiments, using plasma enhances chemical vapor deposition method (PECVD) to form hard mask layer 106.Wherein, sink
100 DEG C~400 DEG C of high temperature may be employed in product process.It will be understood by those of skill in the art that the species of hard mask layer 106 and
Preparation method is not limited to above example, but can be made choice according to practical application.
The thickness of hard mask layer 106 is represented with H1.With technology node further deeply, such as into 20nm and following,
The thickness of hard mask layer 106 can generally increase.In some embodiments, the thickness H1 of hard mask layer 106 be more than or equal toIt is understood by those skilled in the art that the numerical value of the thickness H1 of hard mask layer 106 is without being limited thereto.
In some embodiments, the stress regulating course 104 that the application introduces, which can be used for reducing, even to be eliminated by hard mask
Influence caused by stress and possibility that layer 106 generates.
Fig. 4 A and Fig. 4 B are illustrated respectively according in the prior art and the semiconductor device according to an embodiment of the present disclosure
The composition of stress and the schematic sectional view of influence.
Fig. 4 A instantiate the stress situation in semiconductor device 100 ' according to prior art.As shown in Figure 4 A, existing skill
In art, hard mask layer 106 ' is generally formed directly on substrate 101 '.Hard mask layer 106 ' applies compression to substrate 101 ', leads
Substrate 101 ' is caused to deform upon.The characteristic size that the deformation may result in subsequent etching process is not allowed, i.e. feature ruler
Very little accuracy deteriorates.
Fig. 4 B instantiate the stress situation in the semiconductor device 100 according to an embodiment of the present disclosure.As shown in Figure 4 B,
Hard mask layer 106 applies compression to substrate 101, and stress regulating course 104 applies substrate 101 opposite tensile stress.
In this case, the compression that the tensile stress that stress regulating course 104 generates can generate hard mask layer 106 compensates.Cause
This, the stress regulating course 104 introduced in the application can reduce the deformation for even eliminating substrate 101, and then improve characteristic size
Accuracy.
The person skilled in the art will easily understand, although the deformation of the substrate 101 illustrated in Fig. 4 B is it often fully compensated, this
An only example.The application does not have stringent restriction for the stress intensity of stress regulating course 104, as long as can reduce lining
The deformation at bottom 101 and the accuracy for therefore improving characteristic size.
In addition, in some cases, at the back side of substrate 101, there are layer protective layers (not to illustrate), and this protective layer
Stress, such as tensile stress generally can be also generated to substrate 101.In this case, the tensile stress generated at the back side of substrate 101
Compression with being generated in the front of substrate 101 is consistent to the effect of substrate 101 so that its deformation is more notable.
The stress regulating course 104 that the application introduces can also compensate the deformation as caused by protective layer.In identified sign regulating course
During 104 stress intensity, the stress of protective layer can be taken into account so that stress regulating course 104 can reduce or even disappear
Except the stress influence of both hard mask layer 106 and protective layer.
Fig. 2 is the flow chart for the manufacturing method for showing the semiconductor device according to an embodiment of the present disclosure.Fig. 3 A to 3F
It is the schematic sectional view for showing semiconductor device corresponding with the part steps of method shown in Fig. 2.Below in conjunction with Fig. 2 and
Fig. 3 A-3F are illustrated.Corresponding feature is readily applicable to above in conjunction with the described contents of Fig. 1.
In step 202, substrate (for example, substrate 101 of Fig. 3 A) is provided.
In step 204, stress regulating course 104 is formed on the substrate 101.
In some embodiments, stress regulating course 104 can be formed by following several sub-steps.
First, in sub-step 206, intermediate layer of material 102 is formed on the substrate 101, as shown in Figure 3B.
The example of the material of intermediate layer of material 102 can include but is not limited to：Silicon nitride, carborundum, SiGe etc. or its group
It closes.
In some embodiments, one or more formation intermediate layer of material 102 in following processing can be passed through：It is sub- normal
Pressure chemical vapor deposition (SACVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, stove
Pipe growth etc..
Afterwards, in sub-step 208, stress enhancing processing is carried out to intermediate layer of material 102 to obtain stress regulating course 104,
As shown in Figure 3 C.
It in some embodiments, can be by from the films such as the silicon nitride or carborundum that intermediate layer of material 102 includes
The hydrogen of certain content is removed, makes film shrunk to increase the stress of film.For example, in some embodiments, it can be by bag
The intermediate layer of material 102 for including such as silicon nitride film or carborundum films etc carries out ultraviolet light or carries out nitrogenous environment
Under corona treatment etc. increase the stress of intermediate layer of material 102.
Through overstress enhancing, treated that intermediate layer of material 102 is referred to as stress regulating course 104.Wherein, stress regulating course
104 pairs of substrates 101 apply stress, such as tensile stress.
In some embodiments, to intermediate layer of material 102 carry out ultraviolet light at a temperature of 320 DEG C~430 DEG C
It carries out.Preferably, in some embodiments, ultraviolet light carries out at a temperature of 415 DEG C.
In some embodiments, the time of the ultraviolet light carried out to intermediate layer of material 102 is 5 minutes~20 minutes.
Preferably, in some embodiments, the time of ultraviolet light is 20 minutes.
For example, it in some embodiments, is handled by sub- aumospheric pressure cvd, grown on the surface of the substrate 101
Silicon nitride film is as intermediate layer of material 102.Then, ultraviolet light is carried out to the silicon nitride film.Advantageously, ultraviolet lighting
Hydrogen atom concentration therein can be reduced by penetrating, so as to increase the tensile stress of silicon nitride film.It is for example, right at a temperature of 415 DEG C
After the silicon nitride film carries out the ultraviolet light of 20 minutes, stress regulating course 104 is obtained.
In addition, as described above, it in some embodiments, can be by forming the stress regulating course with predetermined thickness
104 change its stress intensity.For example, in some embodiments, cyclically cvd nitride silicon membrane layer and plasma is utilized
The silicon nitride film layer is bombarded, until the overall thickness of nitride multilayer silicon membrane layer from bottom to top reaches predetermined thickness requirement.
In some embodiments, the thickness of stress regulating course 104 can be
It is understood that the generation type and thickness size of stress regulating course 104 are not limited to above-mentioned example.This field skill
Other manner may be employed to form stress regulating course 104 on the substrate 101 in art personnel.
In step 210, as shown in Figure 3D, hard mask layer 106 is formed on stress regulating course 104.
In some embodiments, hard mask layer 106 can be formed by the method for chemical vapor deposition.
In some embodiments, using plasma enhances chemical vapor deposition method to form hard mask layer 106.Example
Such as, in deposition process, by introducing the admixture of gas (CxHy) of one or more kinds of hydrocarbon compounds, underlayer temperature is maintained at
About 100 DEG C~400 DEG C, and plasma is applied to substrate, amorphous carbon hard mask layer 106 can be obtained.In addition, inertia or
Reactant gas can be added in admixture of gas, to improve the property of amorphous carbon material.
It should be readily apparent to one skilled in the art that the formation of hard mask layer 106 is not limited to above-mentioned mode, may be employed other
Mode to form hard mask layer 106 on stress regulating course 104.For example, can using spin-coating method instead of chemical vapor deposition come
Form hard mask layer 106.Spin-coating method is easy to carry out and can also improve gap filling feature and planarizing features.
In addition, although the forming step of hard mask layer 106, shape are explained using amorphous carbon hard mask layer as example here
Material into hard mask layer is without being limited thereto, for example, the material of hard mask layer 106 can also include：Active metal or active metal
Oxide, nitride, fluoride, carbide, boride or its combination.
In some embodiments, to adapt to smaller characteristic size, the thickness of the hard mask layer 106 formed is larger.Example
Such as, in some embodiments, the thickness of hard mask layer 106 be more than or equal to106 meeting of hard mask layer formed
Apply apparent stress, such as compression to substrate 101.
As described above, pass through the hard mask layer 106 that is formed in step 210 and the stress that is formed in step 204
Regulating course 104 applies substrate 101 opposite stress, can reduce the deformation for even eliminating substrate 101.
In some embodiments, optionally, step 212 can be carried out after hard mask layer 106 is formed, by hard mask layer
106 and stress regulating course 104 pattern.
In some embodiments, patterned process can be formed by following several sub-steps.
First, patterned photoresist layer 108 is formed on hard mask layer 106 by photoetching process, as shown in FIGURE 3 E.Light
Carving technology includes photoresist layer 108 being exposed to the light with specific wavelength, and then develops to it.It is noticeable
Be the photoresist layer 108 illustrated in Fig. 3 E pattern as just illustration, it should be readily apparent to one skilled in the art that photoresist layer
108 pattern is without being limited thereto, but can be designed according to actual demand.
Afterwards, the pattern on photoresist layer 108 is transferred on hard mask layer 106 and stress regulating course 104, such as Fig. 3 F institutes
Show.
In some embodiments, can pattern transfer be carried out to hard mask layer 106 and stress regulating course 104 respectively.At this
In the case of kind, first with photoresist layer 108 as mask, the pattern on photoresist layer 108 is transferred to hard mask layer 106
On.Followed by patterned hard mask layer 106 as mask, the pattern on hard mask layer 106 is transferred to stress regulating course
On 104.
Alternatively, in some embodiments, such as by selecting suitable etchant, hard mask layer 106 and stress are adjusted
The pattern transfer that layer 104 carries out can be completed in single step.It in this case, will by the use of photoresist layer 108 as mask
Pattern on photoresist layer 108 is transferred on hard mask layer 106 and stress regulating course 104.
In some embodiments, optionally, step 214 can be carried out after the completion of the patterning, using patterned hard
Mask layer 106 and stress regulating course 104 are etched substrate 101.
It should be readily apparent to one skilled in the art that any of suitable etch process, such as wet method can be used herein
Etching, dry etching (such as plasma etching).
Advantageously, because reducing or even eliminating the deformation of substrate 101 by above step, therefore can reduce
The offset of the characteristic size in the etching process of step 214 is even avoided, so as to improve its accuracy.
In addition, although the stress regulating course 104 in figure is configured to the whole of covering substrate 101, people in the art
Member will readily appreciate that stress regulating course 104 can be made only in hard mask layer 106 with merge can be to hard mask layer 106
The position that stress compensates.
It is worth noting that, hard mask layer 106 and stress regulating course 104 in practice would generally be gone in subsequent processing
It removes.Actual semiconductor device is likely present the other steps subsequently manufactured, and in order to avoid obscuring the main points of the disclosure, it is attached
Figure is not shown and does not also go that other steps are discussed herein.
According to one aspect of the disclosure, a kind of method for manufacturing semiconductor device is provided, this method includes：Lining is provided
Bottom；Stress regulating course is formed on substrate；And form hard mask layer on stress regulating course；Wherein, stress regulating course with it is hard
Mask layer applies substrate opposite stress.
According to one embodiment, this method further includes：Patterning hard mask layer and stress regulating course；And utilize patterning
Hard mask layer and stress regulating course substrate is etched.
According to one embodiment, hard mask layer applies compression to substrate；And stress regulating course, which applies substrate to draw, answers
Power.
According to one embodiment, hard mask layer includes the one or more in llowing group of materials：Amorphous carbon, metal or its oxygen
Compound, nitride, fluoride, carbide, boride.
According to one embodiment, stress regulating course includes the one or more in llowing group of materials：Silicon nitride, carborundum, silicon
Germanium.
According to one embodiment, the thickness of hard mask layer be more than or equal to
According to one embodiment, the thickness of stress regulating course is
According to one embodiment, forming stress regulating course includes：Intermediate layer of material is formed on substrate；And to intermediate wood
The bed of material carries out stress enhancing processing to obtain stress regulating course.
According to one embodiment, pass through one or more formation intermediate layer of material in following processing：Sub- normal pressure chemical gas
Mutually deposition, plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, boiler tube growth.
According to one embodiment, intermediate layer of material is carried out at stress enhancing by the one or more in following processing
Reason：Corona treatment, ultraviolet light under nitrogen atmosphere.
According to one embodiment, ultraviolet light carries out at a temperature of 320 DEG C~430 DEG C, and irradiation time is 5 points
Clock~20 minute.
According to one embodiment, the one side opposite with forming hard mask layer of substrate forms matcoveredn, and stress tune
Ganglionic layer is configured at least reduce the stress that hard mask layer and protective layer apply substrate.
According to one aspect of the disclosure, a kind of semiconductor device is provided, which includes：Substrate；It is formed
Stress regulating course on substrate；And it is formed in the hard mask layer on stress regulating course；Wherein, stress regulating course and hard mask
Layer applies substrate opposite stress.
According to one embodiment, hard mask layer applies compression to substrate；And stress regulating course, which applies substrate to draw, answers
Power.
According to one embodiment, hard mask layer includes the one or more in llowing group of materials：Amorphous carbon, metal or its oxygen
Compound, nitride, fluoride, carbide, boride.
According to one embodiment, stress regulating course includes the one or more in llowing group of materials：Silicon nitride, carborundum, silicon
Germanium.
According to one embodiment, the thickness of hard mask layer be more than or equal to
According to one embodiment, the thickness of stress regulating course is
According to one embodiment, the one side opposite with forming hard mask layer of substrate forms matcoveredn, and stress tune
Ganglionic layer is configured at least reduce the stress that hard mask layer and protective layer apply substrate.
Word "front", "rear", " top ", " bottom " in specification and claim,
" on ", " under " etc., if it exists, being not necessarily used to describe constant for descriptive purposes
Relative position.It should be appreciated that the word so used is interchangeable in appropriate circumstances so that described herein public affairs
The embodiment opened, for example, can from it is shown here go out or other description different other orientations of those orientations on operate.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other realization methods in the arbitrary realization method of this exemplary description
Preferred or favourable.Moreover, the disclosure is from above-mentioned technical field, background technology, the content of the invention or specific embodiment
Given in the theory that is any stated or being implied that goes out limited.
As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance
Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other actual Considerations being likely to be present in actual realization method with perfect or preferable situation
Between difference.
Foregoing description can indicate to be " connected " or " coupled " element together or node or feature.As used herein
, unless otherwise expressly noted, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless otherwise expressly noted,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection indirectly of element or other feature, including profit
With the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can also be described below it is middle use certain term, and thus not anticipate
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" is as used herein, illustrate that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or combination thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the border between aforesaid operations is merely illustrative.Multiple operations
Single operation can be combined into, single operation can be distributed in additional operation, and operate can at least portion in time
Divide and overlappingly perform.Moreover, alternative embodiment can include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are changed, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to illustrating rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
- A kind of 1. method for manufacturing semiconductor device, which is characterized in that including：Substrate is provided；Stress regulating course is formed over the substrate；AndHard mask layer is formed on the stress regulating course；Wherein, the stress regulating course stress opposite to substrate application with the hard mask layer.
- 2. it according to the method described in claim 1, it is characterized in that, further includes：Pattern the hard mask layer and the stress regulating course；AndThe substrate is etched using patterned hard mask layer and stress regulating course.
- 3. according to the method described in claim 1, it is characterized in that：The hard mask layer applies compression to the substrate；AndThe stress regulating course applies tensile stress to the substrate.
- 4. according to the method described in claim 1, it is characterized in that：The hard mask layer includes the one or more in llowing group of materials：Amorphous carbon, metal or its oxide, nitride, fluorine Compound, carbide, boride.
- 5. according to the method described in claim 1, it is characterized in that：The stress regulating course includes the one or more in llowing group of materials：Silicon nitride, carborundum, SiGe.
- 6. according to the method described in claim 1, it is characterized in that：The thickness of the hard mask layer be more than or equal to
- 7. according to the method described in claim 1, it is characterized in that：The thickness of the stress regulating course is
- 8. the method according to right wants 1, it is characterised in that：Forming the stress regulating course includes：Intermediate layer of material is formed over the substrate；AndStress enhancing processing is carried out to the intermediate layer of material to obtain the stress regulating course.
- 9. the method according to right wants 8, it is characterised in that：The intermediate layer of material is formed by the one or more in following processing：Sub- aumospheric pressure cvd, low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, Boiler tube is grown.
- 10. the method according to right wants 8, it is characterised in that：By one or more to the intermediate layer of material progress stress enhancing processing in following processing：Under nitrogen atmosphere Corona treatment, ultraviolet light.
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| CN201711379402.7A CN108122737A (en) | 2017-12-20 | 2017-12-20 | Semiconductor device and its manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115172159A (en) * | 2022-08-10 | 2022-10-11 | 拓荆科技股份有限公司 | Stress balancing method of semiconductor wafer and application thereof |
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| CN1637438A (en) * | 2003-12-26 | 2005-07-13 | 精工爱普生株式会社 | Etching method, substrate having a plurality of concave portions, microlens substrate, transmission screen, and rear projector |
| CN103426749A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming opening and stacking structure |
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| CN1637438A (en) * | 2003-12-26 | 2005-07-13 | 精工爱普生株式会社 | Etching method, substrate having a plurality of concave portions, microlens substrate, transmission screen, and rear projector |
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