CN108090001B

CN108090001B - Kernel DMA (direct memory access) steady-state scheduling method and device

Info

Publication number: CN108090001B
Application number: CN201711310406.XA
Authority: CN
Inventors: 孟杰; 马瑶瑶; 薛皓琳; 卢彦; 杨建生; 方平; 吴昆鹏; 李洪斌; 杨晓璇; 张蓓; 冯艳红; 程毅轩; 穆鹤林; 申利飞
Original assignee: China Standard Software Co Ltd
Current assignee: China Standard Software Co Ltd
Priority date: 2017-12-11
Filing date: 2017-12-11
Publication date: 2020-10-27
Anticipated expiration: 2037-12-11
Also published as: CN108090001A

Abstract

The invention provides a steady-state scheduling method and a steady-state scheduling device for a kernel DMA (direct memory access), wherein the method comprises the following steps: when the system time sequence abnormity is detected, calling a time sequence mapping table; and controlling the working state of system hardware equipment according to the mapping relation of the time sequence mapping table so as to correct the time sequence to be adjusted. Therefore, the method solves the problem that the direct memory access cannot be smoothly carried out when the system time sequence is abnormal. And when the system time sequences are inconsistent, correcting the system time sequences according to the mapping relation of the time sequence mapping table by calling the time sequence mapping table. The time sequence mapping table only records the steady-state data when the system time sequence is normal, and can provide necessary basis for correcting the time sequence. In the embodiment, the hardware device of the system is controlled to correct the DMA access error condition caused by the time sequence abnormality, and the DMA scheduling function is completed through the algorithm logic, so that the system is restored to a normal working state, and serious errors such as the suspension of the kernel of the traditional operating system and the like caused by the accidental time sequence abnormality are avoided.

Description

Kernel DMA (direct memory access) steady-state scheduling method and device

Technical Field

The invention relates to the technical field of computers, in particular to a method and a device for steady-state scheduling of kernel DMA (direct memory access).

Background

At present, with the continuous development of the Loongson CPU technology, various embedded products based on the Loongson CPU are also widely applied. At the present stage, a large number of embedded products based on the Loongson CPU are increasingly applied to the fields of government, national defense, public health, finance and the like, and the Loongson CPU, as a first mature autonomous large-scale operation processor produced in China, has a larger market share in the special field of China. As a large-scale, high-performance, multi-core central processing unit, the overall performance of the system is greatly hindered only by the low-speed communication mode of hardware devices and Memory Access realized by the conventional hardware interrupt, and there is a need for a scheduling method capable of Direct Memory Access (DMA) to accelerate the efficiency of communication between hardware and an operating system.

At present, the basic DMA scheduling function is realized on the loongson processor No. 3 through processor hardware, a hardware DMA controller and an operating system kernel scheduling algorithm. However, due to the limitation of the stream slice process in the processor, there are cases where the system timing is disturbed, such as unstable or system delay, in the memory cycle and clock synchronization of the CPU cache call. At this time, if the processing method in the prior art is still adopted, it is not possible to ensure that the time sequences of the system are completely consistent, which is easy to cause serious errors such as kernel suspension of the traditional operating system, and seriously affects the stable operation of the system.

Disclosure of Invention

In view of the above, the present invention has been made to provide a core DMA steady-state scheduling method and a corresponding apparatus that overcome or at least partially solve the above-mentioned problems.

According to one aspect of the invention, a kernel DMA steady-state scheduling method is provided, which comprises the following steps:

when the system time sequence abnormity is detected, calling a time sequence mapping table;

and controlling the working state of system hardware equipment according to the mapping relation of the time sequence mapping table so as to correct the time sequence to be adjusted.

Optionally, when a system timing anomaly is detected, invoking a timing mapping table, including:

when the system time sequence is detected to be abnormal, switching the system time sequence state machine to a time sequence abnormal state;

and calling a Markov check sequence state mapping table by a kernel scheduling unit according to the time sequence abnormal state of the time sequence state machine.

Optionally, after the invoking, by the kernel scheduling unit, the markov check sequence state mapping table according to the time sequence abnormal state of the time sequence state machine, the method further includes:

and activating a time sequence delay state of the time sequence state machine, and switching the time sequence state machine from a time sequence abnormal state to the time sequence delay state.

Optionally, when the system timing state machine is a timing abnormal state, the method further includes:

the kernel scheduling unit places the information of each register of the CPU in a closed state through a system calling function;

and the kernel scheduling unit sets the system bus in a closed state through a system calling function and forbids the reading operation of the system bus I/O data.

Optionally, controlling the working state of the system hardware device according to the mapping relationship of the timing mapping table to modify the timing to be adjusted, including:

and the kernel scheduling unit calls a system calling function to control the working states of the CPU and the DMA controller according to the mapping relation of the Markov check sequence state mapping table so as to correct the time sequence to be adjusted.

Optionally, the invoking, by the kernel scheduling unit, the working states of the system call function control CPU and the DMA controller according to the mapping relationship of the markov check sequence state mapping table to modify the timing sequence to be adjusted, includes:

controlling a CPU and a DMA controller to be in an idle state by a kernel scheduling unit by utilizing a system calling function, wherein the duration of the CPU and the DMA controller in the idle state is determined according to the mapping relation of the Markov check sequence state mapping table;

the kernel scheduling unit controls the values of each register and each storage unit of the CPU to maintain the values in the last normal period by using the system calling function.

Optionally, before invoking the timing mapping table, the method further includes:

acquiring data information of DMA access of a system in a time sequence normal state, wherein the data information at least comprises the total times of the DMA access and the number of CPU clock cycles consumed by each DMA access;

and performing mathematical model training on the acquired data information according to the Markov check sequence to generate a Markov check sequence state mapping table.

Optionally, the kernel DMA steady state schedule is applied to a Loongson platform.

According to another aspect of the present invention, there is also provided a kernel DMA steady-state scheduling apparatus, including:

the calling module is configured to call the time sequence mapping table when the system time sequence abnormity is detected;

and the correcting module is configured to control the working state of system hardware equipment according to the mapping relation of the time sequence mapping table so as to correct the time sequence to be adjusted.

Optionally, the invoking module is further configured to:

Optionally, the apparatus further comprises:

and the activation module is configured to activate the time sequence delay state of the time sequence state machine and switch the time sequence state machine from the time sequence abnormal state to the time sequence delay state.

Optionally, the apparatus further comprises:

the control module is configured to enable the kernel scheduling unit to place the information of each register of the CPU in a closed state through a system calling function;

Optionally, the modification module is further configured to:

Optionally, the apparatus further comprises:

the acquisition module is configured to acquire data information of DMA access of a system in a time sequence normal state, wherein the data information at least comprises the total number of DMA access and the number of CPU clock cycles consumed by each DMA access;

and the generating module is configured to perform mathematical model training on the acquired data information according to the Markov check sequence to generate a Markov check sequence state mapping table.

According to another aspect of the present invention, there is also provided an electronic apparatus, including:

a processor; and

a memory arranged to store computer executable instructions that, when executed, cause the processor to perform a kernel DMA steady state scheduling method according to any one of the preceding claims.

According to another aspect of the present invention, there is also provided a computer readable storage medium, wherein the computer readable storage medium stores one or more programs which, when executed by an electronic device including a plurality of application programs, cause the electronic device to execute the kernel DMA steady-state scheduling method according to any one of the above.

According to the steady-state scheduling method of the kernel DMA, the time sequence state of the system can be detected firstly, and when the abnormal time sequence of the system is detected, a time sequence mapping table is called. And further, controlling the working state of system hardware equipment according to the mapping relation of the called time sequence mapping table so as to correct the time sequence to be adjusted. Therefore, the method can be applied to the condition that the time sequences of a hardware CPU, a cache of a high-speed buffer memory, a DMA controller and a memory controller are inconsistent, and solves the problem that the direct memory access can not be smoothly carried out when the time sequence of the system is abnormal in the prior art. Specifically, in the embodiment, when the system timings are inconsistent, the system timings may be corrected according to the mapping relationship of the timing mapping table by calling the specific timing mapping table. The timing mapping table of the embodiment records only the steady-state data when the system timing is normal, and can provide a necessary basis for correcting the timing by taking the steady-state data as the reference of the system timing. In addition, when the system time sequence is abnormal, the embodiment of the invention corrects the DMA access error condition caused by the time sequence abnormality by controlling the hardware equipment of the system, and further, completes the DMA scheduling function by the algorithm logic in the correction process, so that the system is restored to the normal working state, and avoids the serious errors such as the hang-up of the kernel of the traditional operating system and the like caused by the accidental time sequence abnormality.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, taken in conjunction with the accompanying drawings.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a flow diagram of a method for steady-state scheduling of kernel DMA according to one embodiment of the present invention;

FIG. 2 is an idealized DMA timing diagram in accordance with one embodiment of the present invention;

FIG. 3 is a diagram of an exemplary DMA timing violation, according to one embodiment of the invention;

figure 4 is a schematic diagram of the structure of the markov check sequence module according to an embodiment of the present invention;

FIG. 5 is a diagram of various states of a sequential state machine according to one embodiment of the invention;

FIG. 6 is a detailed flowchart of a method for steady-state scheduling of kernel DMA according to an embodiment of the present invention;

FIG. 7 is a first schematic diagram of a core DMA steady-state scheduler, according to an embodiment of the invention;

FIG. 8 is a second schematic diagram of a core DMA steady-state scheduler, according to an embodiment of the invention;

FIG. 9 is a block diagram of a computing device for performing a kernel DMA steady-state scheduling method in accordance with the present invention, according to one embodiment of the present invention; and

FIG. 10 is a memory location for holding or carrying program code implementing a kernel DMA steady state scheduling method according to one embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Currently, when implementing hardware devices and memory access operations in computer technology, the low-speed communication mode of only relying on traditional hardware interrupts has greatly hindered the overall performance of the system. Therefore, in order to improve the communication efficiency between the hardware device and the operating system, a scheduling method capable of Direct Memory Access (DMA) has been adopted in the prior art. DMA technology is a direct memory access technology, which is a mechanism for quickly transferring data. The importance of the DMA technology is that the DMA technology is used for data access without the intervention of a CPU, and the efficiency of the system for executing application programs can be improved.

However, the precondition that some direct memory access methods in the present stage need to be dependent on is that the CPU, the cache of the cache memory, the DMA controller, and the memory controller are completely unified in time sequence, and there is no time sequence disorder. Due to the limited manufacturing process in the domestic CPU field, when the domestic CPU is used to perform the above operations, it cannot be guaranteed that the system timings are completely consistent. However, when the system timing is abnormal, if the existing direct memory access method is still used, serious errors such as kernel suspension of the conventional operating system are usually caused, and the stable operation of the system is seriously affected.

In order to solve the technical problem, the invention provides a kernel DMA steady-state scheduling method. FIG. 1 is a flow diagram of a method for steady-state scheduling of core DMA according to one embodiment of the invention. As shown in fig. 1, the kernel DMA steady-state scheduling method at least includes steps S102 to S104:

step S102, when the system time sequence is detected to be abnormal, calling a time sequence mapping table;

and step S104, controlling the working state of the system hardware equipment according to the mapping relation of the time sequence mapping table so as to correct the time sequence to be adjusted.

According to the steady-state scheduling method of the kernel DMA, the time sequence state of the system can be detected firstly, and when the abnormal time sequence of the system is detected, a time sequence mapping table is called. And further, controlling the working state of system hardware equipment according to the mapping relation of the called time sequence mapping table so as to correct the time sequence to be adjusted. Therefore, the method can be applied to the condition that the time sequences of a hardware CPU, a cache, a DMA controller and a memory controller are inconsistent, and solves the problem that the direct memory access cannot be stably carried out when the system time sequence is abnormal in the prior art. Specifically, in the embodiment, when the system timings are inconsistent, the system timings may be corrected according to the mapping relationship of the timing mapping table by calling the specific timing mapping table. The timing mapping table of the embodiment records only the steady-state data when the system timing is normal, and can provide a necessary basis for correcting the timing by taking the steady-state data as the reference of the system timing. In addition, when the system time sequence is abnormal, the embodiment of the invention corrects the DMA access error condition caused by the time sequence abnormality by controlling the hardware equipment of the system, and further, completes the DMA scheduling function by the algorithm logic in the correction process, so that the system is restored to the normal working state, and avoids the serious errors such as the hang-up of the kernel of the traditional operating system and the like caused by the accidental time sequence abnormality.

In this embodiment, FIG. 2 shows an idealized DMA timing diagram according to one embodiment of the present invention. Referring to fig. 2, the CPU timing cycle of this embodiment is 1.2us, and in actual operation, the CPU timing cycle may be divided into two parts, where the CPU masters the control right of the system in the first part (see timing 0.6us of cache1 in fig. 2) of the CPU timing cycle, and the CPU controls the system bus and other operations. The control right of the system is grasped by the DMA controller in the second part of the CPU timing cycle (see the timing 0.6us of the cache2 in FIG. 2), and the system bus and other operations are controlled by the DMA controller. As shown in fig. 2, in the ideal time sequence, the CPU and the DMA controller execute corresponding control operations within the respective set control time, and there is no timing confusion caused by incomplete timing. Therefore, when the hardware equipment interacts with the memory controller, serious errors such as kernel suspension caused by time sequence disorder can not occur.

However, due to the defects of domestic design and production process, part of domestic CPU motherboards cannot completely rely on hardware to implement all direct memory access functions. Moreover, the DMA timing is realized by depending on the kernel of the operating system to transfer the right with the CPU timing, and in the transfer process of the right, the phenomenon that the system timing is inconsistent often occurs. In particular, FIG. 3 illustrates an exemplary DMA timing violation diagram, according to one embodiment of the invention. Referring to fig. 3, when the DMA control timing violation occurs when the core applies for a DMA period exceeding the rated CPU timing period, since it crosses over to the next CPU period, the data in the next CPU period is accessed illegally (for example, the violation timing portion in fig. 3 should be controlled by the CPU to control the system bus and other operations, but at this stage shown in fig. 3, the DMA controller still controls the system bus, and at this time, the DMA control timing violation occurs, and the operation performed on the data bus is an illegal read/write operation). The DMA timing violation may destroy the data in the bus and cause an operating system exception. Although the traditional direct memory access method can meet the requirement of direct memory access of most platforms, the method is only limited to the condition that the time sequences of a hardware CPU, a cache and a memory controller are consistent, and the direct memory access operation cannot be completed under the condition that the time sequence sequences of systems such as the memory, the cache and the like are not synchronous.

In order to solve the problems of suspending the kernel of the conventional operating system and the like caused by the system time sequence abnormality, a markov check sequence module is additionally arranged in the kernel and is used for correcting illegal read/write access operations on a system bus when the time sequence is out of range and solving the problem of inconsistency of a CPU, a cache, a DMA controller and a memory controller in the time sequence. When the consistency of the system time sequence conflicts, the method of the embodiment can finish the correction operation of the system time sequence by depending on the self verification mechanism of the Markov verification sequence module and the buffer area, so that the same effect as the DMA access under the normal condition can be achieved when the system time sequence is abnormal.

The markov check sequence of the present embodiment is a generic term of a time sequence check optimization mathematical model with the current state being independent of the past time. In addition, in the present embodiment, the current past system history state obtained based on the markov check sequence is relatively independent from the future (i.e., the current future state) and is not actually related to the future state.

Further, fig. 4 is a schematic diagram illustrating a structure of the markov check sequence module according to an embodiment of the present invention. As shown in fig. 4, the markov check sequence module provided in this embodiment may include a system timing state machine, a markov check sequence state mapping table, and a kernel scheduling unit. The kernel scheduling unit is an independent unit added in the kernel of the operating system and is a basic unit of the whole Markov check sequence module. The system is internally responsible for coordinating the work of a system time sequence state machine and a Markov check sequence state mapping table, and externally responsible for sending a control instruction to a bus and a hardware DMA controller through a system call function systemcall. In this embodiment, the kernel scheduling unit is a core component, which not only schedules other components in the markov check sequence module, but also realizes the coordination work inside the markov check sequence module, and can correspondingly control the system hardware device according to different time sequence states of the system. It can be seen that the kernel scheduling unit plays an extremely important role in this embodiment.

In addition, the present embodiment also relates to a system sequential state machine, and fig. 5 shows different state diagrams of the sequential state machine according to an embodiment of the present invention. As shown in fig. 5, the system timing state machine is divided into three basic system states, including a timing normal state, a timing abnormal state, and a timing delay state. Normally, the system is in a time-sequential normal state. In this embodiment, the timing state of the system may be detected first, and specifically, the timing state of the system may be detected by separately starting one detection unit by the kernel. When it is detected that the system timing is in a normal state, no other operation needs to be performed. However, when the system time sequence is detected to be abnormal, the situation that the time sequence of the system is out of range is shown, and at the moment, the system time sequence state machine can be switched from the time sequence normal state to the time sequence abnormal state.

Further, in this embodiment, when the timing state machine is in the timing abnormal state, the markov check sequence state mapping table may be called by the kernel scheduling unit. And then, the kernel scheduling unit controls the working state of the system hardware equipment according to the mapping relation of the Markov check sequence state mapping table so as to achieve the purpose of correcting the time sequence to be adjusted in the future.

Specifically, the state mapping table of the markov check sequence of the present embodiment is generated based on the time-sequence check optimization mathematical model of the markov check sequence. The Markov check sequence is a time sequence check optimization mathematical model with the current state independent of the past time, namely, future data can be measured by early empirical data, namely, tasks which start to be performed at a certain time in the future can be measured by early steady-state empirical data. In this embodiment, the markov check sequence only counts the total CPU clock cycles experienced by all hardware during DMA accesses under normal timing conditions for estimating its time data at steady state timing. When an unsteady condition occurs, redeployment can be performed according to the steady historical data.

In addition, there is a special case of the markov check sequence, that is, under the normal time sequence condition, the total CPU cycle experienced by a certain hardware in DMA access is uncertain. It should be noted that the above special case is actually derived from the clock frequency consistency, which is not present in the field of computer hardware engineering, but in order to prevent the occurrence of the philosophical special case, the sum of the CPU timing with the largest consumption and N CPU clock cycles may be eliminated as the final value of the statistics in the present embodiment.

Therefore, when generating the markov check sequence mapping table, the present embodiment may first acquire data information for DMA access of the system in a time sequence normal state. The data information includes at least a total number of DMA accesses and a number of CPU clock cycles consumed for each DMA access. Further, performing mathematical model training on the acquired data information according to the Markov check sequence to generate a Markov check sequence state mapping table. It should be noted that the data information of the DMA access obtained in this embodiment is only an example, and the present invention may also obtain various related data according to actual requirements, and further perform mathematical model training on the obtained data according to the markov check sequence to generate a state mapping table of the markov check sequence with higher accuracy.

The markov check sequence state mapping table of this embodiment is only exemplified by table 1, and table 1 shows the markov check sequence state mapping table of an encryption card according to an embodiment of the present invention. Referring to table 1, in the case where the time sequence was normal in the past, the encryption card 1 makes a total of 450 times of direct memory access (only 2 times are illustrated in the present embodiment, and others are not shown), and the CPU clock cycle consumed in each access process is 30 CPU cycles. On the basis of the Markov check sequence state mapping table, if a time sequence abnormality occurs under a certain specific condition, the clock cycle of the direct memory access should be 30 CPU cycles according to the experience of the prior statistical data.

TABLE 1

After the above steps are completed, the state mapping table of the markov check sequence can be obtained. Meanwhile, when the sequential state machine is in a sequential abnormal state, the data in the system bus can be damaged, and an operating system exception is generated. At this time, according to the method of the present invention, the kernel scheduling unit may put the information of each register of the CPU into a closed state through a system call function. On the other hand, the kernel scheduling unit can also set the system bus in a closed state through a system call function, and forbid the read-write operation of the system bus I/O data. The method can control the working state of each hardware device of the system when the system time sequence is abnormal so as to avoid serious errors such as kernel suspension and the like caused by the abnormal system time sequence.

In addition, after the execution of the operations is finished, the timing delay state of the timing state machine can be activated, and the timing state machine can be switched from the timing abnormal state to the timing delay state. Further, in the time sequence delay state, step S104 is executed, and the kernel scheduling unit controls the operating state of the system hardware device according to the mapping relationship of the markov check sequence state mapping table, so as to correct the time sequence to be adjusted. Specifically, the kernel scheduling unit may invoke a system call function to control the operating states of the CPU and the DMA controller according to the mapping relationship of the markov check sequence state mapping table, so as to correct the timing sequence to be adjusted. In this embodiment, the kernel scheduling unit may control the CPU and the DMA controller to be in an idle state by using a system call function, and return to a normal state after the timing verification is normal. In this embodiment, the duration of the idle state of the CPU and the DMA controller is determined according to the mapping relationship of the markov check sequence state mapping table. In addition, in this embodiment, the kernel scheduling unit may control values of each register and each storage unit of the CPU to be maintained at values in the previous normal cycle by using the system call function.

Further, according to the method of the embodiment, after the system timing is corrected by the markov check sequence, the system timing may be checked again. If the problem is still found, the system continues to enter the abnormal state of the time sequence, and then the system time sequence is corrected again according to the steps, and if the system time sequence is corrected without errors, the system returns to the normal state.

Therefore, when the system timing is found to be abnormal, the present embodiment can switch the system timing state machine to the abnormal timing state in time. And when the system time sequence is abnormal, the information of each register and the system bus of the CPU is suspended and closed, and the I/O data read-write operation of the system bus is forbidden. Furthermore, the method can also suspend various illegal operations of the equipment in time when the system time sequence is abnormal, thereby reducing the probability of errors of the operating system caused by the abnormal time sequence. In addition, the embodiment can also call the markov check sequence state mapping table and activate the system time sequence delay state when the system time sequence is abnormal. And correcting the time sequence to be adjusted according to the mapping relation of the Markov check sequence state mapping table in the system time sequence delay state. In the specific correction process, the values of each register and each storage unit of the CPU in the latest normal period of the CPU can be maintained, and the CPU is controlled to idle until the correction of the system time sequence is completed. In an optional embodiment, the kernel DMA steady-state scheduling method is applied to the Loongson platform.

The following describes the core DMA steady-state scheduling method according to the present invention in a specific embodiment.

Example one

FIG. 6 is a specific flowchart of a steady-state scheduling method for core DMA according to an embodiment of the present invention.

In this embodiment, step S601 is executed first, and the system normally operates in a time sequence normal state; .

Step S602 is further executed, whether the current time sequence of the system is abnormal is detected, if so, step S603 is executed, and if not, the system time sequence of the step S601 is returned to a normal state;

step S603, switching the system time sequence state machine from the time sequence normal state to the time sequence abnormal state;

step S604, calling a Markov check sequence mapping table to correct the system time sequence;

step S605, activating a time sequence delay state, and switching a system time sequence state machine from a time sequence abnormal state to a time sequence delay state;

in step S606, the timing verification is completed.

It should be noted that, in this embodiment, step S604 and step S605 do not have a definite sequence, and the step of this embodiment may first call the alckoff check sequence mapping table to correct the system timing, and then activate the timing delay state of the system timing state machine. In addition, the time sequence delay state of the system time sequence state machine may be activated first, and the lackoff check sequence mapping table is further invoked to correct the system time sequence, and the two steps may also be performed simultaneously, which is not specifically limited in this embodiment.

In addition, in the present embodiment, after the execution of step S606 is finished, the system timing verification is completed. At this time, the detecting unit may be restarted by the kernel to detect the timing state of the system. If the system timing is detected to be abnormal, the steps S603 to S605 are executed again until the system timing is normal, and the system timing state machine is switched to the timing normal state.

Based on the same inventive concept, the present invention provides a kernel DMA steady-state scheduling apparatus, and fig. 7 is a first schematic diagram of the kernel DMA steady-state scheduling apparatus according to an embodiment of the present invention. As shown in fig. 7, includes:

the calling module 710 is configured to call the timing mapping table when detecting that the system timing is abnormal;

and a correcting module 720, coupled to the calling module 710, configured to control the operating state of the system hardware device according to the mapping relationship of the timing mapping table, so as to correct the timing to be adjusted.

In a preferred embodiment, the invoking module 710 is further configured to:

and calling the Markov check sequence state mapping table by the kernel scheduling unit according to the time sequence abnormal state of the time sequence state machine.

In a preferred embodiment, as shown in fig. 8, the apparatus further comprises:

the activation module 730 is configured to activate a timing delay state of the timing state machine and switch the timing state machine from the timing abnormal state to the timing delay state.

In a preferred embodiment, as shown in fig. 8, the apparatus further comprises:

the control module 740 is configured to enable the kernel scheduling unit to place the information of each register of the CPU in a closed state through a system call function;

and the kernel scheduling unit puts the system bus into a closed state through a system calling function and forbids the reading operation of the system bus I/O data.

In a preferred embodiment, the modification module 720 is further configured to:

the kernel scheduling unit controls the CPU and the DMA controller to be in an idle state by utilizing a system calling function, wherein the duration of the CPU and the DMA controller in the idle state is determined according to the mapping relation of the Markov check sequence state mapping table;

In a preferred embodiment, as shown in fig. 8, the apparatus further comprises:

an obtaining module 810, configured to obtain data information of DMA access performed by the system in a time sequence normal state, where the data information at least includes the total number of DMA accesses and the number of CPU clock cycles consumed by each DMA access;

the generating module 820 is coupled to the obtaining module 810, and configured to perform mathematical model training on the obtained data information according to the markov check sequence, and generate a state mapping table of the markov check sequence.

The kernel DMA steady-state scheduling method and the kernel DMA steady-state scheduling device have the following beneficial effects that:

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in a core DMA steady state scheduling apparatus according to embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

Embodiments of the present invention also provide an electronic device, comprising a processor and a memory arranged to store computer executable instructions, which when executed cause the processor to perform a method of kernel DMA steady-state scheduling according to any of the above embodiments.

Embodiments of the present invention also provide a computer storage medium, where the computer storage medium stores one or more programs, and when the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to execute the kernel DMA steady-state scheduling method according to any one of the above embodiments.

For example, FIG. 9 illustrates a computing device that may implement a kernel DMA steady-state scheduling method. The computing device conventionally includes a computer program product or computer-readable medium in the form of a processor 910 and memory 920. The memory 920 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. The memory 920 has a storage space 930 for storing program code 931 for performing any of the method steps of the method described above. For example, the storage space 930 storing the program codes may include respective program codes 931 each for implementing various steps in the above method. The program code can be read from or written to one or more computer program products. These computer program products comprise a program code carrier such as a hard disk, a Compact Disc (CD), a memory card or a floppy disk. Such a computer program product is typically a portable or fixed storage unit as shown for example in fig. 10. The storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 920 in the computing device of fig. 9. The program code may be compressed, for example, in a suitable form. Typically, the storage unit comprises computer readable code 931' for performing the steps of the method of the present invention, i.e. code that is readable by a processor such as 910, which when run by a computing device causes the computing device to perform the steps of the method described above.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Thus, it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the invention have been illustrated and described in detail herein, many other variations or modifications consistent with the principles of the invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be understood and interpreted to cover all such other variations or modifications.

Claims

1. A steady-state scheduling method for kernel DMA (direct memory access), comprising the following steps:

controlling the working state of system hardware equipment according to the mapping relation of the time sequence mapping table so as to correct the time sequence to be adjusted; the method comprises the following steps:

the method comprises the following steps that a kernel scheduling unit controls a CPU and a DMA controller to be in an idle state by utilizing a system calling function, wherein the duration time of the CPU and the DMA controller in the idle state is determined according to the mapping relation of a Markov check sequence state mapping table;

2. The method of claim 1, wherein invoking a timing map when a system timing anomaly is detected comprises:

3. The method of claim 2, wherein after invoking the Markov check sequence state mapping table by the kernel scheduling unit according to the time abnormal state of the time sequence state machine, further comprising:

4. The method of claim 2, wherein when the system timing state machine is a timing anomaly, further comprising:

and the kernel scheduling unit sets the system bus in a closed state through a system calling function and forbids the read-write operation of the I/O data of the system bus.

5. The method of claim 1, prior to invoking the timing map, further comprising:

6. An electronic device, comprising:

a processor; and

a memory arranged to store computer executable instructions that, when executed, cause the processor to perform the kernel DMA steady-state scheduling method of any of claims 1-5.

7. A computer readable storage medium, wherein the computer readable storage medium stores one or more programs which, when executed by an electronic device comprising a plurality of application programs, cause the electronic device to perform the kernel DMA steady-state scheduling method of any one of claims 1-5.