CN108074814B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is provided with a plurality of isolation structures; forming a gate structure on the substrate between adjacent isolation structures; forming stress layers in the substrate on two sides of the gate structure; and forming a cap layer on the stress layer, wherein the process for forming the cap layer comprises a spin coating process. According to the technical scheme, after the stress layer is formed, the cap layer is formed on the stress layer, and the process for forming the cap layer comprises a spin coating process. The cap layer is formed through a spin coating process, so that the appearance of the formed cap layer cannot change along with the change of the appearance of the stress layer, and a plurality of cap layers between the gate structures have flush surfaces, so that the formed cap layer can better repair the appearance of the stress layer, the surface appearance of the formed cap layer can be improved, and the electrical performance of the formed semiconductor structure can be improved.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a method for forming the same.

Background technique

As the most basic semiconductor device, transistors are being widely used. With the increase in the density and integration of components in integrated circuits, the size of transistors is getting smaller and smaller. As transistor size shrinks, transistor channel length and gate length also shorten. The shortening of the channel length of the transistor makes the approximation of the graded channel no longer tenable, causing the short channel effect, which in turn generates leakage current and affects the performance of the semiconductor device. By introducing stress to the channel region of the transistor, the mobility of carriers in the channel can be improved, thereby increasing the driving current of the transistor, thereby suppressing the leakage current of the transistor.

The method of introducing stress to the channel region of the transistor is to form a stress layer in the transistor to provide compressive stress to the channel region of the PMOS transistor and to introduce tensile stress to the channel region of the NMOS transistor to improve the load in the channel region of the transistor. The mobility of the carriers, thereby improving the performance of the transistor. Specifically, the stress layer is usually formed of a silicon germanium material or a silicon carbon material, and compressive stress or tensile stress is formed through lattice mismatch between the stress layer and the silicon crystal.

However, the semiconductor structure with the stress layer formed in the prior art often has the problem of poor electrical performance.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical properties of the formed semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

providing a substrate with a plurality of isolation structures in the substrate; forming a gate structure on the substrate between adjacent isolation structures; forming a stress layer in the substrate on both sides of the gate structure; A cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process.

Optionally, the step of forming a cap layer on the stress layer includes: forming a precursor layer on the stress layer through a spin coating process; and curing the precursor layer to form the cap layer.

Optionally, in the step of forming a precursor layer on the stressor layer by a spin coating process, the precursor layer is a polysilane layer.

Optionally, in the step of forming a precursor layer on the stressor layer by a spin coating process, the material of the precursor layer includes one or both of polydisilane and cyclopentasilane.

Optionally, in the step of forming a precursor layer on the stressor layer by a spin coating process, the precursor layer further includes a solvent, the solvent is a hydrocarbon, and the number of carbon atoms in the hydrocarbon is greater than 4.

Optionally, in the step of forming a precursor layer on the stressor layer by a spin coating process, the hydrocarbon is C ₅ H ₁₂ .

Optionally, after the precursor layer is formed and before the curing process, the forming method further includes: removing a part of the thickness of the precursor layer by etching back.

Optionally, the step of etching back the precursor layer includes: etching back the precursor layer by dry etching.

Optionally, the step of curing the precursor layer includes: baking the precursor layer; and annealing the baked precursor layer to form the cap layer.

Optionally, in the step of baking the precursor layer, the temperature of the baking treatment is in the range of 150°C to 350°C, and the time of the baking treatment is in the range of 5 minutes to 15 minutes.

Optionally, in the step of annealing the baked precursor layer, the temperature of the annealing treatment is in the range of 350° C. to 800° C., and the time of the annealing treatment is in the range of 2 minutes to 8 minutes.

Optionally, one or both of the step of forming a precursor layer on the stressor layer by a spin coating process and the step of curing the precursor layer include: performing the spin coating process in an inert gas atmosphere. Or in the curing process, the pressure of the inert gas is in the range of 200 Torr to 500 Torr.

Optionally, the step of forming the stress layer includes: forming an opening in the substrate on both sides of the gate structure; filling the opening with a stress material to form the stress layer.

Optionally, the step of forming the stress layer includes: forming a "Σ"-shaped stress layer.

Optionally, the step of forming the stress layer includes: a material of the stress layer is silicon germanium material.

Optionally, the step of filling the opening with a stress material includes: filling the opening with a stress material by means of epitaxial growth.

Optionally, after forming the cap layer, the forming method further includes: forming a metal layer covering the cap layer.

Optionally, in the step of forming the metal layer, the material of the metal layer is nickel.

Correspondingly, the present invention also provides a semiconductor structure, comprising:

a substrate with a plurality of isolation structures in the substrate; gate structures located on the substrate between adjacent isolation structures; stress layers located in the substrate on both sides of the gate structure; caps located on the stress layer layer, the cap layer is a cap layer formed by a spin coating process.

Optionally, the material of the cap layer includes silicon.

Compared with the prior art, the technical solution of the present invention has the following advantages:

According to the technical solution of the present invention, after the stress layer is formed, a cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process. Since the process of forming the capping layer includes a spin coating process, the topography of the formed capping layer will not change with the change of the topography of the stressing layer, and the plurality of capping layers between the gate structures have a flush level Therefore, the formed cap layer can better repair the morphology of the stress layer, thereby improving the surface morphology of the formed cap layer and improving the electrical properties of the formed semiconductor structure.

In an optional solution of the present invention, after the cap layer of the polysilane material is formed, a metal layer covering the cap layer is formed to form a metal silicide to reduce contact resistance. Compared with the technical solution of forming the repair layer, the technical solution of the present invention directly realizes the repair of the stress layer morphology through the cap layer, which simplifies the process steps, is beneficial to reduce the process difficulty and improve the yield.

Description of drawings

1 to 3 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure with a stress layer;

4 to 9 are schematic structural diagrams corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

It can be known from the background art that the semiconductor structure with the stress layer in the prior art has the problem of poor electrical performance. Now combined with a method of forming a semiconductor structure with a stress layer to analyze the reasons for its poor performance:

Referring to FIG. 1 to FIG. 3 , schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure with a stress layer are shown.

Referring to FIG. 1 , a substrate 10 is provided having isolation structures 11 therein; gate structures 12 are formed on the substrate 10 between adjacent isolation structures 11 ; substrates 100 on both sides of the gate structures 12 are formed A stress layer 13 is formed inside; a cap layer 14 is formed on the stress layer 13 .

Specifically, the step of forming the stress layer 13 includes: forming an opening in the substrate 100 on both sides of the gate structure 12 ; filling the opening with a stress material to form the stress layer 13 .

The material of the stress layer 12 is silicon germanium. In the process of epitaxial growth filling of SiGe material, the growth rate of SiGe material on different crystal planes of the silicon substrate is different, and the growth rate on the (100) plane is greater than that on the (111) plane. Therefore, in the process of forming the stress layer 13 , the stress layer 13 adjacent to the isolation structure 11 tends to have a relatively serious facet effect, resulting in the stress layer adjacent to the isolation structure 13 . 13 cannot completely fill the opening, so that the morphology of the formed stress layer 13 is defective (as shown in the circle 15 in FIG. 1 ).

Defects in the morphology of the stress layer 13 will cause the cap layer 14 formed on the stress layer 13 to be prone to defects, which will increase the difficulty of the process of forming the cap layer 13, and it is difficult to guarantee the cap layer 14 formed. Therefore, in the subsequent process, especially in the process of forming the contact hole, the cap layer 14 is easily damaged and the stress layer 13 is exposed. The exposure of the stressor layer 13 increases the possibility of damage to the stressor layer 13 , thereby affecting the yield of the semiconductor structure and the performance of the semiconductor structure.

In order to improve the defects of the stress layer 13 morphology, one method is to reduce the facet effect of the stress layer 13 as much as possible by controlling the process conditions of the stress layer 13 growth, so as to improve the morphology of the stress layer 13 . However, the improvement effect of this method on the morphology defects of the stress layer 13 is limited.

Another method is, as shown in FIG. 2 , to form a polysilicon repair layer 15 on the gate structure 12 and the stressor layer 13 ; then, as shown in FIG. 3 , remove the gate by etching back. The repairing layer 15 on the top and sidewalls of the pole structure 12 (as shown in FIG. 2 ) allows the repairing layer 15 remaining on the stressing layer 13 to modify the morphology of the stressing layer 13 .

However, in the method of using the repair layer 15 to repair the morphology of the stress layer 13, the difficulty of controlling the thickness of the repair layer 15 and the control difficulty of the process of engraving the repair layer 15 back are relatively high:

If the thickness of the repair layer 15 is too large, or the thickness of the repair layer 15 is too small to be etched back, the repair layer 15 of polysilicon material is often conformally covered on the gate structure 12 and the stress layer 13 . Therefore, when the repair layer 15 is etched back, it is easy to leave the repair layer 15 on the sidewall of the gate structure 12 (as shown in the circle 18 in FIG. 3 ). When the plug is subsequently formed, metal silicide is easily formed on the repair layer 15 remaining on the sidewall of the gate structure 12 , which causes a short circuit between the formed plug and the gate structure 12 and affects the formed semiconductor structure. performance.

If the thickness of the repairing layer 15 is too small, or the thickness of the repairing layer 15 is too large, the repairing layer 15 is removed too much, and the remaining repairing layer 15 is too little, and the repairing layer 15 The function of repairing the defects of the stress layer 13 is not obvious (as shown in the circle 17 in FIG. 3 ).

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including:

providing a substrate with a plurality of isolation structures in the substrate; forming a gate structure on the substrate between adjacent isolation structures; forming a stress layer in the substrate on both sides of the gate structure; A cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process.

According to the technical solution of the present invention, after the stress layer is formed, a cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process. Since the capping layer is formed by a spin coating process, the topography of the formed capping layer will not change with the change of the topography of the stressing layer, and the plurality of capping layers between the gate structures are flush with each other. Therefore, the formed cap layer can better repair the morphology of the stress layer, thereby improving the surface morphology of the formed cap layer and improving the electrical properties of the formed semiconductor structure.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 4 to FIG. 9 , schematic structural diagrams corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention are shown.

Referring to FIG. 4, a substrate 100 is provided having a plurality of isolation structures 101 therein.

The substrate 100 is used to provide a process operating platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the material of the substrate can also be selected from polysilicon or amorphous silicon; the substrate can also be selected from silicon, germanium, gallium arsenide or silicon-germanium compounds; the substrate also Other semiconductor materials may be used, or the substrate may also be selected from having an epitaxial layer or a silicon-on-epitaxial layer structure.

The isolation structure 101 is used to electrically isolate adjacent active areas (Active Area, AA).

The material of the isolation structure 101 is silicon oxide. In other embodiments of the present invention, the material of the isolation structure 101 may also be other insulating materials such as fluorosilicate glass, fluorine-doped silicate glass, and tetraethyl orthosilicate.

The steps of forming the isolation structure 101 include: forming an isolation pattern layer on the substrate 100 ; using the isolation pattern layer as a mask, etching the substrate 100 to form an isolation opening in the substrate 100 ; Fill dielectric material into the isolation opening to form the isolation structure 101 .

It should be noted that, in this embodiment, the semiconductor structure is a planar transistor, so the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor; correspondingly, the substrate has discrete fins. The isolation structure is located on the substrate exposed by the fins. The top surface of the isolation structure is lower than the top surface of the fin and covers the surface of the side wall of the fin portion.

With continued reference to FIG. 4 , gate structures 112 on the substrate 100 between adjacent isolation structures 101 are formed.

The gate structure 112 is used to control the turn-on and turn-off of the channel in the formed semiconductor structure. In this embodiment, the gate structure 112 is the gate structure of the formed semiconductor structure. In other embodiments of the present invention, the gate structure may also be a dummy gate structure in a "gate last process", which is used to occupy a space for a gate to be formed subsequently.

It should be noted that, in this embodiment, the forming method further includes: in the process of forming the gate structure 112 , forming a dummy gate structure 111 on the isolation structure 101 . In this embodiment, the gate structure 112 and the dummy gate structure 111 have the same structure, including a gate layer and spacers located on the sidewalls of the gate layer.

The gate layer may have a single-layer structure or a stacked-layer structure. The gate layer includes an electrode layer; or the gate layer includes a gate dielectric layer on the substrate and an electrode layer on the gate dielectric layer. Wherein, the material of the electrode layer is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the material of the gate dielectric layer is silicon oxide or Silicon oxynitride. The sidewalls may be of a single-layer structure or a laminated structure. The material of the sidewall can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or carbonitride. The structure 112 and the dummy gate structure 111 are both composed of an electrode layer of polysilicon, a gate dielectric layer of silicon oxide, and a spacer of silicon nitride.

The gate structure 112 and the dummy gate structure 111 may be formed simultaneously. Specifically, the steps of forming the gate structure 112 and the dummy gate structure 111 include: forming a gate material layer on the substrate 100; forming a gate pattern layer on the gate material layer; The gate pattern layer is a mask, the gate material layer is etched, and part of the gate material layer on the substrate 100 is removed to form a gate layer; the sidewalls covering the substrate 100 and the gate layer are formed material layer; removing the spacer material layer on the substrate 100 and the gate layer to form the spacer.

In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor; correspondingly, in the step of forming the gate structure, the gate structure spans the fin and covers the top and the top of the fin. part of the surface of the side wall.

Referring to FIG. 4 and FIG. 5 in combination, stress layers 130 are formed in the substrate 100 on both sides of the gate structure 112 .

The stressor layer 130 is used to form the source region or the drain region of the transistor.

Specifically, the semiconductor structure is a P-type transistor, so the material of the stressor layer 130 is silicon germanium. In this embodiment, the step of forming the stressing layer 130 includes: forming the stressing layer 130 in a “Σ” shape, so that the stressing layer 130 has a protruding tip pointing to the channel region, which introduces greater stress to the channel region .

The step of forming the stress layer 130 includes: as shown in FIG. 4 , etching the substrate 100 on both sides of the gate structure 112 , and forming openings 120 in the substrate 100 on both sides of the gate structure 112 ; As shown in FIG. 5 , the stress material is filled into the opening 120 to form the stress layer 130 .

The opening 120 is used to provide a process space for the formation of the stress layer.

Since the formed stress layer 130 is in a "Σ" shape, the shape of the opening 120 is a "Σ" shape. In this embodiment, the material of the substrate 100 is silicon, so the bottom of the opening 120 is a (100) plane, and the sidewall of the opening 120 is a (111) plane.

In this embodiment, the first openings 121 are located between adjacent gate structures 112 . The first opening 121 is located in the substrate 100 , that is, surrounded by the substrate 100 ; the opening 120 located between the gate structure 112 and the dummy gate structure 111 is the second opening 122 . The second opening 122 is adjacent to the isolation structure 101 , that is, the second opening 122 is surrounded by the substrate 100 and the isolation structure 101 .

The step of filling the stress material is used to form the stress layer 130 .

Specifically, the step of filling the opening 120 with the stress material includes: filling the opening 120 with the stress material by means of epitaxial growth to form the stress layer 130 . Since the material of the stressor layer 130 is SiGe material, the stress material is SiGe material.

In this embodiment, the stress layer 130 located in the first opening 121 (as shown in FIG. 4 ) is the first stress layer 131 ; the stress layer 130 located in the second opening 122 (as shown in FIG. 4 ) is the second stress layer Layer 132.

Since the bottom of the opening 120 is the (100) plane and the side wall of the opening 120 is the (111) plane, the stress layer 130 is formed on the side wall of the opening 120 during the process of filling the stress material by epitaxial growth. The growth rate of the stress layer 130 is lower than the growth rate of the stress layer 130 at the bottom of the opening 120 . In addition, the growth rate of the stress layer 130 on the surface of the isolation structure 101 is lower than the growth rate of the stress layer 130 on the surface of the substrate 100 .

Therefore, the growth rates on both sides of the first stress layer 131 are similar, so the first stress layer 131 can completely fill the first opening 121, that is, the surface morphology of the first stress layer 131 is better; the The growth rate of the second stress layer 132 near the isolation structure 101 is slow, so the second stress layer 132 cannot completely fill the second opening 132, and defects appear on the side near the isolation structure 101 (as shown in FIG. 5 ). shown in the middle circle 133 ), the shape of the second stress layer 132 is not good.

It should be noted that, in this embodiment, the forming method further includes: performing ion doping on the stressor layer 130 to form a source-drain doped region. Specifically, the step of performing ion doping on the stressor layer 130 may be performed by in-situ self-doping during the process of forming the stressor layer 130 ; or by performing ion implantation on the stressor layer 130 after the stressor layer 130 is formed. In this embodiment, the semiconductor structure is a P-type transistor, so the doping ions are P-type ions, such as B, Ga, or In.

Referring to FIGS. 6 to 9 , a cap layer 140 is formed on the stressor layer 130 , and the step of forming the cap layer 140 includes a spin coating process.

The cap layer 140 is used for subsequent reaction with metal to form metal silicide to reduce the contact resistance of the stress layer. In addition, the cap layer 140 is also used to repair the topographical defects of the stressor layer 130 to improve the performance of the formed semiconductor structure.

Since the process of forming the cap layer includes a spin coating process. Since the spin coating process uses centrifugal force to distribute the glue evenly on the high-speed rotating substrate, the shape of the formed cap layer 140 will not change with the change of the shape of the stress layer 130, and the gate structure 112 The plurality of cap layers 140 in between have flush surfaces, so the formed cap layers 140 can better repair the topography of the stress layer 130, thereby helping to improve the surface topography of the formed cap layers 140, It is beneficial to improve the electrical properties of the formed semiconductor structure.

Specifically, the step of forming the cap layer 140 on the stress layer 130 includes:

As shown in FIG. 6 and FIG. 7 , a precursor layer 141 is formed on the stressor layer 130 through a spin coating process.

The precursor layer 141 is used to form the cap layer.

Specifically, in the step of forming the precursor layer 141 on the stressor layer 130 by a spin coating process, the precursor layer 141 is a polysilane layer. In this embodiment, the material of the precursor layer 141 includes one or both of polydihydrosilance and cyclopentasilan.

In addition, in the step of forming the precursor layer 141 on the stressor layer 130 by a spin coating process, the precursor layer 141 further includes a solvent, the solvent is a hydrocarbon, and the number of carbon atoms in the hydrocarbon is Greater than ₄ , such as _C5H12 .

Therefore, polydihydrosilance or cyclopentasilan forms silicon-containing precursors with hydrocarbon solvents. The silicon-containing precursor material has a certain fluidity; the silicon-containing precursor material with fluidity is coated on the stress layer 130 by a spin coating process to form the precursor layer 141 .

It should be noted that, in order to promote the precipitation of gas in the precursor layer 141, reduce the formation of bubbles in the precursor layer 141, and improve the quality of the formed precursor layer 141, in this embodiment, a spin coating process is used on the stress layer. The step of forming the precursor layer includes: performing a spin coating process in a low pressure environment filled with an inert gas. Specifically, the spin coating process is performed in one or more gases of N ₂ , He, Ne or Ar.

If the pressure of the inert gas is too high, it is not conducive to the precipitation of gas in the formed precursor layer 141, and is not conducive to reducing the formation of bubbles in the precursor layer 141; if the pressure of the inert gas is too low, it will cause energy waste, increase Process difficulty. In this embodiment, the pressure range of the inert gas is in the range of 200 Torr to 500 Torr.

After the precursor layer 141 is formed, referring to FIGS. 8 and 9 , the precursor layer 141 (as shown in FIG. 7 ) is cured to form the cap layer 140 .

It should be noted that, in this embodiment, in order to completely fill the formed precursor layer 141 between adjacent gate structures 112 , the precursor layer 141 covers the gate structures 112 . Therefore, after the precursor layer 141 is formed and before the curing process is performed, the formation method further includes: removing a part of the thickness of the precursor layer 141 by etching back.

The step of etching back the precursor layer 141 is used to remove part of the material of the precursor layer 141 , so that the formed precursor layer 141 reaches a target thickness and exposes the gate structure 112 and the dummy gate structure 111 . Specifically, the step of etching back the precursor layer 141 includes etching back the precursor layer 141 by dry etching.

The curing treatment is used to remove the solvent and other substances in the precursor layer 141 , so as to cure the precursor layer 141 and improve the lattice quality of the cap layer 140 .

Specifically, the step of curing the precursor layer 141 includes: performing a baking treatment 151 on the precursor layer 141; and performing an annealing treatment 152 on the baked precursor layer 141 (as shown in FIG. The cap layer 140 is described.

The baking process 151 is used for removing the solvent in the precursor layer 141 , increasing the hardness of the precursor layer 141 , and preliminarily curing the precursor layer 141 .

The temperature of the baking process 151 should neither be too high nor too low.

If the baking temperature is too low, it is not conducive to the removal of the solvent in the precursor layer 141, and it is not conducive to the preliminary curing of the precursor layer 141, and solvent residues will be formed in the precursor layer 141, which will affect the quality of the formed cap layer 140 and affect the subsequent The reaction between the cap layer 140 and the metal layer; if the baking temperature is too high, unnecessary process risks may be caused, the stress layer 130 may be damaged, and other semiconductor structures on the substrate 100 may be affected. In this embodiment, in the step of performing the baking process 151 on the precursor layer 141, the temperature of the baking process 151 is in the range of 150°C to 350°C.

The time of the baking process 151 should not be too long nor too short.

If the time of the baking treatment 151 is too short, it is not conducive to the removal of the solvent in the precursor layer 141 and the preliminary curing of the precursor layer 141, and solvent residues will be formed in the precursor layer 141, which will affect the quality of the formed cap layer 140. , affecting the reaction between the subsequent cap layer 140 and the metal layer; if the baking process 151 takes too long, unnecessary process risks may be caused, the stress layer 130 may be damaged, and the substrate may also be affected Other semiconductor structures on the 100, and the baking process 151 for a long time will also cause the process time to be too long and affect the production efficiency. In this embodiment, in the step of performing the baking process 151 on the precursor layer 141, the time of the baking process 151 is in the range of 5 minutes to 15 minutes.

It should be noted that, the temperature and time of the baking process 151 are matched with each other to remove the solvent in the precursor layer 141 and preliminarily solidify the precursor layer 141 . Within a reasonable range, the temperature and time of the baking process 151 are set so as to balance the efficiency and effect of the baking process 151 with each other.

The annealing treatment 152 is used to solidify the precursor layer 141 to form the cap layer 140 , and to increase the order of atomic arrangement in the cap layer 140 , thereby improving the quality of the formed cap layer 140 .

The temperature of the annealing treatment 152 should neither be too high nor too low.

If the annealing temperature is too low, it will be unfavorable for the curing of the precursor layer 141 and the increase in the order of the atomic arrangement in the cap layer 140 , which will affect the quality of the formed cap layer 140 and affect the cap layer 140 Reaction with the subsequently formed metal layer; if the annealing temperature is too high, unnecessary process risks may be caused, the stress layer 130 may be damaged, and other semiconductor structures on the substrate 100 may be affected. . In this embodiment, in the step of performing the annealing treatment 152 on the precursor layer 141 subjected to the baking treatment 151, the temperature of the annealing treatment 152 is in the range of 350°C to 800°C.

The time of the annealing treatment 152 should neither be too long nor too short.

If the time of the annealing treatment 152 is too short, it is not conducive to the curing of the precursor layer 141 , and it is not conducive to the increase of the order of the atomic arrangement in the cap layer 140 , which will affect the quality of the formed cap layer 140 and affect the cap layer 140 . The reaction between the layer 140 and the subsequently formed metal layer; if the time of the annealing treatment 152 is too long, unnecessary process risks may be caused, the stress layer 130 may be damaged, and the substrate 100 may be affected. other semiconductor structures, and the annealing treatment 152 for too long will also cause the process time to be too long and affect the production efficiency. In this embodiment, in the step of performing the annealing treatment 152 on the precursor layer 141 subjected to the baking treatment 151, the time of the annealing treatment 152 is in the range of 2 minutes to 8 minutes.

It should be noted that, the temperature and time of the annealing treatment 152 are matched to each other, so that the solvent in the precursor layer 141 is removed, and the precursor layer 141 is cured to form the cap layer 140 . Within a reasonable range, the temperature and time of the annealing treatment 152 are set so as to balance the efficiency and effect of the annealing treatment 152 with each other.

It should be noted that, in order to improve the quality of the formed cap layer 140 and reduce the formation of holes in the cap layer 140, in this embodiment, the step of curing the precursor layer 141 includes: in a low pressure filled with an inert gas The curing process is performed in an environment, that is, the baking process 151 and the annealing process 152 are both performed in a low-pressure environment filled with an inert gas.

Specifically, the baking process 151 and the annealing process 152 are performed in one or more gases of N ₂ , He, Ne or Ar. During the baking process 151 and the annealing process 152 , the polydisilane or cyclopentasilane reacts to form the cap layer 140 . By-products of the reaction, such as _O2 or _H2 , are removed by purging with an inert gas.

If the pressure of the inert gas is too high, it is not conducive to the precipitation of the gas in the formed cap layer 140, and is not conducive to reducing the formation of holes in the cap layer 140; if the pressure of the inert gas is too low, it will cause energy waste. , Increase the difficulty of the process. In this embodiment, the pressure range of the inert gas is in the range of 200 Torr to 500 Torr.

It should be noted that, in this embodiment, after the cap layer 140 is formed, the forming method further includes: forming a metal layer covering the cap layer 140 . Specifically, the metal layer includes nickel. The metal layer reacts with the cap layer 140 to form metal silicide for reducing the contact resistance of the stressor layer 130 .

Since the cap layer 140 is formed by a spin coating process, the shape of the cap layer 140 will not change with the change of the shape of the stress layer 130 , and the cap layer 140 can repair the second stress Therefore, the surface flatness of the cap layer 140 on the second stress layer 132 and the cap layer 140 on the first stress layer 132 is relatively high, thereby effectively reducing the damage to the cap layer 140 in the subsequent process. It is beneficial to the formation of the subsequent metal silicide, and is beneficial to improve the performance of the formed semiconductor structure.

Correspondingly, the present invention also provides a semiconductor structure.

Referring to FIG. 9 , a schematic cross-sectional structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes:

The substrate 100 has a plurality of isolation structures 101 in the substrate 100 ; gate structures 112 located on the substrate 100 between adjacent isolation structures 101 ; stress layers 130 located in the substrate 100 on both sides of the gate structure 112 ; The cap layer 140 located on the stress layer 130, the cap layer 140 is a cap layer formed by a spin coating process.

The substrate 100 is used to provide a process operating platform.

In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the material of the substrate can also be selected from polysilicon or amorphous silicon; the substrate can also be selected from silicon, germanium, gallium arsenide or silicon-germanium compounds; the substrate also Other semiconductor materials may be used, or the substrate may also be selected from having an epitaxial layer or a silicon-on-epitaxial layer structure.

The isolation structure 101 is used to electrically isolate adjacent active areas (Active Area, AA).

The material of the isolation structure 101 is silicon oxide. In other embodiments of the present invention, the material of the isolation structure 101 may also be other insulating materials such as fluorosilicate glass, fluorine-doped silicate glass, and tetraethyl orthosilicate.

It should be noted that, in this embodiment, the semiconductor structure is a planar transistor, so the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor; correspondingly, the substrate has discrete fins. The isolation structure is located on the substrate exposed by the fins. The top surface of the isolation structure is lower than the top surface of the fin and covers the surface of the side wall of the fin portion.

The gate structure 112 is used to control the turn-on and turn-off of the channel in the semiconductor structure.

In this embodiment, the gate structure 112 is the gate structure of the semiconductor structure. In other embodiments of the present invention, the gate structure may also be a dummy gate structure in a "gate last process" for occupying a space for the gate of the semiconductor structure.

It should be noted that, the semiconductor structure further includes: a dummy gate structure 111 located on the isolation structure 101 . In this embodiment, the gate structure 112 and the dummy gate structure 111 have the same structure, including a gate layer and spacers located on the sidewalls of the gate layer.

The gate layer may have a single-layer structure or a stacked-layer structure. The gate layer includes an electrode layer; or the gate layer includes a gate dielectric layer on the substrate and an electrode layer on the gate dielectric layer. Wherein, the material of the electrode layer is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the material of the gate dielectric layer is silicon oxide or Silicon oxynitride. The sidewalls may be of a single-layer structure or a laminated structure. The material of the sidewall can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or carbonitride. The structure 112 and the dummy gate structure 111 are both composed of an electrode layer of polysilicon, a gate dielectric layer of silicon oxide, and a spacer of silicon nitride.

In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor; correspondingly, the gate structure spans the fin and covers part of the top and sidewalls of the fin.

The stressor layer 130 is used to form the source region or the drain region of the transistor.

Specifically, the semiconductor structure is a P-type transistor, so the material of the stressor layer 130 is silicon germanium. In this embodiment, the stressor layer 130 is a "Σ"-shaped stressor layer, so that the stressor layer 130 has a protruding tip pointing to the channel region, which induces greater stress to the channel region.

The stressor layer 130 includes a first stressor layer 131 between adjacent gate structures 112 and a second stressor layer 132 between the gate structures 112 and the dummy gate structures 111 . Since the second stress layer 132 is located on the gate structure 112 and the dummy gate structure 111 , and the dummy gate structure 111 is located on the isolation structure 101 , the second stress layer 132 is adjacent to the isolation structure 101 . Since the material of the substrate 100 is different from the material of the isolation structure 101 , the growth rate of the second stress layer 132 on the surface adjacent to the substrate 100 is the same as that of the second stress layer 132 The growth rate is different on the surface adjacent to the isolation structure 101 . Specifically, the growth rate of the second stress layer 132 on the surface adjacent to the isolation structure 101 is relatively low, so the second stress layer 132 cannot completely fill the second opening 132, and the second stress layer 132 cannot completely fill the second opening 132. Defects occur on one side of the isolation structure 101, resulting in poor morphology.

It should be noted that the stressor layer 130 has doping ions to form source and drain doped regions. In this embodiment, the semiconductor structure is a P-type transistor, so the doping ions in the stressor layer 130 are P-type ions, such as B, Ga, or In.

The cap layer 140 is used for subsequent reaction with metal to form metal silicide to reduce the contact resistance of the stressor layer 130 . In addition, the cap layer 140 is also used to repair the topographical defects of the stressor layer 130 to improve the performance of the semiconductor structure.

Since the cap layer is a cap layer formed by a spin coating process, and the spin coating process uses centrifugal force to uniformly distribute the glue on the high-speed rotating substrate, the topography of the cap layer 140 will not follow any The topography of the stressor layer 130 varies depending on the topography of the stressor layer 130 , and the plurality of capping layers 140 between the gate structures 112 have flush surfaces, so the capping layers 140 can better repair the topography of the stressor layer 130 . , so as to improve the surface topography of the cap layer 140 and improve the electrical properties of the semiconductor structure.

In addition, since the cap layer 140 is also used for the subsequent reaction with metal to form metal silicide to reduce the contact resistance of the stressor layer 130 , the material of the cap layer 140 includes silicon.

It should be noted that, in other embodiments of the present invention, the semiconductor structure further includes: a metal layer covering the cap layer 140 . Specifically, the material of the metal layer includes nickel.

To sum up, according to the technical solution of the present invention, after the stress layer is formed, a cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process. Since the process of forming the capping layer includes a spin coating process, the topography of the formed capping layer will not change with the change of the topography of the stressing layer, and the plurality of capping layers between the gate structures have a flush level Therefore, the formed cap layer can better repair the morphology of the stress layer, thereby improving the surface morphology of the formed cap layer and improving the electrical properties of the formed semiconductor structure. Furthermore, in an optional solution of the present invention, after the cap layer of the polysilane material is formed, a metal layer covering the cap layer is formed to form a metal silicide to reduce contact resistance. Compared with the technical solution of forming the repair layer, the technical solution of the present invention directly realizes the repair of the stress layer morphology through the cap layer, which simplifies the process steps, is beneficial to reduce the process difficulty and improve the yield.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (19)

1. A method for forming a semiconductor structure, comprising: providing a substrate having a plurality of isolation structures therein; forming gate structures on the substrate between adjacent isolation structures; forming a stress layer in the substrate on both sides of the gate structure; forming a cap layer on the stress layer, and the process of forming the cap layer includes a spin coating process; A metal layer is formed overlying the capping layer. 2. The forming method of claim 1, wherein the step of forming a cap layer on the stress layer comprises: forming a precursor layer on the stress layer by a spin coating process; The precursor layer is cured to form the cap layer. 3 . The method of claim 2 , wherein in the step of forming a precursor layer on the stressor layer by a spin coating process, the precursor layer is a polysilane layer. 4 . 4. The formation method according to claim 2 or 3, wherein in the step of forming a precursor layer on the stress layer by a spin coating process, the material of the precursor layer comprises polydisilane and cyclopentasilane of one or both. 5. The formation method according to claim 2, wherein in the step of forming a precursor layer on the stress layer by a spin coating process, the precursor layer further comprises a solvent, and the solvent is a hydrocarbon, so The number of carbon atoms in the hydrocarbon compound is greater than 4. 6 . The method of claim 5 , wherein in the step of forming a precursor layer on the stressor layer by a spin coating process, the hydrocarbon is C ₅ H ₁₂ . 7 . 7 . The forming method according to claim 2 , wherein, after forming the precursor layer and before the curing treatment, the forming method further comprises: removing a part of the thickness of the precursor layer by etching back. 8 . 8. The method of claim 7, wherein the step of etching back the precursor layer comprises: etching back the precursor layer by dry etching. 9. The method of claim 2, wherein the step of curing the precursor layer comprises: Baking the precursor layer; The baked precursor layer is annealed to form the cap layer. 10. The forming method according to claim 9, wherein in the step of baking the precursor layer, the temperature of the baking treatment is in the range of 150°C to 350°C, and the time of the baking treatment is in the range of 150°C to 350°C. 5 minutes to 15 minutes range. 11. The method of claim 9, wherein in the step of annealing the baked precursor layer, the temperature of the annealing is in the range of 350°C to 800°C, and the temperature of the annealing is in the range of 350°C to 800°C. The time is in the range of 2 minutes to 8 minutes. 12. The method of claim 2, wherein one or both of the steps of forming a precursor layer on the stressor layer by a spin coating process and curing the precursor layer include: : The spin coating process or the curing treatment is performed in an inert gas atmosphere, and the pressure of the inert gas is in the range of 200 Torr to 500 Torr. 13. The method of claim 1, wherein the step of forming the stress layer comprises: forming openings in the substrate on both sides of the gate structure; A stress material is filled into the opening to form the stress layer. 14. The method of claim 1 or 13, wherein the step of forming the stress layer comprises: forming a "Σ"-shaped stress layer. 15 . The forming method according to claim 1 or 13 , wherein the step of forming the stress layer comprises: the material of the stress layer is silicon germanium material. 16 . 16. The method of claim 13, wherein the step of filling the opening with a stress material comprises: filling the opening with a stress material by means of epitaxial growth. 17. The method of claim 1, wherein in the step of forming the metal layer, the material of the metal layer is nickel. 18. A semiconductor structure formed by the forming method of any one of claims 1 to 17, characterized by comprising: a substrate having a plurality of isolation structures in the substrate; a gate structure on the substrate between adjacent isolation structures; stress layers in the substrate on both sides of the gate structure; A cap layer on the stress layer, the cap layer is a cap layer formed by a spin coating process. 19. The semiconductor structure of claim 18, wherein the material of the cap layer comprises silicon.

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