CN108074787A - Lower electrode arrangement and semiconductor processing equipment - Google Patents
Lower electrode arrangement and semiconductor processing equipment Download PDFInfo
- Publication number
- CN108074787A CN108074787A CN201610991863.9A CN201610991863A CN108074787A CN 108074787 A CN108074787 A CN 108074787A CN 201610991863 A CN201610991863 A CN 201610991863A CN 108074787 A CN108074787 A CN 108074787A
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- China
- Prior art keywords
- lower electrode
- electrode arrangement
- electrode
- medium ring
- slide holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32568—Relative arrangement or disposition of electrodes; moving means
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of lower electrode arrangement and semiconductor processing equipment, and including the slide holder for bearing wafer, first electrode is provided in slide holder, by the way that the first bias of first electrode loading, back bias voltage is formed in the upper surface of chip；Also, media set is surrounded on the periphery wall of slide holder, to the periphery wall of barrier plasma contact slide holder and the position of restriction chip.Lower electrode arrangement further includes second electrode, which is arranged in media set, by the way that the second bias of second electrode loading, the second back bias voltage is formed in the upper surface of media set.Lower electrode arrangement provided by the invention can adjust electric field strength and the direction of wafer edge, distort so as to eliminate the technique pattern caused by edge effect, and then can improve wafer yield.
Description
Technical field
The present invention relates to semiconductor processing technology fields, and in particular, to a kind of lower electrode arrangement and semiconductor machining are set
It is standby.
Background technology
It is higher and higher to component performance and integrated level requirement with the rapid development of semiconductor components and devices manufacturing process,
So that plasma technique has obtained a very wide range of application.A kind of current plasma processing device includes reaction chamber,
Top is provided with upper electrode arrangement using medium window (quartz or ceramics) sealing at the top of the medium window, and upper electrode arrangement is led to
Often include radio-frequency coil (such as planar coil).RF energy is by radio-frequency coil, in the form of induction discharge, coupled to reaction
In chamber, and generate high-density plasma.Plasma from top to bottom diffuses to wafer surface, carries out specific technique mistake
Journey.
Moreover, lower electrode arrangement is provided in reaction chamber, as shown in Figure 1, the section view for current lower electrode arrangement
Figure.Lower electrode arrangement includes the slide holder 2 for bearing wafer 1, radio-frequency electrode 3 is provided in slide holder 2, the radio-frequency electrode
3 are electrically connected with radio frequency source 4, and radio frequency source 4 is used to load rf bias to radio-frequency electrode 3, to form negative bias in the upper surface of chip 1
Pressure, so as to play the role of control bombardment to the ion energy of wafer surface.It is set in addition, being surround on the periphery wall of slide holder 2
First medium ring 5 is equipped with, to the periphery wall of barrier plasma contact slide holder 2, so as to which radio-frequency electrode 3 is avoided to pass through
(chamber wall) discharges plasma over the ground.Second medium ring 6 is additionally provided on first medium ring 5, is close to the edge of chip 1
It sets, to limit the position of chip 1.
During technique is carried out, as illustrated by the arrows in fig. 1, for the central region of chip 1, direction of an electric field is opposite
In wafer surface vertically downward, under the action of the electric field, the ion in plasma can be vertically bombarded to wafer surface.So
And for the fringe region of chip 1, since wafer edge has tip, electric field will generate distortion, and direction is no longer normal to crystalline substance
Piece surface, but it is less than 90 ° of angle with wafer surface formation, this will cause ion bombardment direction to generate inclination, i.e. " edge
Effect ".In semiconductor etching field, especially in advanced package technologies, there is high requirement to the angle of etched hole, it is above-mentioned
" edge effect " is unable to reach technological requirement, so as to affect wafer yield.
The content of the invention
It is contemplated that at least solve one of technical problem in the prior art, it is proposed that a kind of lower electrode arrangement and
Semiconductor processing equipment can adjust electric field strength and the direction of wafer edge, so as to eliminate because edge effect is led
The technique pattern distortion of cause, and then wafer yield can be improved.
Purpose to realize the present invention and a kind of lower electrode arrangement is provided, the slide holder including being used for bearing wafer, in institute
It states and first electrode is provided in slide holder, by being biased to first electrode loading first, in the upper surface shape of the chip
Into back bias voltage；Also, media set is surrounded on the periphery wall of the slide holder, institute is contacted to barrier plasma
It states the periphery wall of slide holder and limits the position of the chip, further include second electrode, the second electrode is arranged on described
In media set, by the way that the second bias of second electrode loading, the second negative bias is formed in the upper surface of the media set
Pressure.
Preferably, bias generator is further included, for being biased to second electrode loading second；By adjusting the bias generator
The voltage swing of output and direction adjust the size and Orientation of second back bias voltage.
Preferably, second back bias voltage is equal to first back bias voltage.
Preferably, second back bias voltage is more than first back bias voltage.
Preferably, the bias generator includes DC power supply or AC power.
Preferably, the media set includes first medium ring and the second medium ring that is disposed thereon, wherein, described the
One dielectric ring contacts the periphery wall of the slide holder for barrier plasma；The second medium ring is used to limit the chip
Position.
Preferably, the second electrode is arranged in the second medium ring；Alternatively, the second electrode be arranged on it is described
In first medium ring；Alternatively, the second electrode is two, and it is separately positioned on the first medium ring and the second medium
In ring.
Preferably, second electrode tabular in a ring.
Preferably, the difference of the width and the width of the second electrode of the second medium ring is less than or equal to
10mm。
Preferably, the thickness of the second electrode is 1~2mm.
Preferably, the second electrode is two, and is separately positioned on the first medium ring and the second medium ring
In；The bias generator is two, and is electrically connected respectively with two second electrodes；Alternatively, the bias generator is one, and it is same
When be electrically connected with two second electrodes.
The present invention also provides a kind of semiconductor processing equipment, including reaction chamber, under being provided in the reaction chamber
Electrode structure to support chip, and controls the upper surface of chip described in plasma bombardment, and the lower electrode arrangement is using this
The lower electrode arrangement of above-mentioned offer is provided.
The invention has the advantages that：
Lower electrode arrangement provided by the invention, is provided with second electrode in media set, by adding to second electrode
The second bias is carried, the second back bias voltage is formed in the upper surface of media set, so as to can not only pass through the big of the second bias of adjusting
Small and direction to adjust the electric field strength of wafer edge and direction, is distorted with eliminating the technique pattern caused by edge effect,
Wafer yield is improved, but also some expected process results can be completed according to demand.
Semiconductor processing equipment provided by the invention, by using above-mentioned lower electrode arrangement provided by the invention, not only
It can be by adjusting the second size and Orientation biased, to adjust the electric field strength of wafer edge and direction, to eliminate because of side
Technique pattern caused by edge effect distorts, and improves wafer yield, but also can complete some expected technique knots according to demand
Fruit.
Description of the drawings
Fig. 1 is the sectional view of current lower electrode arrangement；
Fig. 2 is the sectional view of lower electrode arrangement provided in an embodiment of the present invention；
Fig. 3 is the partial sectional view of lower electrode arrangement provided in an embodiment of the present invention；
Fig. 4 is the partial enlarged view of lower electrode arrangement provided in an embodiment of the present invention.
Specific embodiment
For those skilled in the art is made to more fully understand technical scheme, come below in conjunction with the accompanying drawings to the present invention
The lower electrode arrangement and semiconductor processing equipment of offer are described in detail.
Fig. 2 is the sectional view of lower electrode arrangement provided in an embodiment of the present invention.Fig. 3 is lower electricity provided in an embodiment of the present invention
The partial sectional view of pole structure.Fig. 4 is the partial enlarged view of lower electrode arrangement provided in an embodiment of the present invention.Also referring to figure
2~Fig. 4, lower electrode arrangement include the slide holder 12 for bearing wafer 10, first electrode 13 are provided in slide holder 12, lead to
It crosses to first bias of the loading of first electrode 13, back bias voltage is formed in the upper surface of chip 10.First electrode 13 and 14 electricity of radio frequency source
Connection, radio frequency source 14 is used to load rf bias to first electrode 13, to form back bias voltage in the upper surface of chip 10, so as to rise
To control bombardment to the effect of the ion energy of wafer surface.
Also, media set is surrounded on the periphery wall of slide holder 12, slide glass is contacted to barrier plasma
The periphery wall of platform 12 and the position for limiting chip 10.Specifically, media set includes first medium ring 15 and is disposed thereon
Second medium ring 16, wherein, boss is provided on slide holder 12, first medium ring 15 is looped around the periphery wall of the boss
On, and the internal ring wall of first medium ring 15 is close to the periphery wall of boss, with the barrier plasma contact slide holder 12 in technique
Periphery wall, so as to avoid first electrode 13 pass through plasma over the ground (chamber wall) discharge.Second medium ring 16 is used for
Limit the position of chip 10.The insulation of ceramics or quartz etc. may be employed in above-mentioned first medium ring 15 and second medium ring 16
Material makes.
Upper electrode arrangement further includes second electrode 11, which is arranged on the second medium ring of above-mentioned media set
In 16, by the way that second bias of the loading of second electrode 11, the second back bias voltage is formed in the upper surface of second medium ring 16.Pass through tune
The size and Orientation of second bias is saved, can not only adjust electric field strength and the direction of wafer edge, to eliminate because of edge
Technique pattern caused by effect distorts, and improves wafer yield, but also can complete some expected process results according to demand.
In the present embodiment, lower electrode arrangement further includes bias generator 17, for being biased to the loading of second electrode 11 second.Partially
Potential source 17 can include DC power supply or AC power.By adjusting voltage swing and the direction that bias generator 17 exports, adjust
The size and Orientation of second back bias voltage.Preferably, the second back bias voltage is equal to the first back bias voltage, as shown in figure 3, carrying out technique
When, it is biased by bias generator 17 to the loading of second electrode 11 second, negative electrical charge can be accumulated in the upper surface of second medium ring 16,
So as to form back bias voltage, the back bias voltage is equal with the back bias voltage that the upper surface of chip 10 is formed, and forms equipotential surface, and then eliminates
Electric field distortion makes the electric field above Waffer edge be distributed vertically downward, abnormal so as to eliminate the technique pattern caused by edge effect
Become.
Alternatively, in order to complete some expected processing purposes, the voltage swing that can also be exported by adjusting bias generator 17
And direction, the upper surface of second medium ring 16 is made to generate second back bias voltage in arbitrary size and direction, for example, making the second back bias voltage
More than the first back bias voltage, this can attract the part plasma above Waffer edge when the processing speed of Waffer edge is too fast
Body bombardment second medium ring 16, to reduce the plasma quantity that should bombard Waffer edge, so as to reduce Waffer edge
Processing speed, be allowed to reach unanimity with the processing speed of center wafer, and then processing uniformity can be improved.If for example,
One back bias voltage is 200V, then the second back bias voltage can be 250~300V, and the direction one of the second back bias voltage and the first back bias voltage
It causes.
In the present embodiment, as shown in figure 4, second electrode 11 tabular, the structure can make to be accumulated in second in a ring
The negative electrical charge of the upper surface of dielectric ring 16 is more evenly distributed.In practical applications, in order to achieve the purpose that improve edge effect, the
The width D 2 of two electrodes 11 should reach unanimity with the width D of second medium ring 16 1 as much as possible, it is preferred that in view of difficult processing
Degree, the width D 1 of second medium ring 16 and the difference of the width D 2 of second electrode 11 are less than or equal to 10mm.Second electrode 11
Thickness can be 1~2mm.
In practical applications, the mode that may be employed in the surface of second electrode 11 progress dielectric deposition makes second electrode 11
Naturally it is built in second medium ring 16.Furthermore, it is possible to it sets in second medium ring 16 using modes such as mechanical tappings
Line passage, one end of transmission cable are connected by the cable tray with second electrode 11, and the other end is by being opened in second medium
Perforate on the periphery wall of ring 16 is drawn, and is connected with bias generator 17.
It should be noted that in the present embodiment, second electrode 11 is arranged in second medium ring 16.It is but of the invention
It is not limited thereto, in practical applications, second electrode can also be arranged in first medium ring 15.
Alternatively, second electrode is two, and it is separately positioned in first medium ring 15 and second medium ring 16.In this feelings
Under condition, bias generator is two, and is electrically connected respectively with two second electrodes；Alternatively, bias generator is one, and simultaneously with two the
Two electrodes are electrically connected.
It is anti-at this including reaction chamber the present invention also provides a kind of semiconductor processing equipment as another technical solution
It answers and lower electrode arrangement is provided in chamber, to support chip, and control the upper surface of plasma bombardment chip.Lower electrode knot
Structure employs above-mentioned lower electrode arrangement provided in an embodiment of the present invention.
Semiconductor processing equipment provided in an embodiment of the present invention, by using above-mentioned lower electricity provided in an embodiment of the present invention
Pole structure, the size and Orientation that can be not only biased by adjusting second, to adjust the electric field strength of wafer edge and direction,
It is distorted with eliminating the technique pattern caused by edge effect, improves wafer yield, but also can complete according to demand some pre-
The process results of phase.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, the essence of the present invention is not being departed from
In the case of refreshing and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (12)
1. a kind of lower electrode arrangement, the slide holder including being used for bearing wafer, first electrode is provided in the slide holder, lead to
It crosses to the first bias of first electrode loading, back bias voltage is formed in the upper surface of the chip；Also, in the slide holder
Media set is surrounded on periphery wall, the periphery wall of the slide holder is contacted to barrier plasma and limits institute
State the position of chip, which is characterized in that further include second electrode, the second electrode is arranged in the media set, passes through
To the second bias of second electrode loading, the second back bias voltage is formed in the upper surface of the media set.
2. lower electrode arrangement according to claim 1, which is characterized in that bias generator is further included, for electric to described second
The second bias of pole loading；
By adjusting voltage swing and the direction that the bias generator exports, the size and Orientation of second back bias voltage is adjusted.
3. lower electrode arrangement according to claim 2, which is characterized in that second back bias voltage is equal to first negative bias
Pressure.
4. bottom electrode mechanism according to claim 2, which is characterized in that second back bias voltage is more than first negative bias
Pressure.
5. lower electrode arrangement according to claim 2, which is characterized in that the bias generator includes DC power supply or exchange
Power supply.
6. according to the lower electrode arrangement described in claim 2-5 any one, which is characterized in that the media set includes first
Dielectric ring and the second medium ring being disposed thereon, wherein,
The first medium ring contacts the periphery wall of the slide holder for barrier plasma；
The second medium ring is used to limit the position of the chip.
7. lower electrode arrangement according to claim 6, which is characterized in that the second electrode is arranged on the second medium
In ring；Alternatively, the second electrode is arranged in the first medium ring；Alternatively, the second electrode is two, and set respectively
It puts in the first medium ring and the second medium ring.
8. lower electrode arrangement according to claim 7, which is characterized in that second electrode tabular in a ring.
9. lower electrode arrangement according to claim 8, which is characterized in that the width of the second medium ring and described second
The difference of the width of electrode is less than or equal to 10mm.
10. lower electrode arrangement according to claim 8, which is characterized in that the thickness of the second electrode is 1~2mm.
11. lower electrode arrangement according to claim 7, which is characterized in that the second electrode is two, and is set respectively
In the first medium ring and the second medium ring；
The bias generator is two, and is electrically connected respectively with two second electrodes；Alternatively, the bias generator is one, and
It is electrically connected simultaneously with two second electrodes.
12. including reaction chamber, lower electrode arrangement is provided in the reaction chamber for a kind of semiconductor processing equipment, to
Chip is supported, and controls the upper surface of chip described in plasma bombardment, which is characterized in that the lower electrode arrangement uses right
It is required that the lower electrode arrangement described in 1-11 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610991863.9A CN108074787A (en) | 2016-11-10 | 2016-11-10 | Lower electrode arrangement and semiconductor processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610991863.9A CN108074787A (en) | 2016-11-10 | 2016-11-10 | Lower electrode arrangement and semiconductor processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108074787A true CN108074787A (en) | 2018-05-25 |
Family
ID=62154655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610991863.9A Pending CN108074787A (en) | 2016-11-10 | 2016-11-10 | Lower electrode arrangement and semiconductor processing equipment |
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| Country | Link |
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| CN (1) | CN108074787A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256316A (en) * | 2018-09-29 | 2019-01-22 | 德淮半导体有限公司 | Plasma etching apparatus and its method for etching plasma |
| CN110880443A (en) * | 2018-09-06 | 2020-03-13 | 株式会社日立高新技术 | Plasma processing device |
| CN113936988A (en) * | 2021-10-12 | 2022-01-14 | 大连理工大学 | An edge plasma distribution adjustment device |
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| CN1521805A (en) * | 2003-02-07 | 2004-08-18 | ���������ƴ���ʽ���� | Plasma processing device, annular element and plasma processing method |
| CN1540738A (en) * | 2003-04-24 | 2004-10-27 | ���������ƴ���ʽ���� | Plasma treatment appts. focusing ring and base |
| KR20080029569A (en) * | 2006-09-29 | 2008-04-03 | 주식회사 하이닉스반도체 | Plasma Etching Device to Prevent Etching Profile |
| CN103227091A (en) * | 2013-04-19 | 2013-07-31 | 中微半导体设备(上海)有限公司 | Plasma processing device |
| CN104217914A (en) * | 2013-05-31 | 2014-12-17 | 中微半导体设备(上海)有限公司 | Plasma processing device |
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Patent Citations (5)
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|---|---|---|---|---|
| CN1521805A (en) * | 2003-02-07 | 2004-08-18 | ���������ƴ���ʽ���� | Plasma processing device, annular element and plasma processing method |
| CN1540738A (en) * | 2003-04-24 | 2004-10-27 | ���������ƴ���ʽ���� | Plasma treatment appts. focusing ring and base |
| KR20080029569A (en) * | 2006-09-29 | 2008-04-03 | 주식회사 하이닉스반도체 | Plasma Etching Device to Prevent Etching Profile |
| CN103227091A (en) * | 2013-04-19 | 2013-07-31 | 中微半导体设备(上海)有限公司 | Plasma processing device |
| CN104217914A (en) * | 2013-05-31 | 2014-12-17 | 中微半导体设备(上海)有限公司 | Plasma processing device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880443A (en) * | 2018-09-06 | 2020-03-13 | 株式会社日立高新技术 | Plasma processing device |
| CN110880443B (en) * | 2018-09-06 | 2022-07-08 | 株式会社日立高新技术 | Plasma processing apparatus |
| CN109256316A (en) * | 2018-09-29 | 2019-01-22 | 德淮半导体有限公司 | Plasma etching apparatus and its method for etching plasma |
| CN113936988A (en) * | 2021-10-12 | 2022-01-14 | 大连理工大学 | An edge plasma distribution adjustment device |
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Application publication date: 20180525 |
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