CN108063117B

CN108063117B - Interconnect structure and method of forming the same

Info

Publication number: CN108063117B
Application number: CN201610986757.1A
Authority: CN
Inventors: 邓浩; 谷勋; 周峰; 杨小军
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-09
Filing date: 2016-11-09
Publication date: 2020-12-01
Anticipated expiration: 2036-11-09
Also published as: CN108063117A

Abstract

An interconnection structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier layer on the bottom and the side wall of the opening, wherein the barrier layer is a Si-doped barrier layer; and filling the opening with the barrier layer formed on the bottom and the side wall with a conductive material to form an interconnection structure. In the technical scheme of the invention, the barrier layers are formed on the bottom and the side wall of the opening and are Si-doped barrier layers; and forming an interconnection structure in the opening in which the barrier layer is formed. Because the barrier layer is doped with Si, Si atoms can react with atoms of a conductive material forming the interconnection structure to form bonds, the barrier capability of the Si-doped barrier layer is strong, the diffusion of the atoms of the conductive material can be effectively inhibited, the occurrence of the time-dependent breakdown phenomenon of the dielectric layer is favorably reduced, and the reliability of the formed interconnection structure is favorably improved.

Description

Interconnect structure and method of forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to an interconnect structure and a method for forming the same.

Background

With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.

In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. As technology nodes advance, the size of interconnect structures also becomes smaller.

As the size of the interconnect structure is reduced, the reliability of the interconnect structure formed by the prior art needs to be improved.

Disclosure of Invention

The invention provides an interconnection structure and a forming method thereof, which are used for improving the reliability of the interconnection structure.

In order to solve the above problem, the present invention provides a method for forming an interconnect structure, including:

providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier layer on the bottom and the side wall of the opening, wherein the barrier layer is a Si-doped barrier layer; and filling the opening with the barrier layer formed on the bottom and the side wall with a conductive material to form an interconnection structure.

Optionally, the step of forming the barrier layer includes: and forming the barrier layer by adopting an atomic layer deposition process.

Optionally, in the step of forming the barrier layer, a material of the barrier layer includes Si-doped TaN.

Optionally, the barrier layer is a laminated structure; the step of forming the barrier layer comprises: forming a first Si-doped TaN layer on the bottom and the side wall of the opening; forming a TaN layer on the first Si-doped TaN layer; and forming a second Si-doped TaN layer on the TaN layer.

Optionally, in the step of forming the first Si-doped TaN layer, the doping concentration of Si in the first Si-doped TaN layer is in a range of 5% to 15% in atomic number percentage; in the step of forming the second Si-doped TaN layer, the doping concentration of Si in the second Si-doped TaN layer is in a range of 5% to 15% in atomic number percentage.

Optionally, in the step of forming the first Si-doped TaN layer, the doping concentration of Si is gradually reduced along a direction in which the dielectric layer points to the TaN layer; in the step of forming the second Si-doped TaN layer, the doping concentration of Si is gradually increased along the direction of the TaN layer pointing to the opening.

Optionally, the step of forming the first Si-doped TaN layer includes: performing at least one first Si-doped material deposition, wherein the first Si-doped material deposition comprises the following steps: depositing a first Ta-containing material layer on the bottom and the side wall of the opening; depositing a first Si-containing material layer on the first Ta-containing material layer; depositing a first N-containing material layer on the first Si-containing material layer; wherein the step of depositing the first Si-containing material layer comprises: introducing a first Si-containing reaction gas, wherein the first Si-containing reaction gas comprises silane; purging the first Si-containing reactant gas; the step of forming the second Si-doped TaN layer comprises: performing at least one second Si-doped material deposition, wherein the second Si-doped material deposition comprises the following steps: depositing a second Ta-containing material layer on the TaN layer; depositing a second Si-containing material layer on the second Ta-containing material layer; depositing a second N-containing material layer on the second Si-containing material layer; wherein the step of depositing the second Si-containing material layer comprises: introducing a second Si-containing reaction gas, wherein the second Si-containing reaction gas comprises silane; purging the second Si-containing reaction gas.

Optionally, the step of performing the first Si-doped material deposition for a plurality of times includes: the flow of silane introduced into the first Si-containing reaction gas is gradually reduced; the step of performing a plurality of second Si-doped material depositions comprises: the flow of silane introduced into the second Si-containing reaction gas is gradually increased; alternatively, the step of performing a plurality of first Si-doped material depositions comprises: the pulse time for introducing silane is gradually reduced; the step of performing a plurality of second Si-doped material depositions comprises: the pulse time for silane introduction was increased in steps.

Optionally, in the step of forming the barrier layer, a ratio of the thickness of the first Si-doped TaN layer, the thickness of the TaN layer, and the thickness of the second Si-doped TaN layer is in a range from 1:1:1 to 2:1: 2.

Optionally, in the step of forming the first Si-doped TaN layer, the thickness of the first Si-doped TaN layer is within the range of

To

Within the range; form aIn the step of the TaN layer, the thickness of the TaN layer is within

To

Within the range; in the step of forming the second Si-doped TaN layer, the thickness of the second Si-doped TaN layer is within

To

Within the range.

Optionally, in the step of forming the dielectric layer, the dielectric layer is made of an ultra-low K material.

Optionally, the step of forming the interconnect structure includes: filling a conductive material into the opening with the barrier layer formed on the bottom and the side wall to form a conductive layer; and carrying out annealing treatment on the barrier layer and the conductive layer to form an interconnection structure.

Optionally, in the step of forming the interconnect structure, the conductive material is Cu.

Accordingly, the present invention also provides an interconnect structure comprising:

a substrate; a dielectric layer on the substrate; an interconnect structure located within the dielectric layer; and the barrier layer is positioned between the interconnection structure and the dielectric layer and is a Si-doped barrier layer.

Optionally, the material of the barrier layer is Si-doped TaN.

Optionally, the barrier layer is a laminated structure; the barrier layer includes: a first Si-doped TaN layer positioned between the dielectric layer and the interconnection structure; a TaN layer located between the first Si doped TaN layer and the interconnect structure; a second Si-doped TaN layer located between the TaN layer and the interconnect structure.

Optionally, a ratio of the thickness of the first Si-doped TaN layer, the thickness of the TaN layer, and the thickness of the second Si-doped TaN layer is in a range of 1:1:1 to 2:1: 2.

Optionally, the doping concentration of Si is gradually reduced along the direction from the dielectric layer to the TaN layer; and the doping concentration of Si is gradually reduced and increased along the TaN layer towards the direction of the interconnection structure.

Optionally, the doping concentration of Si in the first Si-doped TaN layer is in a range of 5% to 15% in atomic number percentage;

the doping concentration of Si in the second Si-doped TaN layer is in the range of 5 to 15 atomic number percent.

Optionally, the thickness of the first Si-doped TaN layer is within

To

Within the range; the TaN layer has a thickness of

To

Within the range; the thickness of the second Si-doped TaN layer is within

To

Within the range.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the technical scheme of the invention, the barrier layers are formed on the bottom and the side wall of the opening and are Si-doped barrier layers; and forming an interconnection structure in the opening in which the barrier layer is formed. Because the barrier layer is doped with Si, Si atoms can react with atoms of a conductive material forming the interconnection structure to form bonds, the barrier capability of the Si-doped barrier layer is strong, the diffusion of the atoms of the conductive material can be effectively inhibited, the occurrence of the time-dependent breakdown phenomenon of the dielectric layer is favorably reduced, and the reliability of the formed interconnection structure is favorably improved.

In an alternative scheme of the invention, the barrier layer is of a laminated structure and comprises a first Si-doped TaN layer, a TaN layer and a second Si-doped TaN layer, wherein the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer are sequentially located on the bottom and the side wall of the opening. Because Si, C, O and TaN can react locally to form TaNSi-O-SiCH, the first Si-doped TaN layer can repair the defects on the interface of the TaN layer and the dielectric layer, so that the adhesion of the barrier layer and the dielectric layer is improved; si, Cu and TaN can react to form TaN-Si-Cu, so that the second Si-doped TaN layer can improve the adhesion between the barrier layer and the interconnection structure; therefore, the formation of the first Si-doped TaN layer and the second Si-doped TaN layer effectively improves the adhesion between the barrier layer and the dielectric layer and between the barrier layer and the interconnection structure, and is beneficial to improving the reliability of the interconnection structure.

In the alternative scheme of the invention, the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can be formed in an atomic deposition mode, and the step coverage of the film layer formed in the atomic layer deposition mode is good, so that the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can better cover the bottom and the side wall of the opening, the process difficulty of filling a conductive material is reduced, and the process window is enlarged.

Drawings

Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps of a method for forming an interconnect structure;

fig. 3 to 7 are schematic structural diagrams corresponding to steps of an interconnect structure forming method according to an embodiment of the invention.

Detailed Description

As can be seen from the background art, the interconnect structure formed in the prior art has a problem of low reliability. The reason for the low reliability of the interconnection structure is analyzed by combining a forming method of the interconnection structure:

referring to fig. 1 to 2, schematic structural diagrams corresponding to steps of a method for forming an interconnect structure are shown.

As shown in fig. 1, a substrate 10 is provided; forming a dielectric layer 11 on the substrate 10; an opening 12 is formed in the dielectric layer 11.

As shown in fig. 2, a barrier layer 13 is formed on the bottom and the sidewall of the opening 12 (shown in fig. 1); the opening 12 formed with the barrier layer 13 is filled with a conductive material to form an interconnect structure 14.

The barrier layer 13 is often formed by atomic layer deposition. The formation of the barrier layer 13 by atomic layer deposition can minimize the formation of protrusions (overhand) on the sidewall of the opening 12 on the side away from the substrate 10, thereby facilitating the filling of the conductive material.

However, the density of the barrier layer 13 formed by the atomic layer deposition method is low, so that the barrier capability of the formed barrier layer 13 is weak, and atoms of the conductive material are easily diffused into the Dielectric layer 11, so that the electrical isolation performance of the Dielectric layer 11 is reduced, a Time Dependent Dielectric Breakdown (TDDB) phenomenon is easily generated, and the reliability of the formed interconnection structure is affected.

In order to solve the technical problem, the invention provides a method for forming an interconnection structure, which comprises the following steps:

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 3 to fig. 7, schematic structural diagrams corresponding to various steps of an embodiment of a method for forming an interconnect structure of the present invention are shown.

Referring to fig. 3, a substrate 100 is provided.

The substrate 100 is used to provide a foundation for process operations. In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.

In this embodiment, the substrate 100 is a planar substrate. In other embodiments of the present invention, the substrate may further have a semiconductor structure, such as a fin portion.

With continued reference to fig. 3, a dielectric layer 110 is formed over the substrate 100.

The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer, and is used to realize electrical isolation between adjacent device layers. In this embodiment, the dielectric layer 110 is made of an ultra-low K material, such as doped silicon dioxide, an organic polymer, a porous material, and the like. In other embodiments of the present invention, the material of the dielectric layer may also be selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low-K dielectric material (dielectric constant less than 2.5). Specifically, the dielectric layer 110 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace tube.

With continued reference to fig. 3, an opening 120 is formed within the dielectric layer 110.

The openings 120 are used to fill and form interconnect structures to make connections to external circuitry. In this embodiment, the bottom of the opening 120 exposes the substrate 100, so as to connect the substrate 100 with an external circuit.

In this embodiment, the formed interconnect Structure is a Dual Damascene Structure (Dual Damascene Structure). The opening 120 includes a trench (not labeled) that extends through a portion of the thickness of the dielectric layer 110; and a via (not shown) located at the bottom of the trench and penetrating through the dielectric layer 110 with the remaining thickness to expose the substrate 100. In other embodiments of the present invention, the formed interconnect Structure may also be a Single Damascene Structure (Single Damascene Structure) or other forms of interconnect structures.

Referring to fig. 4, a barrier layer 130 is formed on the bottom and sidewalls of the opening 120, and the barrier layer 130 is a Si-doped barrier layer.

The barrier layer 130 is used to realize isolation between the formed interconnection structure and the dielectric layer 110, block atoms of the conductive material forming the interconnection structure from diffusing, and prevent the atoms of the conductive material from diffusing into the dielectric layer 110 to affect the electrical isolation performance of the dielectric layer 110. Because the barrier layer 130 is a Si-doped barrier layer, and Si can react with atoms of the conductive material to form bonds, the Si-doped barrier layer can effectively inhibit diffusion of atoms of the conductive material, which is beneficial to improving the barrier capability of the barrier layer 130, preventing the atoms of the conductive material from diffusing into the dielectric layer, reducing the time-lapse breakdown phenomenon of the dielectric layer 110, and improving the reliability of the formed interconnection structure. In this embodiment, in the step of forming the barrier layer 130, the material of the barrier layer 130 is Si-doped TaN.

The step of forming the barrier layer 130 includes: the barrier layer 130 is formed using an atomic layer deposition process. Because the step coverage performance of the film layer formed by the atomic layer deposition process is good, the method of forming the barrier layer 130 by the atomic layer deposition process can reduce the formation of protrusions on the side wall of the opening 120 away from the substrate 100, reduce the process difficulty of forming the interconnection structure, and enlarge the process window.

Specifically, the barrier layer 130 is a stacked structure, so the step of forming the barrier layer 130 includes: forming a first Si-doped TaN layer 131 on the bottom and the side wall of the opening 120; forming a TaN layer 132 on the first Si-doped TaN layer 131; a second Si doped TaN layer 133 is formed over the TaN layer 132.

The first Si-doped TaN layer 131 is used for realizing the connection between the barrier layer 130 and the dielectric layer 110, improving the barrier capability of the barrier layer 130, and enhancing the adhesion between the barrier layer 130 and the dielectric layer 110; the TaN layer 132 is used to prevent diffusion of conductive material atoms of the formed interconnect structure; the second Si-doped TaN layer 133 is used to realize the connection between the barrier layer 130 and the formed interconnect structure, and also used to react with the conductive material atoms to form bonds, so as to block the diffusion of the conductive material atoms, thereby improving the blocking capability of the barrier layer 130.

At the interface between the barrier layer 130 and the dielectric layer 110, Si atoms doped in the first Si-doped TaN layer 131 can form a bond with materials of the TaN layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH, so that local defects at the interface are repaired, the density of the barrier layer 130 is improved, the barrier capability of the barrier layer 130 is enhanced, and the reliability of the formed interconnection structure is improved. In addition, the doped Si atoms bond with the materials of the TaN layer 132 and the dielectric layer 110, and may also enhance the adhesion between the barrier layer 130 and the dielectric layer 110.

The doping concentration of Si in the first Si doped TaN layer 131 should not be too large or too small. If the doping concentration of Si in the first Si-doped TaN layer 131 is too small, too few Si atoms capable of forming bonds with the materials of the TaN layer 132 and the dielectric layer 110 may affect the blocking capability of the barrier layer 130; if the doping concentration of Si in the first Si doped TaN layer 131 is too large, the resistance of the formed interconnect structure will increase. Specifically, in the step of forming the first Si-doped TaN layer 131, the doping concentration of Si in the first Si-doped TaN layer 131 is in a range of 5% to 15% in terms of atomic number percentage.

In addition, since the doped Si atoms react with the interface of the dielectric layer 110 to form bonds, the probability that the Si atoms far away from the dielectric layer 110 react with the material of the dielectric layer 110 to form bonds is low, and the effect of increasing the blocking capability of the blocking layer 130 is weak; and Si atoms further from the dielectric layer 110 increase the resistance of the formed interconnect structure. Therefore, in order to control the resistance of the formed interconnect structure, in the present embodiment, in the step of forming the first Si-doped TaN layer 131, the doping concentration of Si is gradually decreased along the direction from the dielectric layer 110 to the TaN layer 132.

At the interface of the barrier layer 130 and the interconnect structure, the doped Si atoms in the second Si doped TaN layer 133 can react with the TaN layer 132 and the interconnect structure to form bonds, thereby enhancing the barrier capability of the barrier layer 130 and improving the reliability of the formed interconnect structure. In addition, the doped Si atoms bond to the materials of the TaN layer 132 and the interconnect structure, and may also enhance adhesion between the barrier layer 130 and the dielectric layer 110.

The doping concentration of Si in the second Si doped TaN layer 133 should not be too large or too small. If the doping concentration of Si in the second Si doped TaN layer 133 is too small, too few Si atoms capable of bonding with the TaN layer 132 and the interconnect structure material will affect the barrier capability of the barrier layer 130; if the doping concentration of Si in the second Si doped TaN layer 133 is too high, the resistance of the formed interconnect structure will increase. Specifically, in the step of forming the second Si-doped TaN layer 133, the doping concentration of Si in the second Si-doped TaN layer 133 is in a range of 5% to 15% in terms of atomic number percentage.

In addition, since the doped Si atoms react to form bonds at the interface with the interconnect structure, the Si atoms near the TaN layer 132 have a lower probability of reacting to form bonds with the interconnect structure material, and thus have a weaker effect on increasing the blocking capability of the barrier layer 130; and Si atoms near the TaN layer 132 increase the resistance of the resulting interconnect structure. Therefore, in the present embodiment, in the step of forming the second Si-doped TaN layer 133, the doping concentration of Si gradually increases along the direction of the TaN layer 132 toward the opening 120.

Specifically, the step of forming the first Si-doped TaN layer 131 includes: performing at least one first Si-doped material deposition, wherein the first Si-doped material deposition comprises the following steps: depositing a first Ta-containing material layer on the bottom and sidewalls of the opening 120; depositing a first Si-containing material layer on the first Ta-containing material layer; a first N-containing material layer is deposited over the first Si-containing material layer.

Wherein the step of depositing the first Si-containing material layer comprises: introducing a first Si-containing reaction gas, wherein the first Si-containing reaction gas comprises silane; purging the first Si-containing reaction gas.

In this embodiment, the step of forming the first Si-doped TaN layer 131 includes: and carrying out a plurality of times of first Si-doped material deposition. Therefore, when the first Si-doped material is deposited for a plurality of times, the flow of silane introduced into the first Si-containing reaction gas is gradually reduced; or the pulse time for introducing the silane is gradually reduced; alternatively, the flow rate of silane introduced into the first Si-containing reaction gas is gradually decreased and the pulse time for introducing silane is gradually decreased. By the method, the probability of Si atoms participating in the reaction can be reduced, the doping concentration of the Si atoms in the formed atomic layer is reduced, and further the doping concentration of Si in the formed first Si-doped TaN layer 131 is gradually reduced along the direction from the dielectric layer 110 to the TaN layer 132.

It should be noted that, in the step of performing the first Si-doped material deposition for a plurality of times, the flow rate of silane in the first Si-containing reaction gas is not too large or too small. If the flow rate of silane in the first Si-containing reaction gas is too high, the amount of Si doped in the formed first Si-doped TaN layer 131 is too small, which may affect the blocking capability of the formed barrier layer 130; if the flow of silane in the first Si-containing reaction gas is too small, the first Si-doped TaN layer 131 is formed with too much Si, which increases the resistance of the interconnect structure formed. Specifically, in the present embodiment, in the step of performing the first Si-doped material deposition for a plurality of times, the flow rate of silane in the first Si-containing reaction gas is gradually decreased from 300 seem to 500 seem to be in the range of 50 seem to 100 seem.

In the step of depositing the first Si-doped material for a plurality of times, the rate of successive reduction of the pulse time of silane introduction is not preferably too large or too small. If the rate of the gradual reduction of the silane pulse duration is too large, the doped Si in the formed first Si-doped TaN layer 131 will be too small, which will affect the blocking capability of the formed barrier layer 130; the rate of successive reduction in the time to pulse through the silane, if too small, will result in the formation of a first Si-doped TaN layer 131 that is doped with too much Si, which will increase the resistance of the resulting interconnect structure. Specifically, in the present embodiment, in the step of performing the first Si-doped material deposition for a plurality of times, the pulse time for introducing the silane is gradually reduced from 300 ms to 500 ms to 50 ms to 100 ms.

It is noted that, prior to depositing the first Si-containing material layer, the step of depositing the first Si-doped material further comprises: a first Ta-containing material layer is deposited on the bottom and sidewalls of the opening 120. Specifically, the step of depositing the first Ta-containing material layer includes: introducing a first Ta-containing reactant gas comprising pentakis (dimethylamino) tantalum (V) (pentakis (dimethyllamino) tantalum (V), PDMAT); purging the first Ta-comprising reactant gas. The technical scheme of the step of introducing the first Ta-containing reaction gas is the same as that of the prior art, and the invention is not repeated herein.

After depositing the first Si-containing material layer, the step of depositing the first Si-doped material further comprises: a first N-containing material layer is deposited over the first Si-containing material layer. Specifically, the step of depositing the first N-containing material layer comprises the following steps: introducing a first N-containing reaction gas, wherein the first N-containing reaction gas comprises ammonia gas; purging the first N-containing reactant gas. The technical scheme of the step of introducing the first N-containing reaction gas is the same as that of the prior art, and the invention is not described herein again.

The step of forming the second Si doped TaN layer 133 includes: performing at least one second Si-doped material deposition, wherein the second Si-doped material deposition comprises the following steps: depositing a second Ta-containing material layer on the TaN layer 132; depositing a second Si-containing material layer on the second Ta-containing material layer; depositing a second N-containing material layer on the second Si-containing material layer.

Wherein the step of depositing the second Si-containing material layer comprises: introducing a second Si-containing reaction gas, wherein the second Si-containing reaction gas comprises silane; purging the second Si-containing reaction gas.

In this embodiment, the step of forming the second Si-doped TaN layer 133 includes: and carrying out a plurality of second Si-doped material depositions. Therefore, when the second Si-doped material is deposited for a plurality of times, the flow of silane introduced into the second Si-containing reaction gas is gradually increased; or the pulse time for introducing the silane is gradually increased; alternatively, the flow rate of silane introduced into the second Si-containing reaction gas is gradually increased and the pulse time for introducing silane is gradually increased. By the method, the probability of Si atoms participating in the reaction can be increased, the doping concentration of the Si atoms in the formed atomic layer is increased, and further, the doping concentration of Si in the formed first Si-doped TaN layer 131 is gradually increased along the direction of the TaN layer 132 pointing to the opening 120.

It should be noted that, in the step of performing the second Si-doped material deposition for a plurality of times, the flow rate of silane in the second Si-containing reaction gas is not too large or too small. If the flow of silane in the second Si-containing reaction gas is too high, the second Si-doped TaN layer 133 is formed with too much Si, which increases the resistance of the formed interconnect structure; if the flow rate of silane in the second Si-containing reactive gas is too small, the blocking capability of the formed barrier layer 130 will be affected. Specifically, in the present embodiment, in the step of performing the first Si-doped material deposition for a plurality of times, the flow rate of silane in the second Si-containing reaction gas is gradually increased from 50sccm to 100sccm to 300sccm to 500 sccm.

In the step of depositing the second Si-doped material for a plurality of times, the rate of the gradual increase of the silane pulse time is not suitable to be too large or too small. If the rate of the silane pulse time increasing is too large, the Si doped in the formed second Si-doped TaN layer 133 is too much, and the resistance of the formed interconnection structure is increased; the rate of the sequential increase in the silane pulse duration, if too small, will result in too little Si being doped in the second Si-doped TaN layer 133, which will affect the barrier capability of the formed barrier layer 130. Specifically, in this embodiment, in the step of performing the second Si-doped material deposition for a plurality of times, the pulse time for introducing the silane is gradually increased from 50 milliseconds to 100 milliseconds to 300 milliseconds to 500 milliseconds.

It should be noted that after forming the TaN layer 132 and before depositing the second Ta-containing material layer, the step of depositing the second Si-doped material further includes: a second Ta containing material layer is deposited over the TaN layer 132. Specifically, the step of depositing the second Ta-containing material layer includes: introducing a second Ta-containing reactant gas comprising pentakis (dimethylamino) tantalum (V) (pentakis (dimethyllamino) tantalum (V), PDMAT); purging the second Ta-comprising reactant gas. The technical scheme of the step of introducing the second Ta-containing reaction gas is the same as that of the prior art, and the invention is not repeated herein.

After depositing the second Ta-containing material layer, the step of depositing the second Si-doped material further comprises: depositing a second N-containing material layer on the second Si-containing material layer. Specifically, the step of depositing the second N-containing material layer comprises the following steps: introducing a second N-containing reaction gas, wherein the second N-containing reaction gas comprises ammonia gas; purging the second N-containing reactant gas. The technical scheme of the step of introducing the second N-containing reaction gas is the same as that of the prior art, and the invention is not described herein again.

It should be noted that the number of times the deposition of the first Si-doped material is performed is related to the thickness of the formed first Si-doped TaN layer 131; the number of times the second Si-doped material deposition is performed is related to the thickness of the second Si-doped TaN layer 133 that is formed. The number of times the first Si-doped material deposition and the number of times the second Si-doped material deposition are performed are determined according to the preset thickness of the first Si-doped TaN layer 131 and the preset thickness of the second Si-doped TaN layer 133, and process parameters (such as the flow rate of the first Si-containing reaction gas and the pulse time of silane) are set within a reasonable range to improve the performance of the formed interconnect structure.

The thickness of the first Si doped TaN layer 131 is neither too large nor too small. If the thickness of the first Si-doped TaN layer 131 is too large, the space of the remaining opening 120 is too small, so that the aspect ratio of the opening 120 is increased, and the process difficulty of subsequent filling of the conductive material is further increased; if the thickness of the first Si-doped TaN layer 131 is too small, the barrier capability of the formed barrier layer 130 is affected, which is not favorable for increasing the barrier capability of the barrier layer 130. Specifically, in the embodiment, in the step of forming the first Si-doped TaN layer 131, the thickness of the first Si-doped TaN layer 131 is greaterIs measured in

To

Within the range.

The thickness of the TaN layer 132 is preferably neither too large nor too small. If the thickness of the TaN layer 132 is too large, the space of the remaining opening 120 is too small, so that the aspect ratio of the opening 120 is increased, and the process difficulty of filling the conductive material subsequently is increased; if the thickness of the TaN layer 132 is too small, the barrier capability of the formed barrier layer 130 is affected. Specifically, in the present embodiment, in the step of forming the TaN layer 132, the thickness of the TaN layer 132 is within the range

To

Within the range.

The thickness of the second Si doped TaN layer 133 is preferably neither too large nor too small. If the thickness of the second Si-doped TaN layer 133 is too large, the space of the remaining opening 120 is too small, so that the aspect ratio of the opening 120 is increased, and the process difficulty of subsequent filling of the conductive material is further increased; if the thickness of the second Si doped TaN layer 133 is too small, the barrier capability of the formed barrier layer 130 is affected, which is not favorable for increasing the barrier capability of the barrier layer 130. Specifically, in the embodiment, in the step of forming the second Si-doped TaN layer 133, the thickness of the second Si-doped TaN layer 133 is within the range

To

Within the range.

It should be further noted that in the step of forming the barrier layer 130, the thickness of the first Si-doped TaN layer 131, the thickness of the TaN layer, and the ratio of the second Si-doped TaN layer 133 affect the resistance of the formed interconnect structure and the blocking capability of the barrier layer 130, and also affect the adhesion between the barrier layer 130 and the dielectric layer 110 and between the barrier layer 130 and the interconnect structure.

If the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 account for too much of the barrier layer 130, that is, the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 account for too much of the total thickness of the barrier layer 130, the resistance of the formed interconnect structure will be too large; if the proportion of the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 in the formed barrier layer 130 is too small, that is, the proportion of the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 in the total thickness of the barrier layer 130 is too small, it is not favorable for improving the barrier capability of the barrier layer 130, and it also affects the adhesion between the barrier layer 130 and the dielectric layer 110 and the interconnect structure. In this embodiment, in the step of forming the barrier layer, the ratio of the thickness of the first Si-doped TaN layer 131, the thickness of the TaN layer 132, and the thickness of the second Si-doped TaN layer 133 is in the range of 1:1:1 to 2:1: 2.

It should be noted that, referring to fig. 5, in order to improve the blocking capability of the blocking layer 130, in this embodiment, after forming the second Si-doped TaN layer 133, the step of forming the blocking layer 130 at the bottom and the sidewall of the opening 120 further includes: forming a supplemental TaN layer 134 on the second Si doped TaN layer 133; an adhesion layer 135 is formed over the supplemental TaN layer 134.

The supplemental TaN layer 134 is used to block the diffusion of the conductive material atoms to enhance the barrier capability of the barrier layer 130; the adhesion layer 134 is used to achieve a connection between the subsequently formed interconnect structure and the barrier layer 130, and improve adhesion between the formed barrier layer 130 and the interconnect structure.

In the step of forming the adhesion layer 135, the material of the adhesion layer 135 is Ta. Specifically, one or both of the step of forming the supplemental TaN layer 134 and the step of forming the adhesion layer 135 include: the formation is carried out by adopting a physical vapor deposition process. In this embodiment, the supplemental TaN layer 134 and the adhesion layer 135 are formed by a physical vapor deposition process.

It should be noted that the thicknesses of the supplemental TaN layer 134 and the adhesion layer 135 are not preferably too large or too small. If the thickness of the supplemental TaN layer 134 is too large, the space of the remaining opening 120 will be too small, so as to increase the aspect ratio of the opening 120, and further increase the difficulty of the subsequent conductive material filling process; the thickness of the supplemental TaN layer 134, if too small, is detrimental to enhancing the barrier capability of the barrier stack 130. Specifically, in the step of forming the supplemental TaN layer 134, the supplemental TaN layer 134 has a thickness

To

Within the range.

If the thickness of the adhesion layer 135 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the difficulty of the subsequent conductive material filling process; the thickness of the adhesion layer 135, if too small, may affect the adhesion between the formed barrier stack 130 and the interconnect structure. Specifically, in the step of forming the adhesive layer 135, the adhesive layer 135 has a thickness of

To

Within the range.

It should be noted that, in other embodiments of the present invention, the connection between the interconnect structure and the dielectric layer may also be directly realized through the second Si-doped TaN layer, so as to reduce the thickness of the formed barrier layer, enlarge the size of the opening, reduce the difficulty of the process for filling the conductive material, and enlarge the process window.

Referring to fig. 6 to 7, the opening 120 (shown in fig. 5) having the barrier layer 130 formed on the bottom and the sidewall thereof is filled with a conductive material to form an interconnect structure 150 (shown in fig. 7).

In this embodiment, the interconnect structure 150 is a dual damascene structure, and the opening 120 includes a trench (not shown) and a via (not shown) at the bottom of the trench, so that the interconnect structure 150 includes a plug (not shown) in the via and a connection (not shown) in the trench.

Specifically, the step of forming the interconnect structure 150 includes:

referring to fig. 6, a conductive material is filled into the opening 120 (shown in fig. 5) having the barrier layer 130 formed on the bottom and the sidewall thereof, thereby forming a conductive layer 151.

The conductive layer 151 is used to form an interconnect structure for connection to an external circuit. In this embodiment, the conductive material is Cu, so the material of the conductive layer 151 is Cu.

Therefore, at the interface between the barrier layer 130 and the conductive layer 151, the doped Si atoms in the second Si-doped TaN layer 133 can form Cu-Si-TaN by bonding with the TaN layer 132 and the conductive material, thereby inhibiting the diffusion of the conductive material atoms, improving the barrier capability of the barrier layer 130, and improving the reliability of the formed interconnect structure 150; in addition, Si atoms bond with the TaN layer 132 and the conductive material to form Cu-Si-TaN, which may also enhance adhesion between the TaN layer 132 and the conductive material.

Specifically, the step of forming the conductive layer 151 includes: forming a seed layer on the bottom and the side wall of the opening 120; then, a conductive material is filled into the opening 120 by an electrochemical plating (ECP) method to form a conductive layer 151.

Referring to fig. 7, the barrier layer 130 and the conductive layer 151 (shown in fig. 6) are annealed 140 to form an interconnect structure 150.

The annealing process 140 is used to form the interconnect structure 150, and is also used to diffuse Si atoms in the barrier layer 130, so that the Si atoms react with the dielectric layer 110 and the interconnect structure 150 to form bonds, thereby improving the barrier ability of the barrier layer 130, and improving the adhesion of the barrier layer 130 to the dielectric layer 110 and the interconnect structure 150. Specifically, at the interface between the first Si-doped TaN layer 131 and the dielectric layer 110 and the interface between the first Si-doped TaN layer 131 and the TaN layer 132, the annealing treatment 140 diffuses Si atoms into the dielectric layer 110 and the TaN layer 132, and the Si atoms react with TaN, O, C, and H locally to form bonds, thereby forming tassi-O-SiCH, so as to repair defects at the interface between the TaN layer 132 and the dielectric layer 110, improve the density of the TaN layer 132, enhance the blocking capability of the TaN layer 132, facilitate the improvement of the blocking capability of the blocking layer 130, and improve the reliability of the interconnect structure 150.

At the interface between the second Si-doped TaN layer 133 and the TaN layer 132 and the interface between the second Si-doped TaN layer 133 and the interconnect structure 150, the annealing treatment 140 diffuses silicon atoms into the TaN layer 132 and the interconnect structure 150, and the Si atoms react with TaN and Cu atoms to form bonds, thereby forming Cu-Si-TaN, so as to inhibit diffusion of Cu atoms, improve adhesion between the TaN layer 132 and the interconnect structure 150, facilitate improvement of the barrier capability of the barrier layer 130, and improve reliability of the interconnect structure 150.

Specifically, in the step of performing the annealing treatment 140, the annealing temperature is not preferably too high or too high. If the annealing temperature is too high, unnecessary process risks are caused, and the possibility of damaging other semiconductor structures on the substrate 100 is increased; if the annealing temperature is too low, the diffusion of Si atoms is affected, which is not favorable for the reaction of Si atoms with the material atoms of the TaN layer 132 and the interconnect structure 150 to form bonds, improving the barrier capability of the formed barrier layer 130, and improving the adhesion between the barrier layer 130 and the interconnect structure 150 and the dielectric layer 110. Specifically, in the step of performing the annealing treatment, the annealing temperature is in the range of 300 ℃ to 375 ℃.

The annealing time is preferably neither too long nor too short. If the annealing time is too long, unnecessary process risks may be caused, increasing the possibility of damage to other semiconductor structures on the substrate 100; if the annealing time is too short, the silicon atoms cannot diffuse sufficiently, which is not favorable for the Si atoms to react with the material atoms of the TaN layer 132 and the interconnect structure 150 to form bonds, which is not favorable for improving the barrier capability of the formed barrier layer 130, and is also not favorable for improving the adhesion between the barrier layer 130 and the interconnect structure 150 and the dielectric layer 110. Specifically, in the step of performing the annealing treatment, the annealing time is in the range of 3 minutes to 6 minutes.

It should be noted that in the present embodiment, in the step of forming the conductive layer 151, the conductive layer 151 is also located on the dielectric layer 110; and in the step of forming the barrier layer 130, the barrier layer 130 is also located on the dielectric layer 110. Therefore, after the conductive layer 151 is formed and before the annealing process 140 is performed, the forming method further includes: a planarization process is performed to remove the conductive layer 151 and the barrier layer 130 on the dielectric layer 110, and form an interconnect structure 150 located in the opening 120 (shown in fig. 5).

Specifically, the planarization process is performed by a chemical mechanical polishing method, and the planarization process is stopped until the surface of the dielectric layer 110 is exposed.

Correspondingly, the invention also provides an interconnection structure. Referring to fig. 7, a schematic diagram of an embodiment of the interconnect structure of the present invention is shown.

The interconnect structure includes: a substrate 100; a dielectric layer 110 on the substrate 100; an interconnect structure 150 located within the dielectric layer 110; a barrier layer 130 between the interconnect structure 150 and the dielectric layer 110, wherein the barrier layer 130 is a Si-doped barrier layer.

The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer, and is used to realize electrical isolation between adjacent device layers. The material of the dielectric layer 110 may be selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant greater than or equal to 2.5, less than 3.9) or ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the dielectric layer 110 is made of an ultra-low K material, such as doped silicon dioxide, an organic polymer, a porous material, and the like.

The interconnect structure 150 is used to make connections to external circuitry. Specifically, the interconnect structure 150 is a dual damascene structure, so the interconnect structure 150 includes a plug (not shown) located in the via and a connection (not shown) located in the trench. In this embodiment, the material of the interconnect structure 150 is a conductive material, such as Cu.

The barrier layer 130 is used to realize isolation between the interconnect structure and the dielectric layer 110, block atoms of a conductive material forming the interconnect structure from diffusing, and prevent the atoms of the conductive material from diffusing into the dielectric layer 110 to affect the electrical isolation performance of the dielectric layer 110.

Because the barrier layer 130 is a Si-doped barrier layer, and Si can react with atoms of the conductive material to form bonds, the Si-doped barrier layer can effectively inhibit diffusion of atoms of the conductive material, which is beneficial to improving the blocking capability of the barrier layer 130, preventing the atoms of the conductive material from diffusing into the dielectric layer, reducing the occurrence of time-lapse breakdown of the dielectric layer 130, and improving the reliability of the interconnection structure 150. In this embodiment, the material of the barrier layer 130 is Si-doped TaN.

The barrier layer 130 is a stacked structure including: a first Si doped TaN layer 131 between the dielectric layer 110 and the interconnect structure 150; a TaN layer 132 between the first Si doped TaN layer 131 and the interconnect structure 150; a second Si doped TaN layer 133 between the TaN layer 132 and the interconnect structure 150.

The first Si-doped TaN layer 131 is used for realizing the connection between the barrier layer 130 and the dielectric layer 110, improving the barrier capability of the barrier layer 130, and enhancing the adhesion between the barrier layer 130 and the dielectric layer 110; the TaN layer 132 is used to prevent atomic diffusion of the conductive material of the interconnect structure 150; the second Si-doped TaN layer 133 is used to realize the connection between the barrier layer 130 and the interconnect structure 150, and also used to react with the conductive material atoms to form bonds, so as to block the diffusion of the conductive material atoms, thereby improving the blocking capability of the barrier layer 130.

At the interface between the barrier layer 130 and the dielectric layer 110, Si atoms doped in the first Si-doped TaN layer 131 can form a bond with materials of the TaN layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH, so that local defects at the interface are repaired, the density of the barrier layer 130 is improved, the blocking capability of the barrier layer 130 is enhanced, and the reliability of the interconnection structure 150 is improved. In addition, the doped Si atoms bond with the materials of the TaN layer 132 and the dielectric layer 110, and may also enhance the adhesion between the barrier layer 130 and the dielectric layer 110.

Specifically, at the interface between the first Si-doped TaN layer 131 and the dielectric layer 110 and the interface between the first Si-doped TaN layer 131 and the TaN layer 132, Si atoms diffuse into the dielectric layer 110 and the TaN layer 132, and the Si atoms react with TaN, O, C, and H locally to form bonds, thereby forming TaNSi-O-SiCH, so as to repair defects at the interface between the TaN layer 132 and the dielectric layer 110, improve the density of the TaN layer 132, enhance the blocking capability of the TaN layer 132, facilitate the improvement of the blocking capability of the blocking layer 130, and improve the reliability of the interconnect structure 150.

At the interface of the barrier layer 130 and the interconnect structure 150, the doped Si atoms in the second Si doped TaN layer 133 can react with the TaN layer 132 and the interconnect structure to form bonds, thereby enhancing the barrier capability of the barrier layer 130 and improving the reliability of the interconnect structure 150. In addition, the doped Si atoms bond to the materials of the TaN layer 132 and the interconnect structure 150, and may also enhance adhesion between the barrier layer 130 and the dielectric layer 110.

At the interface of the second Si-doped TaN layer 133 and the TaN layer 132 and the interface layer of the second Si-doped TaN layer 133 and the interconnect structure 150, Si atoms diffuse into the TaN layer 132 and the interconnect structure 150, and react with TaN and Cu atoms to form bonds, so as to form Cu-Si-TaN, thereby improving the adhesion of the TaN layer 132 and the interconnect structure 150, facilitating the improvement of the barrier capability of the barrier layer 130, and improving the reliability of the interconnect structure 150.

The doping concentration of Si in the first Si doped TaN layer 131 should not be too large or too small. If the doping concentration of Si in the first Si-doped TaN layer 131 is too small, too few Si atoms capable of forming bonds with the materials of the TaN layer 132 and the dielectric layer 110 may affect the blocking capability of the barrier layer 130; if the doping concentration of Si in the first Si doped TaN layer 131 is too large, the resistance of the interconnect structure 150 is increased. Specifically, the doping concentration of Si in the first Si-doped TaN layer 131 is in the range of 5% to 15% in atomic number percentage.

In addition, since the doped Si atoms react with the interface of the dielectric layer 110 to form bonds, the probability that the Si atoms far away from the dielectric layer 110 react with the material of the dielectric layer 110 to form bonds is low, and the effect of increasing the blocking capability of the blocking layer 130 is weak; and Si atoms further from the dielectric layer 110 increase the resistance of the interconnect structure 150. Therefore, in order to control the resistance of the interconnect structure 150, in the present embodiment, the doping concentration of Si is gradually decreased along the direction from the dielectric layer 110 to the TaN layer 132.

The doping concentration of Si in the second Si doped TaN layer 133 should not be too large or too small. If the doping concentration of Si in the second Si doped TaN layer 133 is too small, too few Si atoms can bond with the materials of the TaN layer 132 and the interconnect structure 150, which may affect the barrier capability of the barrier layer 130; if the doping concentration of Si in the second Si doped TaN layer 133 is too high, the resistance of the interconnect structure 150 is increased. Specifically, the doping concentration of Si in the second Si-doped TaN layer 133 is in the range of 5% to 15% in atomic number percentage.

In addition, since the doped Si atoms react to form bonds at the interface with the interconnect structure 150, the Si atoms near the TaN layer 132 have a lower probability of reacting to form bonds with the interconnect structure 150 material, which is less effective in increasing the barrier capability of the barrier layer 130; and the Si atoms near the TaN layer 132 increase the resistance of the interconnect structure 150. Therefore, in the present embodiment, the doping concentration of Si in the second Si-doped TaN layer 133 gradually decreases and increases along the direction of the TaN layer 132 toward the interconnect structure 150.

The thickness of the first Si doped TaN layer 131 is neither too large nor too small. If the thickness of the first Si-doped TaN layer 131 is too large, the process difficulty of filling conductive material may be increased; if the thickness of the first Si doped TaN layer 131 is too small, the blocking capability of the barrier layer 130 is affected, which is not favorable for increasing the blocking capability of the barrier layer 130. Specifically, in this embodiment, the thickness of the first Si-doped TaN layer 131 is within

To

Within the range.

The thickness of the TaN layer 132 is preferably neither too large nor too small. If the thickness of the TaN layer 132 is too large, the process difficulty of filling conductive material may increase; if the thickness of the TaN layer 132 is too small, the barrier capability of the barrier layer 130 is affected. Specifically, in the present embodiment, the thickness of the TaN layer 132 is within

To

Within the range.

The thickness of the second Si doped TaN layer 133 is preferably neither too large nor too small. If the thickness of the second Si-doped TaN layer 133 is too large, the space of the remaining opening 120 will be too small, and the aspect ratio of the opening 120 will be increased, thereby increasing the difficulty of the subsequent conductive material filling processDegree; if the thickness of the second Si doped TaN layer 133 is too small, the barrier capability of the barrier layer 130 is affected, which is not favorable for increasing the barrier capability of the barrier layer 130. Specifically, in this embodiment, the thickness of the second Si-doped TaN layer 133 is within

To

Within the range.

It should be further noted that the thickness of the first Si doped TaN layer 131, the thickness of the TaN layer 132, and the ratio of the second Si doped TaN layer 133 affect the resistance of the interconnect structure 150 and the barrier capability of the barrier layer 130, and also affect the adhesion between the barrier layer 130 and the dielectric layer 110 and the barrier layer 130 and the interconnect structure 150.

If the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 account for too much of the barrier layer 130, i.e., the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 account for too much of the total thickness of the barrier layer 130, the resistance of the interconnect structure 150 will be too large; if the proportion of the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 in the barrier layer 130 is too small, that is, the proportion of the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 in the total thickness of the barrier layer 130 is too small, it is not favorable for improving the blocking capability of the barrier layer 130, and it also influences the adhesion between the barrier layer 130 and the dielectric layer 110 and the interconnect structure 150. In this embodiment, the ratio of the thickness of the first Si-doped TaN layer 131, the thickness of the TaN layer 132, and the thickness of the second Si-doped TaN layer 133 is in the range of 1:1:1 to 2:1: 2.

It should be noted that, in order to improve the blocking capability of the blocking layer 130, in this embodiment, the blocking layer 130 further includes: a supplemental TaN layer 134 between the second Si doped TaN layer 133 and the interconnect structure 150; and an adhesion layer 135 between the supplemental TaN layer 134 and the interconnect structure 150. Specifically, the material of the adhesion layer 135 is tantalum.

The supplemental TaN layer 134 is used to block the diffusion of the conductive material atoms to enhance the barrier capability of the barrier layer 130; the adhesion layer 134 is used to realize the connection between the interconnect structure 150 and the barrier layer 130, and improve the adhesion between the barrier layer 130 and the interconnect structure 150.

It should be noted that the thicknesses of the supplemental TaN layer 134 and the adhesion layer 135 are not preferably too large or too small. If the thickness of the supplemental TaN layer 134 is too large, the space of the remaining opening 120 will be too small, so as to increase the aspect ratio of the opening 120, and further increase the difficulty of the subsequent conductive material filling process; the thickness of the supplemental TaN layer 134, if too small, is detrimental to enhancing the barrier capability of the barrier layer 130. Specifically, the supplemental TaN layer 134 has a thickness of

To

Within the range.

If the thickness of the adhesion layer 135 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the difficulty of the subsequent conductive material filling process; the thickness of the adhesion layer 135, if too small, may affect the adhesion between the barrier layer 130 and the interconnect structure 150. Specifically, the thickness of the adhesion layer 135 is within

To

Within the range.

It should be noted that, in other embodiments of the present invention, the connection between the interconnect structure 150 and the dielectric layer may also be directly realized through the second Si-doped TaN layer, so as to reduce the thickness of the barrier layer, enlarge the size of the opening, reduce the difficulty of the process for filling the conductive material, and enlarge the process window.

In summary, in the technical solution of the present invention, the barrier layers are formed on the bottom and the sidewall of the opening, and the barrier layers are Si-doped barrier layers; and forming an interconnection structure in the opening in which the barrier layer is formed. Because the barrier layer is doped with Si, Si atoms can react with atoms of a conductive material forming the interconnection structure to form bonds, the barrier capability of the Si-doped barrier layer is strong, the diffusion of the atoms of the conductive material can be effectively inhibited, the occurrence of the time-dependent breakdown phenomenon of the dielectric layer is favorably reduced, and the reliability of the formed interconnection structure is favorably improved. In an alternative embodiment of the present invention, the barrier layer is a stacked structure, and includes a first Si-doped TaN layer located on the bottom and the sidewall of the opening, a TaN layer located on the first Si-doped TaN layer, and a second Si-doped TaN layer located on the TaN layer. Because Si, C, O and TaN can react locally to form TaNSi-O-SiCH, the first Si-doped TaN layer can repair the defects on the interface of the TaN layer and the dielectric layer, so that the adhesion of the barrier layer and the dielectric layer is improved; si, Cu and TaN can react to form TaN-Si-Cu, so that the second Si-doped TaN layer can improve the adhesion between the barrier layer and the interconnection structure; therefore, the formation of the first Si-doped TaN layer and the second Si-doped TaN layer effectively improves the adhesion between the barrier layer and the dielectric layer and between the barrier layer and the interconnection structure, and is beneficial to improving the reliability of the interconnection structure. In addition, in an alternative scheme of the invention, the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can be formed in an atomic deposition mode, and the step coverage of the film layer formed in the atomic layer deposition mode is good, so that the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can better cover the bottom and the side wall of the opening, the process difficulty of filling a conductive material is reduced, and the process window is enlarged.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming an interconnect structure, comprising:

providing a substrate;

forming a dielectric layer on the substrate;

forming an opening in the dielectric layer;

forming a barrier layer on the bottom and the side wall of the opening, wherein the barrier layer is a Si-doped barrier layer and is of a laminated structure, and the step of forming the barrier layer comprises the following steps: forming a first Si-doped TaN layer on the bottom and the side wall of the opening, forming a TaN layer on the first Si-doped TaN layer, and forming a second Si-doped TaN layer on the TaN layer;

filling a conductive material in the opening with the barrier layer formed on the bottom and the side wall to form an interconnection structure, wherein the step of forming the interconnection structure comprises the following steps: filling a conductive material into the opening with the barrier layer formed on the bottom and the side wall to form a conductive layer; and annealing the barrier layer and the conductive layer to form an interconnection structure and diffuse silicon atoms in the barrier layer.

2. The method of forming of claim 1, wherein forming the barrier layer comprises: and forming the barrier layer by adopting an atomic layer deposition process.

3. The method of forming of claim 1, wherein in the step of forming the barrier layer, the material of the barrier layer comprises Si-doped TaN.

4. The forming method of claim 1, wherein in the step of forming the first Si-doped TaN layer, the doping concentration of Si in the first Si-doped TaN layer is in a range of 5% to 15% in atomic number percentage;

in the step of forming the second Si-doped TaN layer, the doping concentration of Si in the second Si-doped TaN layer is in a range of 5% to 15% in atomic number percentage.

5. The method according to claim 1, wherein in the step of forming the first Si-doped TaN layer, the doping concentration of Si is gradually reduced along a direction from the dielectric layer to the TaN layer;

in the step of forming the second Si-doped TaN layer, the doping concentration of Si is gradually increased along the direction of the TaN layer pointing to the opening.

6. The method of forming of claim 1, wherein forming the first Si doped TaN layer comprises: performing at least one first Si-doped material deposition, wherein the first Si-doped material deposition comprises the following steps: depositing a first Ta-containing material layer on the bottom and the side wall of the opening; depositing a first Si-containing material layer on the first Ta-containing material layer; depositing a first N-containing material layer on the first Si-containing material layer; wherein the step of depositing the first Si-containing material layer comprises: introducing a first Si-containing reaction gas, wherein the first Si-containing reaction gas comprises silane; purging the first Si-containing reactant gas;

the step of forming the second Si-doped TaN layer comprises: performing at least one second Si-doped material deposition, wherein the second Si-doped material deposition comprises the following steps: depositing a second Ta-containing material layer on the TaN layer; depositing a second Si-containing material layer on the second Ta-containing material layer; depositing a second N-containing material layer on the second Si-containing material layer; wherein the step of depositing the second Si-containing material layer comprises: introducing a second Si-containing reaction gas, wherein the second Si-containing reaction gas comprises silane; purging the second Si-containing reaction gas.

7. The method of forming of claim 6, wherein performing a plurality of depositions of the first Si-doped material comprises: the flow of silane introduced into the first Si-containing reaction gas is gradually reduced; the step of performing a plurality of second Si-doped material depositions comprises: the flow of silane introduced into the second Si-containing reaction gas is gradually increased;

alternatively, the step of performing a plurality of first Si-doped material depositions comprises: the pulse time for introducing silane is gradually reduced; the step of performing a plurality of second Si-doped material depositions comprises: the pulse time for silane introduction was increased in steps.

8. The forming method of claim 1, wherein in the step of forming the barrier layer, a ratio of a thickness of the first Si-doped TaN layer, a thickness of the TaN layer, and a thickness of the second Si-doped TaN layer is in a range of 1:1:1 to 2:1: 2.

9. The method of forming of claim 1, wherein in the step of forming the first Si doped TaN layer, the first Si doped TaN layer has a thickness in the range of

To

Within the range;

in the step of forming the TaN layer, the thickness of the TaN layer is within

To

Within the range;

in the step of forming the second Si-doped TaN layer, the thickness of the second Si-doped TaN layer is within

To

Within the range.

10. The method of claim 1, wherein in the step of forming the dielectric layer, the dielectric layer is made of an ultra-low-K material.

11. The method of forming of claim 1, wherein in the step of forming an interconnect structure, the conductive material is Cu.

12. An interconnect structure, comprising:

a substrate;

a dielectric layer on the substrate;

an interconnect structure located within the dielectric layer;

the barrier layer is positioned between the interconnection structure and the dielectric layer, the barrier layer is a Si-doped barrier layer, and the barrier layer is of a laminated structure; the barrier layer includes: a first Si-doped TaN layer positioned between the dielectric layer and the interconnection structure; a TaN layer located between the first Si doped TaN layer and the interconnect structure; a second Si-doped TaN layer located between the TaN layer and the interconnect structure;

and silicon atoms in the barrier layer are diffused through annealing treatment.

13. The interconnect structure of claim 12 wherein said barrier layer material is Si doped TaN.

14. The interconnect structure of claim 12, wherein a ratio of a thickness of said first Si doped TaN layer, a thickness of said TaN layer, and a thickness of said second Si doped TaN layer is in a range of 1:1:1 to 2:1: 2.

15. The interconnect structure of claim 12, wherein in said first Si doped TaN layer, the doping concentration of Si decreases gradually along the direction of said dielectric layer towards said TaN layer;

in the second Si-doped TaN layer, the doping concentration of Si is gradually reduced and increased along the direction from the TaN layer to the interconnection structure.

16. The interconnect structure of claim 12 wherein the doping concentration of Si in said first Si doped TaN layer is in the range of 5% to 15% in atomic number percentage;

17. The interconnect structure of claim 12 wherein said first Si doped TaN layer is at a thickness of

To

Within the range; the TaN layer has a thickness of

To

Within the range; the thickness of the second Si-doped TaN layer is within

To

Within the range.