CN108063117B - Interconnect structure and method of forming the same - Google Patents

Abstract

An interconnect structure and a method for forming the same, wherein the forming method comprises: providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier layer on the bottom and sidewalls of the opening , the barrier layer is a Si-doped barrier layer; conductive materials are filled in the openings with barrier layers formed at the bottom and sidewalls to form an interconnection structure. In the technical solution of the present invention, the barrier layer formed on the bottom and sidewalls of the opening is a Si-doped barrier layer; and then an interconnection structure is formed in the opening in which the barrier layer is formed. Since the barrier layer is doped with Si, the Si atoms can react with the atoms of the conductive material forming the interconnection structure to form bonds, so the Si-doped barrier layer has strong blocking ability, can effectively inhibit the diffusion of the atoms of the conductive material, and is conducive to reducing the The occurrence of breakdown phenomenon of the dielectric layer over time is beneficial to improve the reliability of the formed interconnect structure.

Description

Interconnect structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to an interconnection structure and a method for forming the same.

Background technique

With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are becoming smaller, and the circuit density inside the integrated circuit is increasing. This development makes the wafer surface unable to provide enough area to make the required interconnection lines.

In order to meet the requirements of interconnect lines after the critical dimension has been shrunk, the current conduction between different metal layers or the metal layers and the substrate is realized through an interconnect structure. As technology nodes advance, the size of interconnect structures also becomes smaller.

As the size of the interconnect structure shrinks, the reliability of the interconnect structure formed in the prior art needs to be improved.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide an interconnect structure and a method for forming the same, so as to improve the reliability of the interconnect structure.

In order to solve the above problems, the present invention provides a method for forming an interconnect structure, including:

providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier layer on the bottom and sidewalls of the opening, the barrier layer being a Si-doped barrier layer; at the bottom The conductive material is filled in the opening with the barrier layer formed on the sidewall to form an interconnection structure.

Optionally, the step of forming the barrier layer includes: using an atomic layer deposition process to form the barrier layer.

Optionally, in the step of forming the barrier layer, the material of the barrier layer includes Si-doped TaN.

Optionally, the barrier layer is a laminated structure; the step of forming the barrier layer includes: forming a first Si-doped TaN layer on the bottom and sidewalls of the opening; and forming a first Si-doped TaN layer on the first Si-doped TaN layer A TaN layer is formed on the TaN layer; a second Si-doped TaN layer is formed on the TaN layer.

Optionally, in the step of forming the first Si-doped TaN layer, the doping concentration of Si in the first Si-doped TaN layer is in the range of 5% to 15% by atomic percentage; In the step of the second Si-doped TaN layer, the doping concentration of Si in the second Si-doped TaN layer is in the range of 5% to 15% by atomic percentage.

Optionally, in the step of forming the first Si-doped TaN layer, the doping concentration of Si is gradually reduced along the direction from the dielectric layer to the TaN layer; forming the second Si-doped TaN layer In the step of layering, along the direction of the TaN layer pointing to the opening, the doping concentration of Si increases gradually.

Optionally, the step of forming the first Si-doped TaN layer includes: performing at least one deposition of a first Si-doped material, wherein the step of depositing the first Si-doped material includes: depositing on the bottom and sidewalls of the opening a first Ta-containing material layer; depositing a first Si-containing material layer on the first Ta-containing material layer; depositing a first N-containing material layer on the first Si-containing material layer; wherein, depositing a first Si-containing material layer The step of the material layer includes: feeding a first Si-containing reaction gas, the first Si-containing reaction gas including silane; removing the first Si-containing reaction gas; and the step of forming the second Si-doped TaN layer includes: Performing at least one deposition of a second Si-doped material, wherein the step of depositing the second Si-doped material includes: depositing a second Ta-containing material layer on the TaN layer; depositing a second Ta-containing material layer on the second Ta-containing material layer Si material layer; depositing a second N-containing material layer on the second Si-containing material layer; wherein, the step of depositing the second Si-containing material layer includes: passing a second Si-containing reaction gas, the second Si-containing material layer The reactive gas includes silane; the second Si-containing reactive gas is purged.

Optionally, the step of performing multiple depositions of the first Si-doped material includes: the flow rate of the silane in the first Si-containing reaction gas is gradually reduced; the step of performing multiple depositions of the second Si-doped material includes: feeding the second Si-doped material The flow rate of silane in the Si-containing reaction gas is increased successively; or, the step of performing multiple depositions of the first Si-doped material includes: successively decreasing the pulse time for feeding silane; the step of performing multiple depositions of the second Si-doped material includes: passing The pulse time of the silane was gradually increased.

Optionally, in the step of forming the barrier layer, the ratio of the thickness of the first Si-doped TaN layer, the thickness of the TaN layer and the thickness of the second Si-doped TaN layer is 1:1: 1 to 2:1:2 range.

到

范围内；形成所述TaN层的步骤中，所述TaN层的厚度在

到

范围内；形成所述第二Si掺杂TaN层的步骤中，所述第二Si掺杂TaN层的厚度在

到

范围内。Optionally, in the step of forming the first Si-doped TaN layer, the thickness of the first Si-doped TaN layer is

arrive

range; in the step of forming the TaN layer, the thickness of the TaN layer is

arrive

range; in the step of forming the second Si-doped TaN layer, the thickness of the second Si-doped TaN layer is within

arrive

within the range.

Optionally, in the step of forming the dielectric layer, the material of the dielectric layer is an ultra-low K material.

Optionally, the step of forming the interconnection structure includes: filling the openings with the barrier layer formed on the bottom and the sidewalls of the opening with a conductive material to form a conductive layer; annealing the barrier layer and the conductive layer to form an interconnection. connected structure.

Optionally, in the step of forming the interconnect structure, the conductive material is Cu.

Correspondingly, the present invention also provides an interconnection structure, comprising:

a substrate; a dielectric layer on the substrate; an interconnect structure within the dielectric layer; a barrier layer between the interconnect structure and the dielectric layer, the barrier layer being Si-doped barrier layer.

Optionally, the material of the barrier layer is Si-doped TaN.

Optionally, the barrier layer is a stacked structure; the barrier layer includes: a first Si-doped TaN layer located between the dielectric layer and the interconnect structure; and a first Si-doped TaN layer located between the dielectric layer and the interconnect structure; A TaN layer between the layer and the interconnect structure; a second Si-doped TaN layer between the TaN layer and the interconnect structure.

Optionally, the ratio of the thickness of the first Si-doped TaN layer, the thickness of the TaN layer, and the thickness of the second Si-doped TaN layer is in the range of 1:1:1 to 2:1:2 .

Optionally, along the direction from the dielectric layer to the TaN layer, the doping concentration of Si gradually decreases; along the direction from the TaN layer to the interconnect structure, the doping concentration of Si gradually decreases and increases big.

Optionally, by atomic percentage, the doping concentration of Si in the first Si-doped TaN layer is in the range of 5% to 15%;

The doping concentration of Si in the second Si-doped TaN layer is in the range of 5% to 15% in atomic percentage.

到

范围内；所述TaN层的厚度在

到

范围内；所述第二Si掺杂TaN层的厚度在

到

范围内。Optionally, the thickness of the first Si-doped TaN layer is

arrive

range; the thickness of the TaN layer is

arrive

range; the thickness of the second Si-doped TaN layer is

arrive

within the range.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the barrier layer formed on the bottom and sidewalls of the opening is a Si-doped barrier layer; and then an interconnection structure is formed in the opening in which the barrier layer is formed. Since the barrier layer is doped with Si, the Si atoms can react with the atoms of the conductive material forming the interconnection structure to form bonds, so the Si-doped barrier layer has strong blocking ability, can effectively inhibit the diffusion of the atoms of the conductive material, and is conducive to reducing the The occurrence of breakdown phenomenon of the dielectric layer over time is beneficial to improve the reliability of the formed interconnect structure.

In an optional solution of the present invention, the barrier layer is a stacked structure, including a first Si-doped TaN layer on the bottom and sidewalls of the opening, and a TaN layer on the first Si-doped TaN layer. and a second Si-doped TaN layer on the TaN layer. Since Si, C, O, and TaN can react locally to form TaNSi-O-SiCH, the first Si-doped TaN layer can repair the defects on the interface between the TaN layer and the dielectric layer, thereby improving the relationship between the barrier layer and the dielectric layer. The adhesion of the dielectric layer; Si, Cu and TaN can react to form TaN-Si-Cu, so the second Si-doped TaN layer can improve the adhesion between the barrier layer and the interconnect structure; Therefore, the formation of the first Si-doped TaN layer and the second Si-doped TaN layer effectively improves the adhesion between the barrier layer and the dielectric layer and between the barrier layer and the interconnect structure The adhesion is beneficial to improve the reliability of the interconnect structure.

In an optional solution of the present invention, the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can all be formed by atomic deposition. The step coverage is better, so the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can better cover the bottom and sidewalls of the opening, which is beneficial to reduce the filling of conductive materials The difficulty of the process is conducive to expanding the process window.

Description of drawings

1 to 2 are schematic structural diagrams corresponding to each step of a method for forming an interconnect structure;

3 to 7 are schematic structural diagrams corresponding to each step of an embodiment of the method for forming an interconnect structure of the present invention.

Detailed ways

It can be known from the background art that the interconnection structure formed in the prior art has the problem of low reliability. Now combined with a method for forming an interconnect structure, the reasons for the low reliability of the interconnect structure are analyzed:

Referring to FIG. 1 to FIG. 2 , schematic structural diagrams corresponding to each step of a method for forming an interconnect structure are shown.

As shown in FIG. 1 , a substrate 10 is provided; a dielectric layer 11 is formed on the substrate 10 ; an opening 12 is formed in the dielectric layer 11 .

As shown in FIG. 2 , a barrier layer 13 is formed on the bottom and sidewalls of the opening 12 (as shown in FIG. 1 ); conductive material is filled into the opening 12 formed with the barrier layer 13 to form an interconnection structure 14 .

The barrier layer 13 is usually formed by atomic layer deposition. Using the atomic layer deposition method to form the barrier layer 13 can minimize the formation of overhangs on the sidewall of the opening 12 away from the substrate 10 , thereby facilitating the filling of conductive materials.

However, the density of the barrier layer 13 formed by the atomic layer deposition method is low, so the barrier layer 13 formed has a weak barrier ability, and the atoms of the conductive material are easily diffused into the dielectric layer 11, thereby resulting in the electrical isolation performance of the dielectric layer 11. If it falls, the phenomenon of Time Dependent Dielectric Breakdown (TDDB) is prone to occur, which affects the reliability of the formed interconnect structure.

In order to solve the technical problem, the present invention provides a method for forming an interconnect structure, including:

providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier layer on the bottom and sidewalls of the opening, the barrier layer being a Si-doped barrier layer; at the bottom The conductive material is filled in the opening with the barrier layer formed on the sidewall to form an interconnection structure.

In the technical solution of the present invention, the barrier layer formed on the bottom and sidewalls of the opening is a Si-doped barrier layer; and then an interconnection structure is formed in the opening in which the barrier layer is formed. Since the barrier layer is doped with Si, the Si atoms can react with the atoms of the conductive material forming the interconnection structure to form bonds, so the Si-doped barrier layer has strong blocking ability, can effectively inhibit the diffusion of the atoms of the conductive material, and is conducive to reducing the The occurrence of breakdown phenomenon of the dielectric layer over time is beneficial to improve the reliability of the formed interconnect structure.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 3 to FIG. 7 , schematic structural diagrams corresponding to each step of an embodiment of a method for forming an interconnection structure of the present invention are shown.

Referring to Figure 3, a substrate 100 is provided.

The substrate 100 is used to provide the basis for process operations. In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the material of the substrate can also be selected from polysilicon or amorphous silicon; the substrate can also be selected from silicon, germanium, gallium arsenide or silicon-germanium compounds; the substrate also Other semiconductor materials may be used, or the substrate may also be selected from having an epitaxial layer or a silicon-on-epitaxial layer structure.

It should be noted that, in this embodiment, the substrate 100 is a planar substrate. In other embodiments of the present invention, the substrate may further have semiconductor structures, such as semiconductor structures such as fins.

Continuing to refer to FIG. 3 , a dielectric layer 110 is formed on the substrate 100 .

The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer for realizing electrical isolation between adjacent device layers. In this embodiment, the material of the dielectric layer 110 is an ultra-low K material, such as doped silicon dioxide, an organic polymer, and a porous material. In other embodiments of the present invention, the material of the dielectric layer may also be selected from silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials (dielectric constant greater than or equal to 2.5, less than 3.9) or ultra-low-K dielectric materials (Dielectric constant less than 2.5) in one or more combinations. Specifically, the dielectric layer 110 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, furnace tube, or the like.

Continuing to refer to FIG. 3 , openings 120 are formed in the dielectric layer 110 .

The opening 120 is used for filling and forming an interconnection structure, so as to realize the connection with the external circuit. In this embodiment, the substrate 100 is exposed at the bottom of the opening 120 to realize the connection between the substrate 100 and an external circuit.

It should be noted that, in this embodiment, the formed interconnect structure is a Dual Damascene Structure. Therefore, the opening 120 includes a trench (not marked in the figure), which penetrates a part of the thickness of the dielectric layer 110; and a through hole (not marked in the figure), which is located at the bottom of the trench and penetrates the rest of the The thickness of the dielectric layer 110 exposes the substrate 100 . In other embodiments of the present invention, the formed interconnect structure may also be a Damascus structure (Single Damascene Structure) or other forms of interconnect structures.

Referring to FIG. 4 , a barrier layer 130 is formed on the bottom and sidewalls of the opening 120 , and the barrier layer 130 is a Si-doped barrier layer.

The barrier layer 130 is used to realize the isolation between the formed interconnect structure and the dielectric layer 110 , block the diffusion of the conductive material atoms forming the interconnect structure, and prevent the conductive material atoms from diffusing into the dielectric layer 110 to affect the dielectric layer 110 . Electrical isolation performance. Since the barrier layer 130 is a Si-doped barrier layer, and Si can react with the atoms of the conductive material to form bonds, the Si-doped barrier layer can effectively inhibit the diffusion of the atoms of the conductive material, which is beneficial to improve the barrier layer. The blocking ability of 130 prevents the diffusion of conductive material atoms into the dielectric layer, reduces the time-dependent breakdown phenomenon of the dielectric layer 110, and improves the reliability of the formed interconnect structure. In this embodiment, in the step of forming the barrier layer 130 , the material of the barrier layer 130 is Si-doped TaN.

The step of forming the barrier layer 130 includes: using an atomic layer deposition process to form the barrier layer 130 . Since the layer formed by the atomic layer deposition process has better step coverage, the method of forming the barrier layer 130 by the atomic layer deposition process can reduce the formation of protrusions on the sidewall of the opening 120 away from the substrate 100, reducing the The process difficulty of forming the interconnect structure expands the process window.

Specifically, the barrier layer 130 is a laminated structure, so the steps of forming the barrier layer 130 include: forming a first Si-doped TaN layer 131 on the bottom and sidewalls of the opening 120; A TaN layer 132 is formed on the doped TaN layer 131 ; a second Si-doped TaN layer 133 is formed on the TaN layer 132 .

The first Si-doped TaN layer 131 is used to realize the connection between the barrier layer 130 and the dielectric layer 110 , improve the blocking ability of the barrier layer 130 , and strengthen the barrier layer 130 and the dielectric layer Adhesion between 110; the TaN layer 132 is used to prevent the diffusion of conductive material atoms of the formed interconnect structure; the second Si-doped TaN layer 133 is used to realize the barrier layer 130 and the formed interconnect The connection between the structures is also used for reacting with the conductive material atoms to form bonds, blocking the diffusion of the conductive material atoms, so as to improve the blocking ability of the blocking layer 130 .

At the interface between the barrier layer 130 and the dielectric layer 110 , the Si atoms doped in the first Si-doped TaN layer 131 can form bonds with the materials of the TaN layer 132 and the dielectric layer 110 . TaNSi-O-SiCH, thereby repairing local defects at the interface, improving the density of the barrier layer 130, enhancing the barrier capability of the barrier layer 130, and improving the reliability of the formed interconnect structure. In addition, the doped Si atoms form bonds with the materials of the TaN layer 132 and the dielectric layer 110 , which can also enhance the adhesion between the barrier layer 130 and the dielectric layer 110 .

The doping concentration of Si in the first Si-doped TaN layer 131 should neither be too large nor too small. If the doping concentration of Si in the first Si-doped TaN layer 131 is too small, too few Si atoms can bond with the materials of the TaN layer 132 and the dielectric layer 110 , which will affect the barrier layer 130 If the doping concentration of Si in the first Si-doped TaN layer 131 is too large, the resistance of the formed interconnect structure will be increased. Specifically, in the step of forming the first Si-doped TaN layer 131 , the doping concentration of Si in the first Si-doped TaN layer 131 is in the range of 5% to 15% by atomic percentage.

In addition, since the doped Si atoms react at the interface with the dielectric layer 110 to form bonds, the probability of Si atoms far away from the dielectric layer 110 react with the material of the dielectric layer 110 to form bonds is relatively small, which is very important for increasing the The blocking ability of the blocking layer 130 is weak; and Si atoms far away from the dielectric layer 110 will increase the resistance of the formed interconnect structure. Therefore, in order to control the resistance of the formed interconnect structure, in this embodiment, in the step of forming the first Si-doped TaN layer 131 , along the direction from the dielectric layer 110 to the TaN layer 132 , the Si-doped The impurity concentration gradually decreased.

At the interface between the barrier layer 130 and the interconnect structure, Si atoms doped in the second Si-doped TaN layer 133 can react with the TaN layer 132 and the interconnect structure to form bonds, thereby forming bonds. The blocking ability of the blocking layer 130 is enhanced, and the reliability of the formed interconnect structure is improved. In addition, the doped Si atoms form bonds with the TaN layer 132 and the materials of the interconnect structure, which can also enhance the adhesion between the barrier layer 130 and the dielectric layer 110 .

The doping concentration of Si in the second Si-doped TaN layer 133 should neither be too large nor too small. If the doping concentration of Si in the second Si-doped TaN layer 133 is too small, too few Si atoms that can form bonds with the TaN layer 132 and the interconnect structure material will affect the barrier layer 130. Blocking ability; if the doping concentration of Si in the second Si-doped TaN layer 133 is too large, the resistance of the formed interconnect structure will be increased. Specifically, in the step of forming the second Si-doped TaN layer 133, the doping concentration of Si in the second Si-doped TaN layer 133 is in the range of 5% to 15% by atomic percentage.

In addition, since the doped Si atoms react and form bonds at the interface with the interconnect structure, the Si atoms near the TaN layer 132 have a lower probability of reacting with the interconnect structure material to form bonds, which is beneficial for increasing the barrier layer 130. The effect of blocking ability is weak; and Si atoms close to the TaN layer 132 increase the resistance of the formed interconnect structure. Therefore, in this embodiment, in the step of forming the second Si-doped TaN layer 133 , the doping concentration of Si increases gradually along the direction of the TaN layer 132 toward the opening 120 .

Specifically, the step of forming the first Si-doped TaN layer 131 includes: performing at least one deposition of a first Si-doped material, wherein the step of depositing the first Si-doped material includes: on the bottom and sidewalls of the opening 120 depositing a first Ta-containing material layer; depositing a first Si-containing material layer on the first Ta-containing material layer; depositing a first N-containing material layer on the first Si-containing material layer.

Wherein, the step of depositing the first Si-containing material layer includes: passing in a first Si-containing reactive gas, the first Si-containing reactive gas including silane; and removing the first Si-containing reactive gas.

In this embodiment, the step of forming the first Si-doped TaN layer 131 includes: performing multiple depositions of the first Si-doped material. Therefore, when the first Si-doped material is deposited for many times, the flow rate of the silane introduced into the first Si-containing reaction gas is successively reduced; or, the pulse time for introducing silane is successively reduced; or, the first Si-containing reaction gas is introduced into the reaction gas. The flow rate of silane is successively reduced and the pulse time of silane introduction is successively reduced. This approach can reduce the probability of Si atoms participating in the reaction, reduce the doping concentration of Si atoms in the formed atomic layer, and then make the formed first Si-doped TaN layer 131 point to the TaN along the dielectric layer 110 In the direction of layer 132, the doping concentration of Si gradually decreases.

It should be noted that, in the step of depositing the first Si-doped material multiple times, the flow rate of silane in the first Si-containing reaction gas should not be too large nor too small. If the flow rate of silane in the first Si-containing reaction gas is too large, too little Si will be doped in the formed first Si-doped TaN layer 131, which will affect the blocking ability of the formed barrier layer 130; If the flow rate of silane in the reaction gas is too small, too much Si will be doped in the formed first Si-doped TaN layer 131, which will increase the resistance of the formed interconnect structure. Specifically, in this embodiment, in the steps of depositing the first Si-doped material multiple times, the flow rate of silane in the first Si-containing reaction gas is gradually reduced from 300 sccm to 500 sccm to 50 sccm to 100 sccm.

In the step of depositing the first Si-doped material for many times, the rate at which the pulse time of passing silane is successively reduced should not be too large nor too small. If the rate at which the pulse time of passing silane is gradually decreased is too large, too little Si will be doped in the formed first Si-doped TaN layer 131, which will affect the blocking ability of the formed barrier layer 130; the pulse time of passing silane If the rate of successive reduction is too small, too much Si will be doped in the formed first Si-doped TaN layer 131, which will increase the resistance of the formed interconnect structure. Specifically, in this embodiment, in the step of depositing the first Si-doped material for multiple times, the pulse time for introducing silane is gradually reduced from 300 milliseconds to 500 milliseconds to 50 milliseconds to 100 milliseconds.

It should be noted that, before depositing the first Si-containing material layer, the step of depositing the first Si-doped material further includes: depositing a first Ta-containing material layer on the bottom and sidewalls of the opening 120 . Specifically, the step of depositing the first Ta-containing material layer includes: passing a first Ta-containing reaction gas, wherein the first Ta-containing reaction gas includes penta(dimethylamino) tantalum (V) (Pentakis (dimethylamino) tantalum (V) ), PDMAT); remove the first Ta-containing reaction gas. The technical solution of the step of introducing the first Ta-containing reaction gas is the same as that in the prior art, and details are not described herein again in the present invention.

After depositing the first Si-containing material layer, the step of depositing the first Si-doped material further includes: depositing a first N-containing material layer on the first Si-containing material layer. Specifically, the step of depositing the first N-containing material layer includes: feeding a first N-containing reaction gas, where the first N-containing reaction gas includes ammonia gas; and removing the first N-containing reaction gas. The technical solution of the step of introducing the first N-containing reaction gas is the same as that in the prior art, and details are not described herein again in the present invention.

The step of forming the second Si-doped TaN layer 133 includes: performing at least one deposition of a second Si-doped material, wherein the step of depositing the second Si-doped material includes: depositing a second Ta-containing material on the TaN layer 132 layer; depositing a second Si-containing material layer on the second Ta-containing material layer; depositing a second N-containing material layer on the second Si-containing material layer.

Wherein, the step of depositing the second Si-containing material layer includes: passing a second Si-containing reactive gas, the second Si-containing reactive gas including silane; and removing the second Si-containing reactive gas.

In this embodiment, the step of forming the second Si-doped TaN layer 133 includes: performing multiple depositions of the second Si-doped material. Therefore, when the deposition of the second Si-doped material is performed for several times, the flow rate of the silane introduced into the second Si-containing reaction gas is gradually increased; or, the pulse time for introducing silane is gradually increased; The flow rate of silane was increased successively and the pulse time of silane introduction was successively increased. This approach can increase the probability of Si atoms participating in the reaction, increase the doping concentration of Si atoms in the formed atomic layer, and then make the formed first Si-doped TaN layer 131 point to the opening along the TaN layer 132 In the direction of 120, the doping concentration of Si increases gradually.

It should be noted that, in the step of depositing the second Si-doped material multiple times, the flow rate of silane in the second Si-containing reaction gas should not be too large nor too small. If the flow rate of silane in the second Si-containing reaction gas is too large, too much Si will be doped in the formed second Si-doped TaN layer 133, which will increase the resistance of the formed interconnect structure; If the flow rate of silane in the reaction gas is too small, the blocking ability of the formed barrier layer 130 will be affected. Specifically, in this embodiment, in the steps of depositing the first Si-doped material multiple times, the flow rate of silane in the second Si-containing reaction gas is gradually increased from 50 sccm to 100 sccm to 300 sccm to 500 sccm.

In the step of performing multiple depositions of the second Si-doped material, the rate at which the pulse time of passing silane is gradually increased should not be too large nor too small. If the rate of successively increasing the pulse time of silane feeding is too large, too much Si will be doped in the formed second Si-doped TaN layer 133, which will increase the resistance of the formed interconnect structure; pulse time of silane feeding If the successively increasing rate is too small, too little Si will be doped in the formed second Si-doped TaN layer 133 , which will affect the blocking ability of the formed barrier layer 130 . Specifically, in this embodiment, in the step of performing multiple depositions of the second Si-doped material, the pulse time for introducing silane is gradually increased from 50 milliseconds to 100 milliseconds to 300 milliseconds to 500 milliseconds.

It should be noted that, after forming the TaN layer 132 and before depositing the second Ta-containing material layer, the step of depositing the second Si-doped material further includes: depositing a second Ta-containing material layer on the TaN layer 132 . Specifically, the step of depositing the second Ta-containing material layer includes: passing a second Ta-containing reactive gas, the second Ta-containing reactive gas including Pentakis (dimethylamino) tantalum (V) ), PDMAT); remove the second Ta-containing reaction gas. The technical solution of the step of introducing the second Ta-containing reaction gas is the same as that in the prior art, and details are not described herein again in the present invention.

After depositing the second Ta-containing material layer, the step of depositing the second Si-doped material further includes: depositing a second N-containing material layer on the second Si-containing material layer. Specifically, the step of depositing the second N-containing material layer includes: feeding a second N-containing reaction gas, where the second N-containing reaction gas includes ammonia gas; and removing the second N-containing reaction gas. The technical solution of the step of introducing the second N-containing reaction gas is the same as that in the prior art, and details are not described herein again in the present invention.

It should be noted that the number of times of depositing the first Si-doped material is related to the thickness of the first Si-doped TaN layer 131 formed; the number of times of depositing the second Si-doped TaN layer 133 thickness related. Therefore, according to the preset thickness of the first Si-doped TaN layer 131 and the preset thickness of the second Si-doped TaN layer 133, the number of times to deposit the first Si-doped material and the number of times to deposit the second Si-doped material are determined, and The process parameters (eg, the flow rate of the first Si-containing reactive gas and the pulse time of the silane) are set within reasonable ranges to improve the performance of the formed interconnect structure.

到

范围内。The thickness of the first Si-doped TaN layer 131 should neither be too large nor too small. If the thickness of the first Si-doped TaN layer 131 is too large, the space of the remaining openings 120 will be too small, and the aspect ratio of the openings 120 will be increased, thereby increasing the difficulty of the subsequent filling of the conductive material; If the thickness of the first Si-doped TaN layer 131 is too small, the blocking ability of the formed barrier layer 130 will be affected, which is not conducive to increasing the blocking ability of the blocking layer 130 . Specifically, in this embodiment, in the step of forming the first Si-doped TaN layer 131, the thickness of the first Si-doped TaN layer 131 is

arrive

within the range.

到

范围内。The thickness of the TaN layer 132 should neither be too large nor too small. If the thickness of the TaN layer 132 is too large, the space of the remaining openings 120 will be too small, the aspect ratio of the openings 120 will be increased, and the process difficulty of subsequent filling of conductive materials will be increased; if the TaN layer If the thickness of 132 is too small, the blocking ability of the formed barrier layer 130 will be affected. Specifically, in this embodiment, in the step of forming the TaN layer 132, the thickness of the TaN layer 132 is

arrive

within the range.

到

范围内。The thickness of the second Si-doped TaN layer 133 should neither be too large nor too small. If the thickness of the second Si-doped TaN layer 133 is too large, the space of the remaining openings 120 will be too small, and the aspect ratio of the openings 120 will be increased, thereby increasing the difficulty of the subsequent filling of the conductive material; If the thickness of the second Si-doped TaN layer 133 is too small, the blocking ability of the formed barrier layer 130 will be affected, which is not conducive to increasing the blocking ability of the blocking layer 130 . Specifically, in this embodiment, in the step of forming the second Si-doped TaN layer 133, the thickness of the second Si-doped TaN layer 133 is

arrive

within the range.

It should also be noted that in the step of forming the barrier layer 130, the thickness of the first Si-doped TaN layer 131, the thickness of the TaN layer and the ratio of the second Si-doped TaN layer 133 will affect The resistance of the formed interconnect structure and the blocking ability of the barrier layer 130 also affect the adhesion between the barrier layer 130 and the dielectric layer 110 and the barrier layer 130 and the interconnect structure.

If the barrier layer 130 is formed, the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 account for an excessively large proportion, that is, the thickness of the first Si-doped TaN layer 131 and the If the proportion of the thickness of the second Si-doped TaN layer 133 to the total thickness of the barrier layer 130 is too large, the resistance of the formed interconnect structure will be too large; if the barrier layer 130 is formed, the first Si The proportions of the doped TaN layer 131 and the second Si-doped TaN layer 133 are too small, that is, the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 account for If the proportion of the total thickness of the barrier layer 130 is too small, it is not conducive to improving the barrier capability of the barrier layer 130 and also affects the adhesion between the barrier layer 130 and the dielectric layer 110 and the interconnect structure. In this embodiment, in the step of forming the barrier layer, the ratio of the thickness of the first Si-doped TaN layer 131 to the thickness of the TaN layer 132 and the thickness of the second Si-doped TaN layer 133 is 1:1:1 to 2:1:2 range.

It should be noted that, referring to FIG. 5 , in order to improve the blocking capability of the blocking layer 130 , in this embodiment, after the second Si-doped TaN layer 133 is formed, the bottom and sidewalls of the opening 120 are formed. The step of the barrier layer 130 further includes: forming a supplementary TaN layer 134 on the second Si-doped TaN layer 133 ; and forming an adhesion layer 135 on the supplementary TaN layer 134 .

The supplementary TaN layer 134 is used to block the atomic diffusion of the conductive material to enhance the blocking ability of the barrier layer 130 ; the adhesion layer 134 is used to realize the connection between the subsequently formed interconnect structure and the barrier layer 130 . connection, improving the adhesion between the formed barrier layer 130 and the interconnect structure.

In the step of forming the adhesion layer 135, the material of the adhesion layer 135 is Ta. Specifically, one or both of the steps of forming the supplemental TaN layer 134 and the step of forming the adhesion layer 135 include: using a physical vapor deposition process to form. In this embodiment, the supplementary TaN layer 134 and the adhesion layer 135 are formed by a physical vapor deposition process.

到

范围内。It should be noted that the thicknesses of the supplementary TaN layer 134 and the adhesion layer 135 should not be too large nor too small. If the thickness of the supplementary TaN layer 134 is too large, the space of the remaining openings 120 will be too small, thereby increasing the aspect ratio of the openings 120, thereby increasing the difficulty of the subsequent filling of conductive materials; the supplementary TaN layer If the thickness of 134 is too small, it is not conducive to enhancing the blocking capability of the blocking stack 130 . Specifically, in the step of forming the supplementary TaN layer 134, the thickness of the supplementary TaN layer 134 is

arrive

within the range.

到

范围内。If the thickness of the adhesive layer 135 is too large, the space for the remaining openings 120 will be too small, thereby increasing the aspect ratio of the openings 120, thereby increasing the difficulty of the subsequent process of filling conductive materials; the adhesive layer If the thickness of 135 is too small, the adhesion between the formed barrier stack 130 and the interconnect structure may be affected. Specifically, in the step of forming the adhesive layer 135, the thickness of the adhesive layer 135 is

arrive

within the range.

It should be noted that, in other embodiments of the present invention, the connection between the interconnection structure and the dielectric layer can also be realized directly through the second Si-doped TaN layer, thereby reducing the thickness of the formed barrier layer and expanding the The size of the opening reduces the process difficulty of filling the conductive material and expands the process window.

Referring to FIGS. 6 to 7 , the opening 120 (shown in FIG. 5 ) having the barrier layer 130 formed on the bottom and sidewalls of the opening 120 (shown in FIG. 5 ) is filled with a conductive material to form an interconnect structure 150 (shown in FIG. 7 ).

In this embodiment, the interconnection structure 150 is a double damascene structure, and the opening 120 includes a trench (not shown in the figure) and a through hole (not shown in the figure) at the bottom of the trench, so the interconnection structure 150 includes a plug (not shown in the figure) located in the through hole and a connection line (not shown in the figure) located in the groove.

Specifically, the steps of forming the interconnect structure 150 include:

Referring to FIG. 6 , a conductive material is filled into the opening 120 (as shown in FIG. 5 ) with the barrier layer 130 formed on the bottom and the sidewall to form a conductive layer 151 .

The conductive layer 151 is used to form an interconnect structure for connection with external circuits. In this embodiment, the conductive material is Cu, so the material of the formed conductive layer 151 is Cu.

Therefore, at the interface between the barrier layer 130 and the conductive layer 151, the Si atoms doped in the second Si-doped TaN layer 133 can bond with the TaN layer 132 and the conductive material to form Cu- Si-TaN, thereby inhibiting the diffusion of the conductive material atoms, improving the blocking ability of the barrier layer 130, and improving the reliability of the formed interconnect structure 150; in addition, Si atoms are closely related to the TaN layer 132 and the conductive material. Bonding to form Cu-Si-TaN can also enhance the adhesion between the TaN layer 132 and the conductive material.

Specifically, the step of forming the conductive layer 151 includes: forming a seed layer on the bottom and sidewalls of the opening 120; Conductive layer 151 .

Referring to FIG. 7 , an annealing process 140 is performed on the barrier layer 130 and the conductive layer 151 (as shown in FIG. 6 ) to form an interconnection structure 150 .

The annealing treatment 140 is used for forming the interconnection structure 150, and is also used for diffusing Si atoms in the barrier layer 130, so that the Si atoms react with the dielectric layer 110 and the interconnection structure 150 to form bonds, so as to improve the performance of the interconnection structure 150. The blocking ability of the blocking layer 130 is improved, and the adhesion of the blocking layer 130 to the dielectric layer 110 and the interconnection structure 150 is improved. Specifically, at the interface between the first Si-doped TaN layer 131 and the dielectric layer 110 and at the interface between the first Si-doped TaN layer 131 and the TaN layer 132 , the annealing process 140 makes the Si atoms diffuse into the dielectric layer 110 and the TaN layer 132, and the Si atoms react with TaN and O, C, and H locally to form bonds to form TaNSi-O-SiCH, so as to repair the connection between the TaN layer 132 and the TaN layer 132. Defects at the interface of the dielectric layer 110 are improved, the density of the TaN layer 132 is improved, and the blocking ability of the TaN layer 132 is enhanced, which is beneficial to improve the blocking ability of the blocking layer 130 and improve the reliability of the interconnect structure 150. sex.

At the interface between the second Si-doped TaN layer 133 and the TaN layer 132 and at the interface between the second Si-doped TaN layer 133 and the interconnect structure 150 , the annealing process 140 causes silicon atoms Diffusion into the TaN layer 132 and the interconnect structure 150, and Si atoms react with TaN and Cu atoms to form bonds to form Cu-Si-TaN, thereby inhibiting the diffusion of Cu atoms and improving the TaN layer 132 and the The adhesion of the interconnection structure 150 is beneficial to improve the blocking ability of the barrier layer 130 and improve the reliability of the interconnection structure 150 .

Specifically, in the step of performing the annealing treatment 140, the annealing temperature should not be too high nor too high. If the annealing temperature is too high, it will cause unnecessary process risks and increase the possibility of damage to other semiconductor structures on the substrate 100; if the annealing temperature is too low, it will affect the diffusion of Si atoms, which is not conducive to Si atoms and the TaN The material atoms of the layer 132 and the interconnect structure 150 react to form bonds, which is not conducive to improving the blocking ability of the formed barrier layer 130, nor is it conducive to improving the barrier layer 130, the interconnect structure 150 and the dielectric layer 110. Adhesion. Specifically, in the step of performing the annealing treatment, the annealing temperature is in the range of 300°C to 375°C.

The annealing time should neither be too long nor too short. If the annealing time is too long, it will cause unnecessary process risks and increase the possibility of damage to other semiconductor structures on the substrate 100; if the annealing time is too short, the silicon atoms cannot be fully diffused, which is not conducive to the Si atoms and the TaN layer. 132 and the material atoms of the interconnect structure 150 react to form bonds, which is not conducive to improving the blocking ability of the formed barrier layer 130, nor is it conducive to improving the adhesion between the barrier layer 130 and the interconnect structure 150 and the dielectric layer 110. Attachment. Specifically, in the step of performing the annealing treatment, the annealing time is in the range of 3 minutes to 6 minutes.

It should be noted that, in this embodiment, in the step of forming the conductive layer 151, the conductive layer 151 is also located on the dielectric layer 110; and in the step of forming the barrier layer 130, the barrier layer 130 Also on the dielectric layer 110 . Therefore, after the conductive layer 151 is formed and before the annealing process 140 is performed, the forming method further includes: performing a planarization process to remove the conductive layer 151 and the barrier layer 130 on the dielectric layer 110 to form the opening 120 (shown in FIG. 5 ) interconnect structure 150 within.

Specifically, the planarization process is performed by chemical mechanical polishing, and the planarization process stops until the surface of the dielectric layer 110 is exposed.

Correspondingly, the present invention also provides an interconnection structure. Referring to FIG. 7 , a schematic structural diagram of an embodiment of the interconnection structure of the present invention is shown.

The interconnect structure includes: a substrate 100; a dielectric layer 110 located on the substrate 100; an interconnect structure 150 located in the dielectric layer 110; between the interconnect structure 150 and the dielectric layer 110 A barrier layer 130 between them is formed, and the barrier layer 130 is a Si-doped barrier layer.

The substrate 100 is used to provide the basis for process operations. In this embodiment, the material of the substrate 100 is single crystal silicon. In other embodiments of the present invention, the material of the substrate can also be selected from polysilicon or amorphous silicon; the substrate can also be selected from silicon, germanium, gallium arsenide or silicon-germanium compounds; the substrate also Other semiconductor materials may be used, or the substrate may also be selected from having an epitaxial layer or a silicon-on-epitaxial layer structure.

It should be noted that, in this embodiment, the substrate 100 is a planar substrate. In other embodiments of the present invention, the substrate may further have semiconductor structures, such as semiconductor structures such as fins.

The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer for realizing electrical isolation between adjacent device layers. The material of the dielectric layer 110 can be selected from silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials (dielectric constant greater than or equal to 2.5, less than 3.9) or ultra-low-K dielectric materials (dielectric constant less than 2.5) One or more combinations of . In this embodiment, the material of the dielectric layer 110 is an ultra-low K material, such as doped silicon dioxide, an organic polymer, and a porous material.

The interconnect structure 150 is used to realize connection with external circuits. Specifically, the interconnection structure 150 is a dual damascene structure, so the interconnection structure 150 includes a plug (not marked in the figure) located in the through hole and a connection line located in the trench (in the figure) not marked). In this embodiment, the material of the interconnect structure 150 is a conductive material, such as Cu.

The barrier layer 130 is used to realize the isolation between the interconnect structure and the dielectric layer 110 , block the diffusion of the conductive material atoms forming the interconnect structure, and prevent the conductive material atoms from diffusing into the dielectric layer 110 to affect the dielectric layer 110 . Electrical isolation performance.

Since the barrier layer 130 is a Si-doped barrier layer, and Si can react with the atoms of the conductive material to form bonds, the Si-doped barrier layer can effectively inhibit the diffusion of the atoms of the conductive material, which is beneficial to improve the barrier layer. The blocking ability of the 130 prevents the conductive material atoms from diffusing into the dielectric layer, reduces the time-dependent breakdown phenomenon of the dielectric layer 130, and improves the reliability of the interconnect structure 150. In this embodiment, the material of the barrier layer 130 is Si-doped TaN.

The barrier layer 130 is a stacked structure, including: a first Si-doped TaN layer 131 located between the dielectric layer 110 and the interconnect structure 150; The TaN layer 132 between the interconnection structures 150 ; the second Si-doped TaN layer 133 between the TaN layer 132 and the interconnection structure 150 .

The first Si-doped TaN layer 131 is used to realize the connection between the barrier layer 130 and the dielectric layer 110 , improve the blocking ability of the barrier layer 130 , and strengthen the barrier layer 130 and the dielectric layer Adhesion between 110; the TaN layer 132 is used to prevent the diffusion of conductive material atoms of the interconnection structure 150; the second Si-doped TaN layer 133 is used to realize the barrier layer 130 and the interconnection The connection between the connecting structures 150 is also used for reacting with the conductive material atoms to form bonds, blocking the diffusion of the conductive material atoms, so as to improve the blocking ability of the blocking layer 130 .

At the interface between the barrier layer 130 and the dielectric layer 110 , the Si atoms doped in the first Si-doped TaN layer 131 can form bonds with the materials of the TaN layer 132 and the dielectric layer 110 . TaNSi-O-SiCH, thereby repairing local defects at the interface, improving the density of the barrier layer 130 , enhancing the barrier capability of the barrier layer 130 , and improving the reliability of the interconnect structure 150 . In addition, the doped Si atoms form bonds with the materials of the TaN layer 132 and the dielectric layer 110 , which can also enhance the adhesion between the barrier layer 130 and the dielectric layer 110 .

Specifically, at the interface between the first Si-doped TaN layer 131 and the dielectric layer 110 and at the interface between the first Si-doped TaN layer 131 and the TaN layer 132 , Si atoms diffuse into the In the dielectric layer 110 and the TaN layer 132 , Si atoms react with TaN and O, C and H locally to form bonds to form TaNSi-O-SiCH, thereby repairing the interface between the TaN layer 132 and the dielectric layer 110 Therefore, the density of the TaN layer 132 is increased, and the blocking ability of the TaN layer 132 is enhanced, which is beneficial to improve the blocking ability of the blocking layer 130 and improve the reliability of the interconnect structure 150 .

At the interface between the barrier layer 130 and the interconnect structure 150, Si atoms doped in the second Si-doped TaN layer 133 can react with the TaN layer 132 and the interconnect structure to form bonds, Therefore, the blocking capability of the blocking layer 130 is enhanced, and the reliability of the interconnection structure 150 is improved. In addition, the doped Si atoms form bonds with the TaN layer 132 and the materials of the interconnect structure 150 , which can also enhance the adhesion between the barrier layer 130 and the dielectric layer 110 .

At the interface between the second Si-doped TaN layer 133 and the TaN layer 132 and at the interface between the second Si-doped TaN layer 133 and the interconnect structure 150, Si atoms diffuse into the TaN layer 132 and the interconnect structure 150, Si atoms react with TaN and Cu atoms to form bonds to form Cu-Si-TaN, thereby improving the adhesion between the TaN layer 132 and the interconnect structure 150, which is beneficial to improve the The blocking capability of the blocking layer 130 improves the reliability of the interconnect structure 150 .

The doping concentration of Si in the first Si-doped TaN layer 131 should neither be too large nor too small. If the doping concentration of Si in the first Si-doped TaN layer 131 is too small, too few Si atoms can bond with the materials of the TaN layer 132 and the dielectric layer 110 , which will affect the barrier layer 130 If the doping concentration of Si in the first Si-doped TaN layer 131 is too large, the resistance of the interconnect structure 150 will be increased. Specifically, in terms of atomic percentage, the doping concentration of Si in the first Si-doped TaN layer 131 is in the range of 5% to 15%.

In addition, since the doped Si atoms react at the interface with the dielectric layer 110 to form bonds, the probability of Si atoms far away from the dielectric layer 110 react with the material of the dielectric layer 110 to form bonds is relatively small, which is very important for increasing the The blocking ability of the blocking layer 130 is weak; and Si atoms far away from the dielectric layer 110 will increase the resistance of the interconnection structure 150 . Therefore, in order to control the resistance of the interconnection structure 150 , in this embodiment, the doping concentration of Si is gradually reduced along the direction of the dielectric layer 110 toward the TaN layer 132 .

The doping concentration of Si in the second Si-doped TaN layer 133 should neither be too large nor too small. If the doping concentration of Si in the second Si-doped TaN layer 133 is too small, too few Si atoms can bond with the TaN layer 132 and the material of the interconnect structure 150 , which will affect the barrier layer 130 If the doping concentration of Si in the second Si-doped TaN layer 133 is too large, the resistance of the interconnection structure 150 will be increased. Specifically, in terms of atomic percentage, the doping concentration of Si in the second Si-doped TaN layer 133 is in the range of 5% to 15%.

In addition, since the doped Si atoms react at the interface with the interconnect structure 150 to form bonds, the Si atoms near the TaN layer 132 have a lower probability of reacting with the material of the interconnect structure 150 to form bonds, which increases The blocking ability of the blocking layer 130 is weak; and Si atoms close to the TaN layer 132 increase the resistance of the interconnect structure 150 . Therefore, in the present embodiment, in the second Si-doped TaN layer 133 , along the direction from the TaN layer 132 to the interconnection structure 150 , the doping concentration of Si gradually decreases and increases.

到

范围内。The thickness of the first Si-doped TaN layer 131 should neither be too large nor too small. If the thickness of the first Si-doped TaN layer 131 is too large, the process difficulty of filling conductive materials will increase; if the thickness of the first Si-doped TaN layer 131 is too small, the barrier layer will be affected The blocking ability of the blocking layer 130 is not conducive to increasing the blocking ability of the blocking layer 130 . Specifically, in this embodiment, the thickness of the first Si-doped TaN layer 131 is

arrive

within the range.

到

范围内。The thickness of the TaN layer 132 should neither be too large nor too small. If the thickness of the TaN layer 132 is too large, it will increase the difficulty of filling the conductive material; if the thickness of the TaN layer 132 is too small, the blocking ability of the barrier layer 130 will be affected. Specifically, in this embodiment, the thickness of the TaN layer 132 is

arrive

within the range.

到

范围内。The thickness of the second Si-doped TaN layer 133 should neither be too large nor too small. If the thickness of the second Si-doped TaN layer 133 is too large, the space of the remaining openings 120 will be too small, and the aspect ratio of the openings 120 will be increased, thereby increasing the difficulty of the subsequent filling of the conductive material; If the thickness of the second Si-doped TaN layer 133 is too small, the blocking ability of the barrier layer 130 will be affected, which is not conducive to increasing the blocking ability of the blocking layer 130 . Specifically, in this embodiment, the thickness of the second Si-doped TaN layer 133 is

arrive

within the range.

It should also be noted that the thickness of the first Si-doped TaN layer 131 , the thickness of the TaN layer 132 and the ratio of the second Si-doped TaN layer 133 will affect the resistance and The blocking ability of the blocking layer 130 also affects the adhesion between the blocking layer 130 and the dielectric layer 110 and the blocking layer 130 and the interconnection structure 150 .

If the first Si-doped TaN layer 131 and the second Si-doped TaN layer 133 account for an excessively large proportion of the barrier layer 130, that is, the thickness of the first Si-doped TaN layer 131 and the If the proportion of the thickness of the second Si-doped TaN layer 133 to the total thickness of the barrier layer 130 is too large, the resistance of the interconnect structure 150 will be too large; The proportions of the Si-doped TaN layer 131 and the second Si-doped TaN layer 133 are too small, that is, the thickness of the first Si-doped TaN layer 131 and the thickness of the second Si-doped TaN layer 133 account for If the proportion of the total thickness of the barrier layer 130 is too small, it is not conducive to improving the barrier capability of the barrier layer 130 , and also affects the adhesion between the barrier layer 130 , the dielectric layer 110 and the interconnect structure 150 . sex. In this embodiment, the ratio of the thickness of the first Si-doped TaN layer 131 to the thickness of the TaN layer 132 and the thickness of the second Si-doped TaN layer 133 is 1:1:1 to 2:1 :2 range.

It should be noted that, in order to improve the blocking capability of the barrier layer 130 , in this embodiment, the barrier layer 130 further includes: a barrier between the second Si-doped TaN layer 133 and the interconnect structure 150 Supplemental TaN layer 134 ; and adhesion layer 135 between said supplemental TaN layer 134 and said interconnect structure 150 . Specifically, the material of the adhesion layer 135 is tantalum.

The supplementary TaN layer 134 is used to block the atomic diffusion of the conductive material to enhance the blocking ability of the barrier layer 130 ; the adhesion layer 134 is used to realize the gap between the interconnect structure 150 and the barrier layer 130 connection, and improve the adhesion between the barrier layer 130 and the interconnection structure 150 .

到

范围内。It should be noted that the thicknesses of the supplementary TaN layer 134 and the adhesion layer 135 should not be too large nor too small. If the thickness of the supplementary TaN layer 134 is too large, the space of the remaining openings 120 will be too small, thereby increasing the aspect ratio of the openings 120, thereby increasing the difficulty of the subsequent filling of conductive materials; the supplementary TaN layer If the thickness of the barrier layer 134 is too small, it is not conducive to enhancing the barrier capability of the barrier layer 130 . Specifically, the thickness of the supplementary TaN layer 134 is

arrive

within the range.

到

范围内。If the thickness of the adhesive layer 135 is too large, the space for the remaining openings 120 will be too small, thereby increasing the aspect ratio of the openings 120, thereby increasing the difficulty of the subsequent process of filling conductive materials; the adhesive layer If the thickness of 135 is too small, the adhesion between the barrier layer 130 and the interconnection structure 150 will be affected. Specifically, the thickness of the adhesive layer 135 is

arrive

within the range.

It should be noted that, in other embodiments of the present invention, the connection between the interconnection structure 150 and the dielectric layer can also be realized directly through the second Si-doped TaN layer, thereby reducing the thickness of the barrier layer, The size of the opening is enlarged, the process difficulty of filling the conductive material is reduced, and the process window is enlarged.

To sum up, the barrier layer formed on the bottom and sidewalls of the opening in the technical solution of the present invention is a Si-doped barrier layer; and then an interconnection structure is formed in the opening in which the barrier layer is formed. Since the barrier layer is doped with Si, the Si atoms can react with the atoms of the conductive material forming the interconnection structure to form bonds, so the Si-doped barrier layer has strong blocking ability, can effectively inhibit the diffusion of the atoms of the conductive material, and is conducive to reducing the The occurrence of breakdown phenomenon of the dielectric layer over time is beneficial to improve the reliability of the formed interconnect structure. Furthermore, in an optional solution of the present invention, the barrier layer is a laminated structure, including a first Si-doped TaN layer on the bottom and sidewalls of the opening, and a TaN layer on the first Si-doped TaN layer. layer and a second Si-doped TaN layer on the TaN layer. Since Si, C, O, and TaN can react locally to form TaNSi-O-SiCH, the first Si-doped TaN layer can repair the defects on the interface between the TaN layer and the dielectric layer, thereby improving the relationship between the barrier layer and the dielectric layer. The adhesion of the dielectric layer; Si, Cu and TaN can react to form TaN-Si-Cu, so the second Si-doped TaN layer can improve the adhesion between the barrier layer and the interconnect structure; Therefore, the formation of the first Si-doped TaN layer and the second Si-doped TaN layer effectively improves the adhesion between the barrier layer and the dielectric layer and between the barrier layer and the interconnect structure The adhesion is beneficial to improve the reliability of the interconnect structure. In addition, in an optional solution of the present invention, the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can all be formed by atomic deposition. The step coverage of the layers is better, so the first Si-doped TaN layer, the TaN layer and the second Si-doped TaN layer can better cover the bottom and sidewalls of the opening, which is beneficial to reduce filling The process difficulty of conductive materials is conducive to expanding the process window.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (17)

1. A method for forming an interconnect structure, comprising: provide a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; A barrier layer is formed on the bottom and sidewalls of the opening, the barrier layer is a Si-doped barrier layer, and the barrier layer is a stacked layer structure, and the step of forming the barrier layer includes: forming the barrier layer on the bottom and sides of the opening forming a first Si-doped TaN layer on the wall, forming a TaN layer on the first Si-doped TaN layer, and forming a second Si-doped TaN layer on the TaN layer; A conductive material is filled in the opening with the barrier layer formed on the bottom and the sidewall to form an interconnection structure. The step of forming the interconnection structure includes: filling the opening with the barrier layer on the bottom and the sidewall with a conductive material to form a conductive layer ; annealing the barrier layer and the conductive layer to form an interconnect structure and to diffuse silicon atoms in the barrier layer. 2 . The method of claim 1 , wherein the step of forming the barrier layer comprises: using an atomic layer deposition process to form the barrier layer. 3 . 3 . The method of claim 1 , wherein in the step of forming the barrier layer, the material of the barrier layer comprises Si-doped TaN. 4 . 4. The formation method according to claim 1, wherein in the step of forming the first Si-doped TaN layer, the doping concentration of Si in the first Si-doped TaN layer is based on atomic percentage in the range of 5% to 15%; In the step of forming the second Si-doped TaN layer, the doping concentration of Si in the second Si-doped TaN layer is in the range of 5% to 15% by atomic number percentage. 5 . The method of claim 1 , wherein in the step of forming the first Si-doped TaN layer, the doping concentration of Si is gradually increased along the direction from the dielectric layer to the TaN layer. 6 . reduce; In the step of forming the second Si-doped TaN layer, the doping concentration of Si is gradually increased along the direction of the TaN layer toward the opening. 6. The method of claim 1, wherein the step of forming the first Si-doped TaN layer comprises: performing at least one deposition of a first Si-doped material, wherein the step of depositing the first Si-doped material including: depositing a first Ta-containing material layer on the bottom and sidewalls of the opening; depositing a first Si-containing material layer on the first Ta-containing material layer; depositing a first Si-containing material layer on the first Si-containing material layer an N-containing material layer; wherein, the step of depositing the first Si-containing material layer includes: feeding a first Si-containing reaction gas, the first Si-containing reaction gas including silane; removing the first Si-containing reaction gas; The step of forming the second Si-doped TaN layer includes: performing at least one deposition of a second Si-doped material, wherein the step of depositing the second Si-doped material includes: depositing a second Ta-containing material layer on the TaN layer; depositing a second Si-containing material layer on the second Ta-containing material layer; depositing a second N-containing material layer on the second Si-containing material layer; wherein, the step of depositing the second Si-containing material layer includes: A second Si-containing reaction gas is introduced, and the second Si-containing reaction gas includes silane; and the second Si-containing reaction gas is removed. 7 . The method according to claim 6 , wherein the step of depositing the first Si-doped material multiple times comprises: reducing the flow rate of the silane in the first Si-containing reaction gas; The step of depositing the Si-doped material includes: the flow rate of the silane in the second Si-containing reaction gas is gradually increased; Alternatively, the step of performing multiple depositions of the first Si-doped material includes: successively decreasing the pulse time for supplying silane; and the step of performing multiple depositions of the second Si-doped material includes: increasing the pulse time for supplying silane. 8 . The method of claim 1 , wherein in the step of forming the barrier layer, the thickness of the first Si-doped TaN layer, the thickness of the TaN layer and the second Si-doped The ratio of the thickness of the hetero TaN layer is in the range of 1:1:1 to 2:1:2. 9. The method of claim 1, wherein in the step of forming the first Si-doped TaN layer, the thickness of the first Si-doped TaN layer is between

arrive

within the range; In the step of forming the TaN layer, the thickness of the TaN layer is

arrive

within the range; In the step of forming the second Si-doped TaN layer, the thickness of the second Si-doped TaN layer is

arrive

within the range. 10 . The method of claim 1 , wherein, in the step of forming the dielectric layer, the material of the dielectric layer is an ultra-low K material. 11 . 11. The method of claim 1, wherein in the step of forming the interconnect structure, the conductive material is Cu. 12. An interconnect structure, characterized in that it comprises: substrate; a dielectric layer on the substrate; an interconnect structure within the dielectric layer; A barrier layer located between the interconnection structure and the dielectric layer, the barrier layer is a Si-doped barrier layer, and the barrier layer is a stacked structure; the barrier layer comprises: located between the dielectric layer and the dielectric layer. A first Si-doped TaN layer between the interconnect structures; a TaN layer between the first Si-doped TaN layer and the interconnect structure; between the TaN layer and the interconnect structure a second Si-doped TaN layer in between; The silicon atoms in the barrier layer diffuse through the annealing process. 13. The interconnect structure of claim 12, wherein the material of the barrier layer is Si-doped TaN. 14. The interconnect structure of claim 12, wherein the ratio of the thickness of the first Si-doped TaN layer, the thickness of the TaN layer, and the thickness of the second Si-doped TaN layer is 1:1:1 to 2:1:2 range. 15 . The interconnect structure of claim 12 , wherein, in the first Si-doped TaN layer, along the direction from the dielectric layer to the TaN layer, the doping concentration of Si gradually decreases. 16 . ; In the second Si-doped TaN layer, along the direction from the TaN layer to the interconnect structure, the doping concentration of Si gradually decreases and increases. 16. The interconnect structure of claim 12, wherein the doping concentration of Si in the first Si-doped TaN layer is in the range of 5% to 15% by atomic number percentage; The doping concentration of Si in the second Si-doped TaN layer is in the range of 5% to 15% in atomic percentage. 17. The interconnect structure of claim 12, wherein the thickness of the first Si-doped TaN layer is between

arrive

range; the thickness of the TaN layer is

arrive

range; the thickness of the second Si-doped TaN layer is

arrive

within the range.

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