CN108052292A - A kind of high-temperature protection method of solid state disk - Google Patents

Abstract

The present invention relates to the field of storage technology. The embodiment of the present invention discloses a high temperature protection method for a solid-state hard disk. The method includes: detecting the temperature of the solid-state hard disk, and reasonably and efficiently limiting the bandwidth of the solid-state hard disk according to the temperature information fed back and ensuring Other performance indicators of solid-state drives. In this way, the present invention aims at some special application scenarios of solid-state hard drives, such as the ambient temperature as high as 40°C to 100°C, avoiding the abnormal mode of solid-state hard drives under high-temperature conditions, and preventing the solid-state hard drives from burning out due to excessive temperatures, resulting in data loss. It greatly enhances the reliability of solid-state hard drives and solves the technical difficulties of solid-state hard drives under high temperature.

Description

A kind of high temperature protection method of solid state hard disk

technical field

The invention relates to the technical field of electronic memory, in particular to a high-temperature protection method for a solid-state hard disk.

Background technique

With the continuous development of electronic information technology, the demand for big data storage continues to drive the rapid development of flash memory in the direction of larger scale, higher density and higher reliability. Solid State Drive (SSD, Solid State Driver) is a non-volatile storage device, which has the characteristics of long-term data storage, fast data update, and massive data storage, which can meet the needs of big data storage in various industries. Solid-state hard drives use high-density, large-capacity NAND Flash as storage media, which have the advantages of fast access speed and large storage capacity, and are widely used in military, aerospace, consumer, industrial control, monitoring and many other fields. Solid-state hard drives are mainly composed of host communication interfaces, SSD controllers, NAND Flash storage media, and power-related circuits. Among them, the host communication interfaces, SSD controllers, and NAND Flash storage media directly determine the performance of solid-state hard drives. The host communication interface is used as the communication interface between the host and the solid-state hard drive to complete command interaction and data transmission functions. The current mainstream communication interfaces of solid-state hard drives include SATA, AHCI, and NVME. The SSD controller is mainly used for the transfer of data between the host communication interface and the NAND Flash storage medium; the NAND Flash storage medium realizes the storage of data, and the performance of the NAND Flash storage medium plays a vital role in the solid-state hard disk, directly restricting affects the performance of the entire SSD.

As the application scenarios of solid-state drives become more and more complex, when the working environment temperature is 60-100°C, considering the power consumption of the solid-state drive itself, the disk temperature of the solid-state drive may exceed the maximum operating capacity of the solid-state drive controller or storage medium. temperature, causing the solid-state drive to fail to work normally, resulting in loss of user data, and even permanent damage to the solid-state drive. The high temperature of the solid-state disk is mainly caused by the working environment temperature and the power consumption generated by the disk itself during business operation. The working environment temperature is determined by the user, so a method is needed to ensure that the disk can work normally in a high-temperature environment. At the same time, try to take into account the performance of the disc, which can only be achieved by adjusting the performance of the disc.

The performance of SSD disks is mainly reflected in the bandwidth. The bandwidth of SSD disks is mainly controlled by the host communication interface, the back-end command concurrency capability of the SSD controller, and the performance of NAND Flash storage media. The bandwidth of SSD disks includes data Transmission bandwidth and command transmission bandwidth. Since solid-state drives mainly transmit data, the data transmission bandwidth mainly restricts the disk bandwidth. However, the back-end command concurrency capability of the solid-state hard disk controller for a specified solid-state hard disk disk is basically fixed. In the existing technology, the main purpose is to reduce the I/O concurrency of the host communication interface to reduce the temperature of the disk. However, it is difficult to ensure that the disk can work normally when the ambient temperature of the disk is above 80°C. , and will lead to large fluctuations in disk performance and large bandwidth amplitudes, thereby greatly reducing the performance of solid-state drives and severely limiting the wide application of solid-state drives.

To sum up, in the actual use of solid-state drives, the working environment temperature of solid-state drives often occurs at 80°C. For example, enterprises use servers for a long time, or use solid-state drives in hot weather. Chips can still work normally and efficiently at high temperatures, and meet high reliability performance. It is very necessary to propose a solid-state hard drive to solve the technical bottleneck of high-performance solid-state hard drives in high-temperature environments. Improve the reliability of solid-state hard disks, realize wider applications, and make it possible to manufacture high-reliability solid-state hard disks.

Contents of the invention

In view of the above-mentioned defects, the technical problem to be solved by the present invention is to provide a high-temperature protection method for a solid-state hard disk, the purpose of which is to effectively reduce the temperature of the disk when the temperature of the disk is high, thereby improving the reliability of the solid-state hard disk. , and try to take into account other performance of the disk to ensure the safe, reliable and efficient operation of the solid state drive under high temperature.

In order to achieve the above object, the present invention provides a high temperature protection method for a solid-state hard disk. The temperature detection circuit detects the temperature of the solid-state hard disk, and effectively and reasonably limits the bandwidth of the solid-state hard disk according to the detected temperature information, thereby Reduce the power consumption of the solid-state drive to prevent the solid-state drive from not working properly due to overheating. Moreover, the high-temperature protection method of a solid-state hard disk provided by the present invention effectively ensures better disk performance while limiting the bandwidth of the solid-state hard disk, and greatly enhances the performance of the solid-state hard disk on the basis of the prior art. reliability. The method comprises the steps of:

Step 1: The temperature detection circuit detects the disk temperature of the solid-state hard disk;

Step 2: Set the timing to trigger the temperature detection circuit task;

Step 3: Set the initial temperature threshold of the SSD;

Step 4: Start the scheduled trigger task;

Step 5: Obtain the actual temperature information of the solid state drive regularly;

Step 6: Compare the actual temperature of the SSD with the set initial temperature threshold to obtain the difference between the two;

Step 7: Adjust the bandwidth of the solid state drive according to the difference between the actual temperature of the solid state drive and the set initial temperature threshold.

The temperature detection circuit detects the disk temperature of the solid-state hard disk, and the temperature detection circuit receives a trigger signal and starts a temperature collection task of the solid-state hard disk.

The setting of the timing trigger temperature detection circuit includes configuring the interrupt period T1 of the timing circuit of the solid-state hard disk, starting the timer, and periodically sending a trigger signal to the temperature detection circuit in units of T1. When the actual temperature of the solid-state hard disk reaches the set temperature start threshold, the data transmission bandwidth limit for the solid-state hard disk starts.

The timing task periodically sends a trigger signal to the temperature detection circuit, and obtains the actual temperature of the solid state disk fed back by the temperature detection circuit.

Increase or limit the bandwidth of SSD by adjusting the data transmission bandwidth of NAND Flash.

The adjustment of the data transmission bandwidth of the NAND Flash includes adjusting the number of concurrent command channels in the NAND Flash controller and the data throughput rate of the NAND Flash interface.

The adjustment of the number of concurrent channels of commands in the NAND Flash controller includes: when the actual temperature of the solid state disk is greater than the set initial temperature threshold and higher than the disk temperature value of the previous cycle, reducing the number of channels in the NAND Flash controller The number of concurrent command channels; when the actual temperature of the solid state drive is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle, increase the number of concurrent command channels in the NAND Flash controller; when the actual temperature of the solid state drive is lower than the initial temperature threshold Set the initial temperature threshold and restore the default number of concurrent command channels in the NAND Flash controller.

Said adjustment of the data throughput rate of the NAND Flash interface includes: reducing the data throughput rate of the NAND Flash interface when the actual temperature of the solid-state hard disk is greater than the initial temperature threshold value set and higher than the disk temperature value of the previous cycle; The actual temperature of the solid-state drive is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle to improve the data throughput rate of the NANDFlash interface; when the actual temperature of the solid-state drive is lower than the initial temperature threshold, restore the default NANDFlash Data throughput.

The adjustment of the data throughput rate of the NAND Flash interface adopts the operation time of reading or programming commands of the NAND Flash storage medium to adjust.

The business operation time of described adjustment NAND Flash storage medium comprises:

Step 1: Obtain the disk temperature of the solid-state hard disk periodically, which is recorded as the first temperature T1 of the disk;

Step 2: Set the initial temperature threshold of the disk according to the working environment temperature of the disk, which is recorded as the second temperature T2 of the disk;

Step 3: Set the temperature margin according to the process temperature upper limit of the main control chip of the solid-state hard disk, and calculate the upper limit of the disk temperature of the solid-state disk, which is recorded as the third temperature T3 of the disk;

Step 4: Obtain the basic operation time of reading or programming commands from the inside of the NAND Flash storage medium, which are respectively recorded as the first reading time Cr1 and the first programming time Cw1 of NAND Flash;

Step 5: When the first temperature T1 of the solid-state disk rises to the third temperature T3 of the disk, set the maximum operating time of the read or program command of the NAND Flash storage medium, which is respectively recorded as the second read time of the NAND Flash Crmax2 and the second programming time Cwmax2;

Step 6: According to Cr1 and Crmax2, when Cw1 and Cwmax2 obtain the NAND Flash storage medium read or programming operation, the operating time difference of the corresponding command is recorded as the third reading time Cr3 and the third programming time Cw3 of NAND Flash respectively;

Step 7: According to T2 and T3, obtain the actual temperature range difference of the solid-state hard disk, and record it as the first temperature difference T4 of the disk;

Step 8: According to T4 and Cr3, T4 and Cw3, the change value of the NAND Flash storage medium command operation time caused by the average temperature change of each degree Celsius is recorded as the fourth reading cycle Cr4 and the fourth programming cycle of NAND Flash respectively Cw4;

Step 9: If T1 is greater than or equal to T2, start to adjust the SSD bandwidth, get the difference between T1 and T2, and get the type of operation on the NAND Flash storage medium this time, combine Cr4 and Cw4 to get the reading or Actual operation time of programming commands. When this is a read command, the read operation time Cread of the NAND Flash storage medium satisfies:

Cread＝(T1-T2)*Cr4+Cr1

During this programming operation, the actual programming time Cwrite of the NAND Flash storage medium satisfies:

Cwrite＝(T1-T2)*Cw4+Cw1

If T1 is less than T2, stop adjusting the bandwidth of the solid-state hard disk, and at this time, the basic operation time is used for the operation time of reading or programming commands of the NAND Flash storage medium. The actual operation time Cread of the read operation of the NAND Flash storage medium satisfies:

Cread=Cr1

The actual operating time Cwrite of the programming operation of the NAND Flash storage medium satisfies:

Cwrite=Cw1.

Description of drawings

Fig. 1 shows a solid state hard disk device after adding a speed limiting method according to an embodiment of the present invention.

Fig. 2 shows a block diagram of the internal structure of a temperature detection circuit module according to an embodiment of the present invention.

Fig. 3 shows a block diagram of a high temperature speed limit control module according to an embodiment of the present invention.

Fig. 4 shows an overall flowchart of a high temperature protection method for a solid state disk according to an embodiment of the present invention.

FIG. 5 shows a flow chart of adjusting operation time of a solid state disk during a read or program operation according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Referring to Fig. 1, provide a kind of solid state hard disk (SSD, Solid State Driver) device after adding speed limiting method according to the embodiment of the present invention, comprise front-end host computer communication interface, solid state hard disk controller and NAND Flash storage medium chip. The operation business of the solid-state hard disk is generally divided into programming business, reading business and erasing business. The entire solid-state hard disk circuit realizes storing the data issued by the host into the NAND Flash memory particle, and also realizes reading the data stored in the NAND Flash memory to the host. The front-end host communication interface is connected with the solid-state hard disk controller, and is used as an interface for data transmission between the host computer and the disk, including transmitting the data of the solid-state hard disk to the host or sending the data of the host to the solid-state hard disk controller; The data of the solid state disk is transmitted to the host computer or the data of the host computer is transmitted to the solid state disk controller. The front-end host communication interface includes a SATA interface or a PCIE interface, which can support the current mainstream SATA3.0 (Serial ATA, serial ATA) interface or PCIE (Peripheral Component Interconnect Express) interface. The solid-state hard disk controller is connected to the communication interface of the host for receiving or uploading data to the communication interface of the host. Read, program, erase operations. The solid-state hard disk controller is connected to the NAND Flash memory chip, which is used to transmit the data read from the NAND Flash memory chip to the solid-state hard disk controller during the read operation of the solid-state hard disk, and then through the operation control of the solid-state hard disk controller, the read The output data are sent to the communication interface circuit of the host in turn, and finally uploaded to the host. The solid-state disk controller includes a temperature detection circuit module, which generates a temperature detection trigger signal and is connected to the temperature reading module for receiving the control signal in the temperature reading module, triggering the temperature detection circuit module to perform temperature detection, and periodically Send the temperature value information to the high temperature speed limit control module;

A temperature reading module, which generates a temperature reading control signal and is connected to the temperature detection circuit module and a timing trigger circuit, for real-time reading of the temperature of the solid-state hard disk;

A timing trigger circuit, which generates a periodic timing trigger signal and is connected to the high temperature speed limit control module and the temperature reading module, is used as a trigger mechanism for temperature detection, and periodically transmits the timing trigger signal to the temperature reading control circuit;

A high temperature speed limit control module, which generates a signal for controlling the timing trigger and is connected to the timing trigger circuit, generates a speed limit control command and connects to the NAND Flash controller, and transmits the received temperature information value to the high temperature speed limit value generation The controller module is used to control the high-temperature speed limit of the solid-state hard disk when the temperature of the solid-state hard disk is higher than the set temperature.

NAND Flash controller, which receives the speed limit control command sent by the high temperature speed limit control module, generates the control signal and data bandwidth to adjust the channel and the data bandwidth of the NAND Flash memory chip to the interface circuit of the NAND Flash memory chip, and is used to control the entire solid-state hard drive Program, read or erase the disk, and control the transmission of data and commands, and receive the high temperature speed limit logic control signal transmitted by the high temperature speed limit module and the speed limit bandwidth value of the NAND Flash memory chip;

The NAND Flash memory chip interface circuit receives the control signals and data transmitted by the NAND Flash controller, generates access to the programming or erasing or reading operation timing of the NAND Flash memory chip and transmits it to the NAND Flash memory chip; the NAND Flash memory chip interface circuit can support Asynchronous, ONFI protocol interface and Toggle protocol interface. Those skilled in the art know that the ONFI (Open NAND Flash Interface) protocol and the Toggle synchronization protocol are international protocol standards jointly marked by NAND Flash memory particle manufacturers, and different manufacturers adopt different protocols.

High temperature speed limit value generator module, which generates the latency value of NAND Flash reading or programming command and sends it to the high temperature speed limit control module to receive different temperature information values obtained by the high temperature speed limit control module and generate NAND Flash read Or the latency value of the programming command. The temperature detection circuit module, temperature reading module, timing trigger circuit module, high temperature speed limit control module, high temperature speed limit value module, NAND Flash controller (NANDFlash Controller, NFC) and NAND Flash memory interface circuit described in the embodiment of the present invention All are made of digital integrated circuits, which are actual chip circuit modules.

The back end of the solid-state hard disk includes a NAND Flash memory chip interface circuit in the NAND Flash controller and a multi-channel NAND Flash memory chip. In the embodiment of the present invention, the back end of the solid-state hard disk is composed of multiple channels, so that large-capacity data storage and efficient data storage can be realized. Each channel is generally composed of more than two NAND Flash storage chips. The NAND Flash storage medium chip described in this embodiment is cascaded with 8 NAND Flash storage medium chips to form a NAND Flash storage channel, a total of 4 NAND Flash storage channels. Among them, NAND Flash storage medium chips include SLC NAND Flash storage chips, MLC NAND Flash storage chips, TLC NAND Flash storage chips, and 3D NAND Flash storage chips. SLC NAND Flash (Single Level Cell, single-level unit flash memory) memory chip stores 1 bit of data per array device, MLC NAND Flash (Multi-Level Cell) memory chip stores 2 bits of data per array device, TLC NAND Flash (Triple-Level Cell) -Level Cell) memory chip stores 3 bits of data per array device. The array structure of the 3D NAND Flash memory chip adopts the three-dimensional memory of today's advanced technology, which greatly improves the storage capacity. When programming the solid-state hard disk, the solid-state hard disk controller receives the data and commands transmitted by the host communication interface, and generates the corresponding operation sequence circuit according to the operation command, and transmits the data to the specified address of the NAND Flash memory chip according to the programming operation sequence, and completes Programming operations on solid-state drives. The host communication interface adopts the SATA (Serial Advanced Technology Attachment, Serial ATA interface specification) interface protocol to realize command interaction and data transmission with the SATA host. The core components of the solid-state hard disk are the solid-state hard disk controller and the NAND Flash storage medium chip. The solid-state hard disk controller is used to control the data transmitted from the host to the front-end interface circuit to the solid-state hard disk controller, and to control the programming of the data transmitted from the host to the The NAND Flash memory chip, or controls the erasing operation of the NAND Flash memory chip, or realizes reading data from the NAND Flash memory chip to the front-end interface circuit. NAND Flash memory chips are used for data storage. The solid-state hard disk device of the embodiment of the present invention improves the solid-state hard disk controller, adds a high-temperature protection circuit control module, realizes high-temperature protection for the solid-state hard disk, and greatly improves the performance of the solid-state hard disk under the premise of less affecting the performance of the solid-state hard disk. stability. Fig. 1 shows the solid-state hard disk circuit device after adding the speed limiting method according to an embodiment of the present invention, wherein, the solid-state hard disk controller includes a temperature detection circuit module, a temperature reading module, a timing trigger circuit module, a high-temperature speed-limiting control module, a high-temperature A speed limit module, a NAND Flash controller (NAND FlashController, NFC) and a NAND Flash memory interface circuit. The temperature detection circuit module is connected to the temperature reading module, the timing trigger circuit module, the high temperature speed limit control module, and the high temperature speed limit value module in sequence; the high temperature speed limit control module is connected to the NAND Flash controller and the NAND Flash memory chip interface circuit in sequence. Wherein, the temperature detection circuit module is used to receive the control signal from the temperature reading module, trigger the temperature detection circuit module to perform temperature detection, and periodically transmit the temperature value to the high temperature speed limit control module. The temperature detection circuit module is actually an analog-to-digital converter, and the source of the analog signal is the temperature detection circuit. The temperature detection circuit is used as a module to convert physical signals into electrical signals. The core device in the module is PT100 temperature sensor, which transmits temperature signals to corresponding detection circuits through media and converts them into electrical signals. The temperature reading module is used to read the temperature of the solid state disk in real time. As a trigger mechanism for temperature detection, the timer trigger circuit transmits trigger signals to the temperature reading module periodically. The trigger cycle can be customized by the user, and the update of the trigger cycle is mainly completed by adding a host communication command. The trigger cycle is sent to the timer circuit by the CPU, and the timer circuit realizes counting. When the count reaches the set trigger cycle, a trigger signal is generated and sent to the temperature reading module. The high temperature speed limit control module is used to control the high temperature speed limit of the solid state disk when the temperature of the solid state disk is higher than the set temperature. Among them, the method of high temperature speed limit is to adjust the data transmission bandwidth of NAND Flash, including adjusting the number of concurrent command channels in the NAND Flash controller and/or the data throughput rate of the NAND Flash interface. The high temperature speed limit value generator module is used to receive different information values obtained by the high temperature speed limit control module, including the first disk temperature T1, the second disk temperature T2, the third disk temperature T3, and the first reading of NAND Flash. Take the time Cr1 and the first programming time Cw1, the second reading time Crmax2 and the second programming time Cwmax2 of NAND Flash. After the high temperature speed limit value generator module receives the high temperature control parameters calculated by the high temperature speed limit control module, it calculates and generates the actual programming time Cwrite of the NAND Flash storage medium and/or the read operation time Cread time value of the NAND Flash storage medium , and finally transmit the value of the calculated actual programming time Cwrite and/or read operation time Cread time to the NAND Flash storage medium to the high temperature speed limit control module, and the high temperature speed limit control module controls to transmit its value to the NAND Flash controller. The NAND Flash controller regulates the interface circuit of the NAND Flash memory chip according to the value, and finally regulates the data bandwidth of accessing the NAND Flash memory chip, so as to achieve the solution of limiting the speed when the temperature is too high, and recovering the data bandwidth when the temperature decreases. Therefore, the working problem of the solid-state hard disk in a high-temperature environment is efficiently solved without affecting other working performance indicators of the solid-state hard disk, and the reliability of the solid-state hard disk is greatly improved.

Secondly, the solid-state hard drive of the embodiment of the present invention has 4 channels, and each channel can mount 8 NAND Flash storage medium chips, and the multi-channel solid-state hard drive can realize large-capacity storage of data and higher bandwidth. The temperature rise of the solid-state hard disk caused by the operation is also the cause of the high temperature in the present invention, and the contradictory problem of satisfying multi-channel large data transmission and multi-channel data transmission caused by the temperature rise of the disk is also one of the problems solved by the present invention. . The method of high temperature speed limit is to adjust the data transmission bandwidth of NAND Flash, and also includes the adjustment of the number of concurrent command channels in the NAND Flash controller. When the high temperature speed limit control module receives the information value of the temperature reading module, it compares and reads The difference between the disk temperature value and the initial temperature threshold value. When the actual temperature of the solid state disk is greater than the set initial temperature threshold value and higher than the disk temperature value of the previous cycle, reduce the command concurrency in the NAND Flash controller. Number of channels; when the actual temperature of the solid state drive is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle, increase the number of concurrent command channels in the NAND Flash controller; when the actual temperature of the solid state drive is lower than the initial temperature Threshold, restore the default number of concurrent command channels in the NAND Flash controller.

With the continuous development of solid-state drives, the integration level is getting higher and higher. It is not only suitable for normal room temperature environments, but the application scenarios are becoming more and more complex. In some special application scenarios, if the ambient temperature exceeds the conventional temperature, such as 60-100 degrees Celsius , when programming, reading or erasing the solid-state hard disk, its own power consumption is very high, which may cause the temperature of the solid-state hard disk itself to exceed the process temperature of its chip, resulting in abnormal operation of the solid-state hard disk, resulting in In the case of user data loss, the solid-state drive will be burned out in severe cases. Fig. 1 shows that according to the embodiment of the present invention, the front-end interface circuit adopts the SATA protocol. In order not to slow down the access rate of the solid-state hard disk and not reduce other performance indicators, the present invention still uses the front-end interface to issue 32 IO port commands at the same time, that is, the front-end IO port The concurrency degree is still 32. Compared with the previous patent CN201210475065, which proposed to reduce the depth of the instruction queue for high temperature protection (that is, reduce the concurrency degree of the front-end IO port), although the existing patented scheme can protect the solid-state disk to a certain extent However, the overall performance of the solid state drive is greatly reduced. A high-temperature protection method for a solid-state hard disk proposed by the present invention solves the bottleneck of the prior art well, serves to protect the solid-state hard disk in a high-temperature environment, and at the same time ensures the good performance of the solid-state hard disk, and enhances the performance of the solid-state hard disk. HDD reliability.

Fig. 2 shows a block diagram of the internal structure of temperature detection according to an embodiment of the present invention, including a temperature sensor, a temperature conversion circuit, a temperature data register, and a detection trigger module. The temperature conversion circuit, temperature data register and detection trigger module are made of digital circuits. Wherein, the temperature sensor, the temperature conversion circuit, and the temperature data register are connected in sequence, and the detection trigger module is connected to the temperature conversion circuit. The temperature sensor is used to transmit the temperature signal to the temperature conversion circuit. The temperature sensor is made of special material, which has a good effect on its application scene, service life and accuracy. The temperature conversion circuit causes the voltage distribution according to the impedance change corresponding to the temperature sensor, mainly using the temperature resistance effect of the temperature sensor, so as to obtain the conversion of the temperature physical signal to the voltage signal. Due to the particularity of the temperature sensor (PT100), a temperature compensation circuit is required, the main function is to calibrate it, and the temperature value obtained for use is more accurate. When the temperature signal is converted into a voltage signal, the digital signal value can be directly obtained through analog-to-digital conversion, and the conversion standard is as follows:

Temperature value = V _out /C _base

In the above formula, the temperature value is the final accurate value, Vout is the electrical signal value obtained by the temperature conversion circuit, and Cbase is the temperature reference value, that is, the linear relationship of the change of the voltage value caused by the change of each degree Celsius. In practical applications, the temperature resistance efficiency of the sensing device cannot be a linear relationship, but after compensation, it can be approximately regarded as a linear relationship, from which the operating temperature of the solid-state hard disk can be calculated. The working temperature is temporarily stored in the temperature data register, which is written into the register by the master control of the solid-state hard disk. Finally, when obtaining the value, it is necessary to access the base address of the data register in a specific timing, so as to Obtain the operating temperature of the solid state drive. The temperature detection trigger module is a passive trigger and requires a specified trigger signal. Therefore, the temperature acquisition of the solid state disk is passive. Only after the trigger signal is provided to the temperature detection trigger module, the temperature detection and conversion related circuits can really work. Otherwise, the temperature register What is saved is the result of the last detection.

The temperature sensor is used to detect the temperature of the solid-state disk. It obtains physical signals, and the obtained results are directly sent to the temperature conversion circuit. The main function of the temperature conversion circuit is to convert the physical signal into an electrical signal, because the electrical signal is an actual sampleable signal, and then send the electrical signal data to the processor. The data calculated by the processor is the actual disk temperature value of the solid-state hard disk, and the processor finally stores the latest temperature value in the temperature register of the solid-state address, and the user can directly obtain the current disk temperature value of the solid-state hard disk through this address . The detection trigger module is a specially designed circuit for sampling the temperature of the solid-state hard disk. The user can apply it to the module through a simple level trigger, and the module will automatically trigger the temperature conversion circuit to work and send new data to the processor.

Figure 3 shows a diagram of a high temperature speed limit control device according to an embodiment of the present invention, including: a temperature acquisition signal, a temperature acquisition register, a high temperature speed limit control module, a NAND Flash channel, the temperature acquisition register, a high temperature speed limit control module, a NAND Flash channels are all made of digital integrated circuits, which are actually manufactured chip integrated circuits. in:

The temperature acquisition signal is connected to the high temperature speed limit control module for triggering the operation of the temperature acquisition circuit of the solid-state hard disk;

The temperature acquisition register is connected to the high temperature speed limit control module, and is used to store the disk temperature value;

The high temperature speed limit control module is connected to the NAND Flash channel, and is used to complete the high temperature limit control according to the disk temperature value information;

The NAND Flash channel is connected to the high temperature speed limit control module, and is used as a transmission channel for NAND Flash commands or data.

The high temperature speed limit control module includes: temperature acquisition signal generation module, temperature value validity detection module, temperature collection times statistics module, temperature analysis module, temperature and threshold comparison module, high temperature speed limit start determination module, NFC command operation time Obtain module, NFC command operation time validity analysis module and NFC command operation time configuration module, wherein:

The temperature acquisition signal generation module is connected to the temperature effective value detection module, for periodically sending temperature detection signals, and receiving temperature value information, and delivered to the temperature effective value detection module; here, NFC (NAND FlashController, NAND Flash controller) is a term known to those skilled in the art.

The temperature effective value detection module is connected to the temperature collection times statistics module for detecting the temperature value information, if the detected current temperature information is invalid, it will be directly discarded; otherwise, the effective temperature information will be passed to the temperature collection times statistics module ;

The temperature acquisition times statistics module is connected to the temperature analysis module, and is used to obtain multiple temperature information values, and count the time stamp information of the temperature values;

The temperature analysis module is connected to the temperature and threshold comparison module, and is used to analyze all temperature information according to the time stamp information to obtain a maximum temperature value;

The temperature-threshold comparison module is connected to the high-temperature speed-limited start determination module for comparing the temperature value with the set threshold value, and this comparison operation also includes comparison with the temperature information value of the previous cycle;

The high temperature limit speed start determination module is connected to the NFC command operation time acquisition module, which is used to determine whether the high temperature limit speed starts to start, and generates a start signal;

The NFC command operation time acquisition module is connected to the NFC command operation time validity analysis module, and is used to convert the actual operation time of the NFC command according to the temperature obtained currently;

The NFC command operating time validity analysis module is connected to the NFC command operating time configuration module for analyzing the validity of the actual operating time of the NFC command, mainly identifying whether the actual operating time of the current NFC command exceeds the limit;

The NFC command operation time configuration module is connected to the NAND Flash channel for storing the actual operation time of the current NFC command, and is always valid until the operation time of a new NFC command is obtained.

A high-temperature speed-limiting control device for a solid-state hard disk controller is characterized in that the temperature of the disk can be collected in real time.

A high-temperature speed-limiting control device for a solid-state hard disk controller is characterized in that the actual operation time of an NFC read command is obtained based on the temperature of the disk.

A high-temperature speed-limiting control device for a solid-state hard disk controller is characterized in that the actual operation time of the NFC write command is obtained based on the temperature of the disk.

A high-temperature speed-limiting control device for a solid-state hard disk controller, characterized in that the validity of disk temperature information is intelligently detected.

A high-temperature speed-limiting control device for a solid-state hard disk controller, characterized in that the operation time of the NFC command is stored.

A high-temperature speed-limiting control device for a solid-state hard disk controller is characterized in that the operation time of the NFC command will be replaced by a new operation time.

A high-temperature speed-limiting control device for a solid-state hard disk controller, wherein the NFC command includes: a read operation command, a programming operation command, an erasing operation command, a read status command, and a mode switching command to a NAND Flash memory , Read ID command.

Fig. 4 shows the overall flowchart of a high temperature protection method for a solid state disk according to an embodiment of the present invention, including the following steps:

Step 1: The temperature detection circuit detects the disk temperature of the solid-state hard disk;

Step 2: Set the timing trigger temperature detection circuit;

Step 3: Set the initial temperature threshold of the SSD;

Step 4: Start the scheduled trigger task;

Step 5: Obtain the actual temperature information of the solid state drive regularly;

Step 6: Compare the actual temperature of the SSD with the set initial temperature threshold to obtain the difference between the two;

Step 7: Adjust the bandwidth of the solid state drive according to the difference between the actual temperature of the solid state drive and the set initial temperature threshold.

The bandwidth of the solid state disk is adjusted according to the difference between the actual temperature of the solid state disk and the set initial temperature threshold. By detecting the difference between the temperature and the set initial temperature, the bandwidth of the solid-state hard disk is adjusted to adjust the operating time period of the solid-state hard disk, thereby reducing the temperature. The bandwidth of solid-state drives includes data transmission bandwidth and command transmission bandwidth. Since the operation of solid-state drives is mainly data storage, and commands are relatively small compared to data, the impact on the bandwidth of solid-state drives is mainly determined by the data transmission bandwidth.

The setting of the timing trigger temperature detection circuit includes configuring the interrupt period T1 of the timing circuit of the solid-state hard disk, starting the timer, and periodically sending a timing trigger signal to the temperature detection circuit in units of T1. A temperature detection circuit module, which generates a temperature detection trigger signal and is connected to the temperature reading module for receiving the control signal in the temperature reading module, triggering the temperature detection circuit module to perform temperature detection, and periodically transmitting temperature value information To the high temperature speed limit control module.

The setting of the timing trigger temperature detection circuit includes configuring the interrupt period T1 of the timing circuit of the solid-state hard disk, starting the timer, and periodically sending a trigger signal to the temperature detection circuit in units of T1. When the actual temperature of the solid state disk reaches the set temperature start threshold, the bandwidth limit of the solid state disk starts. The initial temperature threshold set by the solid state disk is set by the user, and is usually 70 degrees Celsius in an embodiment. When the temperature detection circuit detects that the disk reaches the set temperature initial threshold, it starts to limit the bandwidth of the solid state disk.

The timing task periodically sends a trigger signal to the temperature detection circuit, and obtains the actual temperature of the solid state disk fed back by the temperature detection circuit. Compare the actual temperature of the solid state disk with the set initial temperature threshold to obtain the difference between the two. For example, the actual temperature of the solid-state hard disk fed back by the temperature detection circuit obtained in the embodiment is T1, and the set initial temperature threshold is T2, then the value of T1-T2 is calculated. Increase or limit the bandwidth of SSD by adjusting the data transmission bandwidth of NAND Flash.

The adjustment of the data transmission bandwidth of the NAND Flash includes adjusting the number of concurrent command channels in the NAND Flash controller and/or the data throughput rate of the NAND Flash interface.

The adjustment of the number of concurrent channels of commands in the NAND Flash controller includes: when the actual temperature of the solid state disk is greater than the set initial temperature threshold and higher than the disk temperature value of the previous cycle, reducing the number of channels in the NAND Flash controller The number of concurrent command channels; when the actual temperature of the solid state drive is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle, increase the number of concurrent command channels in the NAND Flash controller; when the actual temperature of the solid state drive is lower than the initial temperature threshold Set the initial temperature threshold and restore the default number of concurrent command channels in the NAND Flash controller.

Said adjustment of the data throughput rate of the NAND Flash interface includes: reducing the data throughput rate of the NAND Flash interface when the actual temperature of the solid-state hard disk is greater than the initial temperature threshold value set and higher than the disk temperature value of the previous cycle; The actual temperature of the solid state disk is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle, which improves the data throughput rate of the NAND Flash interface; when the actual temperature of the solid state disk is greater than the initial temperature threshold and lower than the previous cycle When the temperature of the disk is low, increase the data throughput rate of the NAND Flash interface to ensure that the overall operating performance of the SSD is improved. That is, when the temperature drops, the bandwidth of the SSD cannot be limited all the time, so the data throughput rate of the NAND Flash interface is increased. Increase the bandwidth of solid-state drives, thereby greatly improving the performance of solid-state drives. When the actual temperature of the SSD is lower than the initial temperature threshold, the default data throughput rate of NAND Flash will be restored.

The adjustment of the data throughput rate of the NAND Flash interface adopts the operation time of reading or programming commands of the NAND Flash storage medium to adjust. The operation time of the read or programming command to the NAND Flash storage medium is the latency period for the operation of the NAND Flash storage chip.

The reading or programming business operation time of described adjustment NAND Flash storage medium comprises:

Step 1: Obtain the disk temperature of the solid-state hard disk periodically, which is recorded as the first temperature T1 of the disk;

Step 2: Set the initial temperature threshold of the disk according to the working environment temperature of the disk, which is recorded as the second temperature T2 of the disk;

Step 3: according to the process temperature upper limit of the solid-state hard disk main control chip, set the temperature margin, and calculate the upper limit of the solid-state hard disk disk temperature, which is recorded as the third temperature T3 of the disk; the process temperature of the solid-state hard disk main control chip is determined by It is determined by the production process line, generally at 125 degrees Celsius. For example, in the embodiment, the process temperature is 125 degrees Celsius, and the temperature margin is 25 degrees Celsius, then the upper limit of the disk temperature of the solid-state hard disk is calculated as the upper limit of the process temperature-set temperature margin=125-25=100 degrees Celsius. The upper limit of the disk temperature of the solid-state hard disk is the maximum disk temperature that cannot be exceeded during the adjustment process, that is, if the high-temperature ambient temperature is 71 degrees Celsius at this time, and the initial threshold of the set temperature is also 70 degrees Celsius, then start to adjust the bandwidth of the solid-state disk at this moment , and the temperature of the solid-state hard disk should not exceed the upper limit of the disk temperature by 100 degrees Celsius.

Step 4: Obtain the basic operation time of reading or programming commands from the inside of the NAND Flash storage medium, which are respectively recorded as the first reading time Cr1 and the first programming time Cw1 of NAND Flash; obtain the reading or programming from the inside of the NAND Flash storage medium The basic operation time of the command can be directly through the operation manual of the NAND Flash memory chip, and send the corresponding command according to the chip operation manual to obtain the first reading time Cr1 and the first programming time Cw1 of the NAND Flash.

Step 5: When the first temperature T1 of the solid-state disk rises to the third temperature T3 of the disk, set the maximum operating time of the read or program command of the NAND Flash storage medium, which is respectively recorded as the second read time of the NAND Flash Crmax2 and the second programming time Cwmax2;

Step 6: According to Cr1 and Crmax2, when Cw1 and Cwmax2 obtain the NAND Flash storage medium read or programming operation, the operating time difference of the corresponding command is recorded as the third reading time Cr3 and the third programming time Cw3 of NAND Flash respectively; That is, Cr3 is the difference between Cr1 and Crmax2, and Cw3 is the difference between Cw1 and Cwmax2.

Step 7: Obtain the actual temperature range difference of the solid state disk according to T2 and T3, and record it as the first disc temperature difference T4; that is, T4 is the size of T2-T3.

Step 8: According to T4 and Cr3, T4 and Cw3, the change value of the NAND Flash storage medium command operation time caused by the average temperature change of each degree Celsius is recorded as the fourth reading cycle Cr4 and the fourth programming cycle of NAND Flash respectively Cw4;

Step 9: If T1 is greater than or equal to T2, start to adjust the bandwidth of the solid-state hard disk, get the difference between T1 and T2 (T1-T2), and obtain the type of operation business on the NAND Flash storage medium this time. The type of operation business includes programming operation business and Read operation business. Combine Cr4 and Cw4 to obtain the actual operation time of the read or program command of the NAND Flash storage medium respectively. When this is a read command, the actual operation time Cread of the NAND Flash storage medium satisfies:

Cread＝(T1-T2)*Cr4+Cr1

During this programming operation, the actual operation time Cwrite of the NAND Flash storage medium satisfies:

Cwrite＝(T1-T2)*Cw4+Cw1

If T1 is less than T2, stop adjusting the bandwidth of the solid-state hard disk, and at this time, the basic operation time is used for the operation time of reading or programming commands of the NAND Flash storage medium. The actual operation time Cread of the read operation of the NAND Flash storage medium satisfies:

Cread=Cr1

The actual operating time Cwrite of the programming operation of the NAND Flash storage medium satisfies:

Cwrite=Cw1

Fig. 5 shows a flow chart of adjusting the operating time of a solid-state hard disk in a read or programming operation according to an embodiment of the present invention, the steps of which include:

Step 1: Obtain the disk temperature of the solid-state hard disk periodically, which is recorded as the first temperature T1 of the disk;

Step 2: Set the initial temperature threshold of the disk according to the working environment temperature of the disk, which is recorded as the second temperature T2 of the disk;

Step 3: Set the temperature margin according to the process temperature upper limit of the main control chip of the solid-state hard disk, and calculate the upper limit of the disk temperature of the solid-state disk, which is recorded as the third temperature T3 of the disk;

Step 4: Obtain the basic operation time of reading or programming commands from the inside of the NAND Flash storage medium, which are respectively recorded as the first reading time Cr1 and the first programming time Cw1 of NAND Flash;

Step 5: When the first temperature T1 of the solid-state disk rises to the third temperature T3 of the disk, set the maximum operating time of the read or program command of the NAND Flash storage medium, which is respectively recorded as the second read time of the NAND Flash Crmax2 and the second programming time Cwmax2;

Step 6: According to Cr1 and Crmax2, when Cw1 and Cwmax2 obtain the NAND Flash storage medium read or programming operation, the operating time difference of the corresponding command is recorded as the third reading time Cr3 and the third programming time Cw3 of NAND Flash respectively;

Step 7: According to T2 and T3, obtain the actual temperature range difference of the solid-state hard disk, and record it as the first temperature difference T4 of the disk;

Step 8: According to T4 and Cr3, T4 and Cw3, the change value of the NAND Flash storage medium command operation time caused by the average temperature change of each degree Celsius is recorded as the fourth reading cycle Cr4 and the fourth programming cycle of NAND Flash respectively Cw4;

Step 9: If T1 is greater than or equal to T2, start to adjust the SSD bandwidth, get the difference between T1 and T2, and get the type of operation on the NAND Flash storage medium this time, combine Cr4 and Cw4 to get the reading or The actual operation time of the programming command; when it is a read command this time, the read operation time Cread of the NAND Flash storage medium satisfies:

Cread＝(T1-T2)*Cr4+Cr1

During this programming operation, the actual programming time Cwrite of the NAND Flash storage medium satisfies:

Cwrite＝(T1-T2)*Cw4+Cw1

If T1 is less than T2, stop adjusting the bandwidth of the solid-state hard disk. At this time, the operation time of the read or program command of the NAND Flash storage medium adopts the basic operation time, and the actual operation time Cread of the read operation of the NAND Flash storage medium satisfies:

Cread=Cr1

The actual operating time Cwrite of the programming operation of the NAND Flash storage medium satisfies:

Cwrite=Cw1.

Claims (10)

1. a high-temperature protection method of solid-state hard disk, is characterized in that, comprises the following steps: Step 1: The temperature detection circuit detects the disk temperature of the solid-state hard disk; Step 2: Set the timing trigger temperature detection circuit; Step 3: Set the initial temperature threshold of the SSD; Step 4: Start the scheduled trigger task; Step 5: Obtain the actual temperature information of the solid state drive regularly; Step 6: Compare the actual temperature of the SSD with the set initial temperature threshold to obtain the difference between the two; Step 7: Adjust the bandwidth of the solid state drive according to the difference between the actual temperature of the solid state drive and the set initial temperature threshold. 2. the high-temperature protection method of a kind of solid-state hard disk as claimed in claim 1, is characterized in that, described setting timing triggers temperature detection circuit, comprises the interruption period T1 of the timing circuit of configuration solid-state hard disk, starts the timer, and with T1 Send a trigger signal to the temperature detection circuit periodically as a unit. 3. The high-temperature protection method of a solid-state hard disk as claimed in claim 1, wherein, when the actual temperature of the solid-state hard disk reaches a set temperature initial threshold, the data transmission bandwidth limit of the solid-state hard disk is started. 4. the high temperature protection method of a kind of solid-state hard disk as claimed in claim 1, is characterized in that, described timing task can periodically send trigger signal to temperature detection circuit, and obtains the actual temperature of the solid-state hard disk of temperature detection circuit feedback . 5. The high temperature protection method of a kind of solid-state hard disk as claimed in claim 1, is characterized in that, promote or limit solid-state hard disk bandwidth by adjusting the data transmission bandwidth of NAND Flash. 6. the high-temperature protection method of a kind of solid-state hard disk as claimed in claim 6, is characterized in that, the data transmission bandwidth of described adjustment NANDFlash, comprises to the concurrent channel quantity of order in the NAND Flash controller and/or the NAND Flash interface The data throughput rate is adjusted. 7. the high-temperature protection method of a kind of solid-state hard disk as claimed in claim 6, is characterized in that, described adjusting the command concurrent channel quantity in the NANDFlash controller comprises: when the actual temperature of solid-state hard disk is greater than the initial temperature valve of setting value and higher than the disk temperature value of the previous cycle, reduce the number of concurrent command channels in the NAND Flash controller; when the actual temperature of the solid state drive is greater than the initial temperature threshold and lower than the disk temperature value of the previous cycle , to increase the number of concurrent command channels in the NAND Flash controller; when the actual temperature of the SSD is lower than the initial temperature threshold, restore the default number of concurrent command channels in the NAND Flash controller. 8. The high-temperature protection method of a kind of solid-state hard disk as claimed in claim 6, is characterized in that, said adjusting the data throughput rate of NANDFlash interface comprises: when the actual temperature of solid-state hard disk is greater than the initial temperature threshold value of setting and is higher than The disk temperature value in the previous cycle is higher, which reduces the data throughput rate of the NAND Flash interface; when the actual temperature of the SSD is greater than the initial temperature threshold and lower than the disk temperature value in the previous cycle, increase the NAND Flash interface. Data throughput rate; when the actual temperature of the SSD is lower than the initial temperature threshold, the default data throughput rate of NAND Flash will be restored. 9. the high-temperature protection method of a kind of solid-state hard disk as claimed in claim 8, is characterized in that, the data throughput rate of described adjustment NAND Flash interface, adopts the operation time of reading or programming order to NAND Flash storage medium to adjust. 10. the high-temperature protection method of a kind of solid-state hard disk as claimed in claim 9, is characterized in that, the service operating time of described adjustment NAND Flash storage medium comprises: Step 1: Obtain the disk temperature of the solid-state hard disk periodically, which is recorded as the first temperature T1 of the disk; Step 2: Set the initial temperature threshold of the disk according to the working environment temperature of the disk, which is recorded as the second temperature T2 of the disk; Step 3: Set the temperature margin according to the process temperature upper limit of the main control chip of the solid-state hard disk, and calculate the upper limit of the disk temperature of the solid-state disk, which is recorded as the third temperature T3 of the disk; Step 4: Obtain the basic operation time of reading or programming commands from the inside of the NAND Flash storage medium, which are respectively recorded as the first reading time Cr1 and the first programming time Cw1 of NAND Flash; Step 5: When the first temperature T1 of the solid-state disk rises to the third temperature T3 of the disk, set the maximum operating time of the read or program command of the NAND Flash storage medium, which is respectively recorded as the second read time of the NAND Flash Crmax2 and the second programming time Cwmax2; Step 6: According to Cr1 and Crmax2, when Cw1 and Cwmax2 obtain the NAND Flash storage medium read or programming operation, the operating time difference of the corresponding command is recorded as the third reading time Cr3 and the third programming time Cw3 of NAND Flash respectively; Step 7: According to T2 and T3, obtain the actual temperature range difference of the solid-state hard disk, and record it as the first temperature difference T4 of the disk; Step 8: According to T4 and Cr3, T4 and Cw3, the change value of the command operation time of the NAND Flash storage medium caused by the temperature change of each degree Celsius is obtained, which is respectively recorded as the fourth reading cycle Cr4 and the fourth programming of NAND Flash cycle Cw4; Step 9: If T1 is greater than or equal to T2, start to adjust the SSD bandwidth, get the difference between T1 and T2, and get the type of operation on the NAND Flash storage medium this time, combine Cr4 and Cw4 to get the reading or The actual operation time of the programming command; when it is a read command this time, the read operation time Cread of the NAND Flash storage medium satisfies: Cread=(T1-T2)*Cr4+Cr1; During this programming operation, the actual programming time Cwrite of the NAND Flash storage medium satisfies: Cwrite=(T1-T2)*Cw4+Cw1; If T1 is less than T2, stop adjusting the bandwidth of the solid-state hard disk. At this time, the operation time of the read or program command of the NAND Flash storage medium adopts the basic operation time, and the actual operation time Cread of the read operation of the NAND Flash storage medium satisfies: Cread=Cr1; The actual operating time Cwrite of the programming operation of the NAND Flash storage medium satisfies: Cwrite=Cw1.