CN108039937B - Resource optimization method and device in baseband processing and electronic equipment - Google Patents

Abstract

The invention provides a resource optimization method, a device and electronic equipment in baseband processing, relates to the technical field of communication, and is applied to a DVB-T2 system sending end, wherein the method comprises the following steps: and acquiring data to be transmitted, writing the data to be transmitted into the RAM according to the writing rule of cell interleaving, and reading the written data to be transmitted from the RAM according to the output rule of time interleaving. The resource optimization method, the resource optimization device and the electronic equipment in the baseband processing reduce occupied RAM resources and improve the running speed of a T2 system by combining cell interleaving and time interleaving into a whole.

Description

Resource optimization method, device and electronic device in baseband processing

technical field

The present invention relates to the field of communication technologies, and in particular, to a resource optimization method, device and electronic device in baseband processing.

Background technique

DVB (Digital Video Broadcasting, Digital Video Broadcasting)-T2 is the second-generation European digital terrestrial television broadcasting transmission standard, and the highest TS stream (Transport Stream) transmission rate supported in the 8MHz spectrum bandwidth is about 50.1Mbit/s. The service to be transmitted is transmitted through the DVB-T2 system (hereinafter referred to as the T2 system).

In the prior art, the transmitting end of the T2 system usually includes four consecutive modules of constellation mapping, constellation rotation, cell interleaving, and time interleaving, which are used to perform baseband processing on the data to be transmitted. As shown in Figure 1, the data to be transmitted after serial-to-parallel conversion (bit width is 8) is transformed into a 32-bit wide data stream after constellation mapping. The ping-pong RAM (random access memory, random access memory) of N _cells sends the data stream into the constellation rotation module, and then completes the cell through a pair of ping-pong RAMs with a bit width of 32 and a depth of (N _cells × N _fec ). After interleaving, a pair of ping-pong RAMs with a bit width of 32 and a depth of (N _cells ×N _fec ) are used to complete time interleaving, thereby obtaining the data to be transmitted after baseband processing. Among them, the data to be transmitted is composed of a plurality of cells after serial-parallel conversion, N _cells represents the number of cells corresponding to a FEC (Forward error correction) block after serial-parallel conversion, and N _fec represents a signal The number of corresponding FEC blocks in the meta-interleaving module.

When the above-mentioned T2 system is used for baseband processing, if there is constellation rotation, the occupied RAM resources are: (32×N _cells ×2+32×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2) ; If there is no constellation rotation, the occupied RAM resources are: (32×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2). It can be seen that more RAM resources are occupied when the existing T2 system is used for baseband processing, which will result in a slow running speed of the T2 system.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a resource optimization method, device and electronic device in baseband processing, so as to reduce the occupied RAM resources and improve the running speed of the T2 system.

In a first aspect, an embodiment of the present invention provides a method for resource optimization in baseband processing. The method is applied to a DVB-T2 system transmitter, and the method includes:

Get the data to be transmitted;

Write the data to be transmitted into the RAM according to the writing rule of the cell interleaving;

The written data to be transmitted is read out from the RAM according to the output rule of time interleaving.

In conjunction with the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the acquiring the data to be transmitted includes:

Receive the data to be transmitted outputted by the serial-to-parallel conversion module; the data to be transmitted is composed of cells corresponding to the serial-to-parallel conversion of a plurality of forward error correction FEC blocks;

The method also includes:

A constellation mapping operation is performed on the data to be transmitted read out from the RAM to obtain constellation point data corresponding to the data to be transmitted.

With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides the second possible implementation manner of the first aspect, wherein the data to be written to be transmitted from the read from the RAM, including:

According to the output rule of time interleaving, the out-of-order cells of the data to be transmitted are directly read from the RAM.

In conjunction with the second possible implementation manner of the first aspect, the embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein the method further includes:

After performing a ping-pong operation on the constellation point data, a constellation rotation operation is performed to obtain the constellation point data after the constellation rotation.

With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the data to be written to be transmitted from all read from the RAM, including:

Read two interleaved data from the RAM, the two interleaved data are two consecutive cells before cell interleaving, and one of the interleaved data is directly read from the RAM according to the output rule of time interleaving The cell after the data to be transmitted is out of sequence;

The constellation point data includes two channels of constellation data corresponding to the two channels of interleaved data, and the method further includes:

Perform a constellation rotation operation on the two-way constellation data to obtain constellation point data after constellation rotation.

In a second aspect, an embodiment of the present invention further provides a resource optimization device in baseband processing, the device is applied in the transmitting end of the DVB-T2 system, the device includes a cell interleaving and time interleaving fusion module, the cell The interleaving and time interleaving fusion module includes:

a data acquisition unit, used to acquire the data to be transmitted;

a writing unit, for writing the data to be transmitted into the RAM according to the writing rule of the cell interleaving;

The readout unit is configured to read out the written data to be transmitted from the RAM according to the output rule of time interleaving.

In conjunction with the second aspect, the embodiment of the present invention provides a first possible implementation manner of the second aspect, wherein the data acquisition unit is specifically configured to:

Receive the data to be transmitted outputted by the serial-to-parallel conversion module; the data to be transmitted is composed of cells corresponding to the serial-to-parallel conversion of a plurality of forward error correction FEC blocks;

The device also includes:

A constellation mapping module, configured to perform a constellation mapping operation on the data to be transmitted read out from the readout unit to obtain constellation point data corresponding to the data to be transmitted.

In conjunction with the first possible implementation manner of the second aspect, the embodiment of the present invention provides a second possible implementation manner of the second aspect, wherein the readout unit is specifically used for:

According to the output rule of time interleaving, the out-of-order cells of the data to be transmitted are directly read from the RAM.

In conjunction with the first possible implementation manner of the second aspect, the embodiment of the present invention provides a third possible implementation manner of the second aspect, wherein the readout unit is specifically used for:

Read two interleaved data from the RAM, the two interleaved data are two consecutive cells before cell interleaving, and one of the interleaved data is directly read from the RAM according to the output rule of time interleaving The cell after the data to be transmitted is out of sequence;

The constellation point data includes two channels of constellation data corresponding to the two channels of interleaved data, and the device further includes:

The constellation rotation module is used for performing a constellation rotation operation on the two-way constellation data to obtain the constellation point data after the constellation rotation.

In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor implements the computer program when the processor executes the computer program. The method described in the first aspect and any possible implementation manner thereof.

The embodiments of the present invention have brought the following beneficial effects:

In the embodiment of the present invention, the data to be transmitted is obtained first, then the data to be transmitted is written into the RAM according to the writing rules of cell interleaving, and the written data to be transmitted is read from the RAM according to the output rules of time interleaving. The resource optimization method, device, and electronic device in baseband processing provided by this embodiment combine cell interleaving and time interleaving into one, so that while ensuring the bit error rate, the RAM occupied by cell interleaving and time interleaving is reduced. The resources are reduced to half of the original, reducing the occupied RAM resources and improving the running speed of the T2 system.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the description, claims and drawings.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

Fig. 1 is the schematic flow chart of adopting the existing T2 system to carry out baseband processing;

2 is a schematic flowchart of a resource optimization method in baseband processing provided by an embodiment of the present invention;

3 is a schematic flowchart of another resource optimization method in baseband processing provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of jump order writing in a resource optimization method in baseband processing provided by an embodiment of the present invention;

5 is a schematic diagram of a time interleaving rule provided by an embodiment of the present invention;

6 is a schematic flowchart of another resource optimization method in baseband processing provided by an embodiment of the present invention;

7 is a schematic flowchart of another resource optimization method in baseband processing provided by an embodiment of the present invention;

8 is a schematic structural diagram of a resource optimization apparatus in baseband processing provided by an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of another apparatus for resource optimization in baseband processing provided by an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of them. example. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

At present, when the existing T2 system is used for baseband processing, a lot of RAM resources are occupied, which will lead to a slow running speed of the T2 system. Based on this, the embodiments of the present invention provide a resource optimization method, device and electronic device in baseband processing. By combining cell interleaving and time interleaving into one, RAM resources occupied can be reduced and the running speed of the T2 system can be improved.

In order to facilitate the understanding of this embodiment, a resource optimization method in baseband processing disclosed in the embodiment of the present invention is first introduced in detail.

Example 1:

A method for resource optimization in baseband processing provided by an embodiment of the present invention is applied to the transmitting end of the DVB-T2 system. The method combines the cell interleaving module and the time interleaving module of the transmitting end of the DVB-T2 system into one. The implementation of the system shrinks the amount of RAM used.

FIG. 2 is a schematic flowchart of a resource optimization method in baseband processing provided by an embodiment of the present invention. As shown in FIG. 2 , the method includes the following steps:

Step S201, acquiring data to be transmitted.

The data to be transmitted is composed of a plurality of cells, which may be data output after constellation rotation, or data output after serial-parallel conversion, which is not limited here.

Step S202, the above data to be transmitted is written into the RAM according to the writing rule of the cell interleaving.

Through the writing rule of cell interleaving, the writing sequence of the data to be transmitted is disrupted in the frequency domain to reduce the bit error rate. The data to be transmitted is written in the cell interleaving in a hopping manner, and the specific writing rules are the same as those in the corresponding prior art, which will not be repeated here.

Step S203: Read the written data to be transmitted from the RAM according to the output rule of time interleaving.

The rule of time interleaving is carried out in columns. Since the RAM space size of cell interleaving and time interleaving is the same, the data output in the order of cell interleaving in the original T2 system will be sequentially written into the RAM of time interleaving, so the cell interleaving is written in The data to be transmitted is directly read out according to the output rule of time interleaving, and the same effect can be obtained, which reduces the occupied RAM resources while ensuring the bit error rate, and improves the running speed of the T2 system. The output rule of time interleaving is the same as that in the prior art, and details are not repeated here.

In the embodiment of the present invention, the data to be transmitted is obtained first, then the data to be transmitted is written into the RAM according to the writing rules of cell interleaving, and the written data to be transmitted is read from the RAM according to the output rules of time interleaving. The resource optimization method in baseband processing provided by this embodiment, by combining cell interleaving and time interleaving into one, while ensuring the bit error rate, the RAM resources occupied by cell interleaving and time interleaving are reduced to the original one. Half, reducing the occupied RAM resources and improving the running speed of the T2 system.

FIG. 3 is a schematic flowchart of another resource optimization method in baseband processing provided by an embodiment of the present invention. As shown in FIG. 3 , the method has no constellation rotation operation and includes the following steps:

Step S301, receiving the data to be transmitted output by the serial-parallel conversion module.

The data to be transmitted is composed of cells corresponding to a plurality of forward error correction FEC blocks after serial-to-parallel conversion respectively. The FEC block is a bit stream data block output by channel coding, with a bit width of 1, including information bits and check bits. At the sending end of the T2 system, the data can be converted into, but not limited to, an 8-bit wide cell stream through serial-to-parallel conversion. The following takes an example where the bit width of the data to be transmitted is 8 for specific description.

In step S302, the above data to be transmitted is written into the RAM according to the writing rule of cell interleaving through a ping-pong operation.

The above-mentioned ping-pong operation refers to: the input data stream is isochronously allocated to the two data buffer modules through the "input data selection unit". In the first buffering cycle, the input data stream is buffered to the "data buffer module 1"; in the second buffering cycle, the input data stream is buffered to the "data buffer module 2" through the switching of the "input data selection unit". ", at the same time, the first cycle data buffered by "data buffer module 1" is selected by "output data selection unit" and sent to "data stream operation processing module" for operation processing; in the third buffer cycle, through "input data" Switch the selection unit again, buffer the input data stream to the "data buffer module 1", and at the same time switch the data of the second cycle buffered by the "data buffer module 2" through the "output data selection unit" and send it to the "data buffer module 2". Stream operation processing module" to perform operation processing. so cycle. The buffer space can be saved by the ping-pong operation, and the low-speed module can process high-speed data.

FIG. 4 is a schematic diagram of jump order writing in a resource optimization method in baseband processing provided by an embodiment of the present invention, each small cell represents a write address of a cell, and each column in the figure only shows five addresses write order. As shown in Figure 4, the number of rows of each group of data to be transmitted is written as N _cells , and the number of columns is denoted as N _fec , where N _cells represents the number of cells corresponding to one FEC block after serial-to-parallel transformation, N _fec represents the number of corresponding FEC blocks in a cell interleaving module. The cells corresponding to each FEC block are mapped to the corresponding columns according to the writing rules. The specific mapping rules are as follows:

其中，

为写入的地址，则Let the data output by parallel-serial conversion be g _r,q , where the value range of r is 0 to N _fec -1; the value range of q is 0 to N _cells -1;

in,

is the write address, then

L _r (q)=[L ₀ (q)+P(r)]modN _cells , where P(r) is the starting offset address of each column, and L ₀ (q) is the correspondence of each column without offset write address.

The rules for L ₀ (q) are first given. Let the bit width of N _cells be N _d , that is, N _d =[log ₂ (N _cells )], and set an array S _i composed of data with a bit width of N _d , where i=0, 1, 2·· · 2 ^Nd-1 .

Then the value rule of each bit of each bit of S _i is as follows:

S _i [N _d -1]=(i mod 2);

i=0,1:

S _i [N _d -2,N _d -3,...1,0]=0,0,...,0,0

i=2:

S ₂ [N _d -2, N _d -3,...1,0]=0,0,...,0,1

2<i<2 ^Nd :

S _i [N _d -3, N _d -4,...1,0]=S _i-1 [N _d -2,N _d -3,...2,1];

When N _d =11,

When N _d =12,

When N _d =13,

When N _d =14,

When N _d =15,

After obtaining _Si , L ₀ (q) is equal to _throwing away the data larger than N _cells in Si. The process is as follows:

Next, the rule of P(r) is given. Let Q _k be an increasing array with a bit width of N _cells and values from 0 to 2 ^Ncells -1, and let the data of Q _k ' be the inversion of each data bit of Q _k data, then P(r) is the data larger than N _cells in Q _k ', the process is as follows:

According to the above rules, the serial-to-parallel converted data is stored in the cell interleaving RAM, and the RAM size is a pair of ping-pong RAMs with a bit width of 8 and a depth of (N _cells × N _fec ).

Step S303, according to the output rule of time interleaving, directly read out the cells whose data to be transmitted is out of order from the RAM.

FIG. 5 is a schematic diagram of a time interleaving rule provided by an embodiment of the present invention. As shown in FIG. 5 , the time interleaving rule is performed in columns, where Nr=N _cells /5, and Nc=5×N _fec .

Since the RAM space size of cell interleaving and time interleaving is the same, the data to be transmitted written in cell interleaving can be directly read out according to the output rules of time interleaving, and the same effect can be obtained. The data obtained at this time is not constellation Raw data when rotated.

Step S304, performing a constellation mapping operation on the above output cells to obtain constellation point data corresponding to the data to be transmitted.

The output cells are constellation mapped according to the constellation mapping method, and are mapped to the corresponding constellation points. The bit width of the mapped constellation point data is 32 (16 bits for the real part and 16 bits for the imaginary part).

In this embodiment, the constellation mapping is moved after time interleaving, so that the data bit width of the interleaving module is 8. Therefore, the RAM resources occupied by the above steps in FIG. 3 are: (8×N _cells ×N _fec ×2). When there is no constellation rotation, the RAM resources occupied by the prior art are: (32×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2). It can be seen that the RAM resources occupied by this embodiment are only the current 1/8 of the technology, thereby improving the operating speed of the T2 system.

FIG. 6 is a schematic flowchart of another method for resource optimization in baseband processing provided by an embodiment of the present invention. On the basis of FIG. 3 , a constellation rotation operation is added to the method. In order to realize the constellation rotation, a ping-pong operation is added before the constellation rotation operation, as shown in Figure 6, the method includes the following steps:

Step S601, receiving the data to be transmitted output by the serial-parallel conversion module.

In step S602, the above data to be transmitted is written into the RAM according to the writing rule of cell interleaving through a ping-pong operation.

Step S603, according to the output rule of time interleaving, directly read out the cells whose data to be transmitted is out of order from the RAM.

Step S604, perform a constellation mapping operation on the above output cells to obtain constellation point data corresponding to the data to be transmitted.

Step S605, after performing a ping-pong operation on the constellation point data, and then performing a constellation rotation operation to obtain the constellation point data after the constellation rotation.

Through a pair of ping-pong RAMs with a bit width of 32 and a depth of (N _cells × N _fec ), the constellation point data is sent to the constellation rotation module for constellation rotation operation, and the constellation point data after the constellation rotation can be obtained. The constellation rotation is the prior art, and details are not repeated here.

The RAM resources occupied by the above method with constellation rotation provided in this embodiment are: (8×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2). When there is constellation rotation, the RAM resources occupied by the prior art are: (32×N _cells ×2+32×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2), which can be seen in this embodiment. The RAM resource occupied is less than 0.625 of the prior art, thereby improving the running speed of the T2 system.

In order to further reduce the RAM resources occupied when there is constellation rotation, the embodiment of the present invention also provides another resource optimization method in baseband processing. As shown in FIG. 7 , the method includes the following steps:

Step S701, receiving the data to be transmitted outputted by the serial-parallel conversion module.

In step S702, the above data to be transmitted is written into the RAM according to the writing rule of cell interleaving through a ping-pong operation.

Step S703, read out two-way interleaving data from the above-mentioned RAM, the two-way interleaving data are two consecutive cells before the cell interleaving, wherein the one-way interleaving data is directly read from the RAM according to the output rule of time interleaving. The cell after the data to be transmitted is out of sequence.

设g_r,q和g_r,q-1写入信元交织模块的位置分别为

和

因此本实施例中，当输出

位置的信元时，同时将

位置的信元输出，即同时输出两路交织数据。通过在交织中直接输出用于星座旋转的两路交织数据，可以使星座旋转前无需进行乒乓操作，以进一步减少乒乓操作占用的RAM资源。When using constellation rotation, because the data of constellation rotation operation is _gr,q and _gr,q-1 , where q takes 0 to N _cells -1, when q=0, _gr,q-1 is

Suppose the positions of _{gr, q} and _{gr, q-1} written into the cell interleaving module are respectively

and

Therefore, in this embodiment, when the output

position cell, while the

Position cell output, that is, output two interleaved data at the same time. By directly outputting the two-way interleaving data used for constellation rotation during interleaving, it is possible to eliminate the need to perform a ping-pong operation before the constellation rotation, so as to further reduce RAM resources occupied by the ping-pong operation.

Step S704: Perform a constellation mapping operation on the two output channels of interleaved data to obtain two channels of constellation data corresponding to the data to be transmitted.

Step S705, performing a constellation rotation operation on the above two channels of constellation data to obtain constellation point data after constellation rotation.

The principle of constellation rotation is as follows:

在此处分别记为

Wherein, e ₀ and e _q both represent the cell position after the constellation is rotated; R _RQD is the rotation factor, which depends on the constellation mapping method; since the constellation rotation is independent of the column, the above step S703

are recorded here as

Since the two-way interleaving data output in step S703 is exactly two consecutive cells before cell interleaving (when one of them is the first cell of the FEC block, it corresponds to the last cell of the FEC block), Therefore, the output result at this time is exactly consistent with the prior art.

In this embodiment, since the input of constellation rotation directly includes two-way data for rotation, RAM storage is not required, that is, when there is constellation rotation, the RAM resource used by the method provided in this embodiment is (8×N _cells ×N _fec ×2), and the RAM resources occupied by the prior art are: (32×N _cells ×2+32×N _cells ×N _fec ×2+32×N _cells ×N _fec ×2). The RAM resource is far less than 1/8 of the prior art, thereby improving the running speed of the T2 system.

Embodiment 2:

Corresponding to the method of the first embodiment, the embodiment of the present invention further provides a resource optimization device in baseband processing, and the device is also applied to the transmitting end of the DVB-T2 system. As shown in FIG. 8 , the device includes cell interleaving. With the time interleaving and fusion module 80, the cell interleaving and time interleaving fusion module 80 includes:

A data acquisition unit 81 for acquiring data to be transmitted;

The writing unit 82 is used to write the above-mentioned data to be transmitted in the RAM according to the writing rule of the cell interleaving;

The readout unit 83 is configured to read out the written data to be transmitted from the RAM according to the output rule of time interleaving.

In the embodiment of the present invention, the data to be transmitted is obtained first, then the data to be transmitted is written into the RAM according to the writing rules of cell interleaving, and the written data to be transmitted is read from the RAM according to the output rules of time interleaving. The resource optimization device in the baseband processing provided in this embodiment combines the cell interleaving and time interleaving into one through the cell interleaving and time interleaving fusion module 80, and combines the cell interleaving and time interleaving while ensuring the bit error rate. The occupied RAM resources are reduced to half of the original ones, which reduces the occupied RAM resources and improves the running speed of the T2 system.

FIG. 9 is a schematic structural diagram of another resource optimization apparatus in baseband processing provided by an embodiment of the present invention. As shown in FIG. 9 , the above-mentioned cell interleaving and time interleaving and fusion module 80 is connected to the serial-parallel conversion module 90, and the above-mentioned data acquisition The unit 81 is specifically configured to: receive the data to be transmitted outputted by the serial-to-parallel conversion module 90; the data to be transmitted is composed of cells corresponding to the serial-to-parallel conversion of a plurality of forward error correction FEC blocks respectively.

As shown in FIG. 9 , on the basis of FIG. 8 , the above-mentioned apparatus further includes: a constellation mapping module 91 for performing a constellation mapping operation on the data to be transmitted read out by the readout unit 83 to obtain a constellation point corresponding to the data to be transmitted data.

In some possible embodiments, the readout unit 83 is specifically configured to: according to the output rule of time interleaving, directly read out the out-of-order cells of the data to be transmitted from the RAM.

In some other possible embodiments, the readout unit 83 is specifically configured to: read out two paths of interleaved data from the RAM, where the two paths of interleaved data are two consecutive cells before the cell interleaving, and one of the interleaved data is according to The output rule of time interleaving is the cell after the data to be transmitted is read out of order directly from the RAM. At this time, the constellation point data includes two channels of constellation data corresponding to the two channels of interleaved data. As shown in FIG. 9 , the device further includes: a constellation rotation module 92 for performing a constellation rotation operation on the two channels of constellation data to obtain Constellation point data after constellation rotation.

In FIG. 9, the data (bit width is 8) output by the serial-parallel conversion module 90 directly passes through a pair of RAMs with a bit width of 8 and a depth of (N _cells ×N _fec ) to complete cell and time interleaving (ping-pong operation), After passing through the constellation mapping module 91 (bit width becomes 32), and then passing through the constellation rotation module 92 (bit width is 32), since the input of the constellation rotation module 92 directly contains two-way data for rotation, there is no need for RAM storage, Therefore, the RAM resource used by the device is (8×N _cells ×N _fec ×2).

Embodiment three:

10, an embodiment of the present invention further provides an electronic device 100, including: a processor 1001, a memory 1002, a bus 1003 and a communication interface 1004, the processor 1001, the communication interface 1004 and the memory 1002 are connected through the bus 1003; processing The processor 1001 is used to execute executable modules, such as computer programs, stored in the memory 1002 .

The memory 1002 may include a high-speed random access memory (RAM, Random Access Memory), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 1004 (which may be wired or wireless), which may use the Internet, a wide area network, a local network, a metropolitan area network, and the like.

The bus 1003 may be an ISA bus, a PCI bus, an EISA bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one bidirectional arrow is shown in FIG. 10, but it does not mean that there is only one bus or one type of bus.

The memory 1002 is used to store a program, and the processor 1001 executes the program after receiving the execution instruction. The method executed by the device defined by the stream process disclosed in any of the foregoing embodiments of the present invention can be applied to processing in the processor 1001, or implemented by the processor 1001.

The processor 1001 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above-mentioned method can be completed by an integrated logic circuit of hardware in the processor 1001 or an instruction in the form of software. The above-mentioned processor 1001 may be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it may also be a digital signal processor (Digital Signal Processing, DSP for short) , Application Specific Integrated Circuit (ASIC for short), Field-Programmable Gate Array (FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. Various methods, steps, and logical block diagrams disclosed in the embodiments of the present invention can be implemented or executed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present invention may be directly embodied as executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory 1002, and the processor 1001 reads the information in the memory 1002, and completes the steps of the above method in combination with its hardware.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, for the specific working process of the apparatus and electronic device described above, reference may be made to the corresponding process in the foregoing method embodiments, which will not be repeated here.

The resource optimization apparatus and electronic device in baseband processing provided by the embodiments of the present invention have the same technical features as the resource optimization method in baseband processing provided by the above-mentioned embodiments, so they can also solve the same technical problems and achieve the same technical effects .

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more functions for implementing the specified logical function(s) executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented in dedicated hardware-based systems that perform the specified functions or actions , or can be implemented in a combination of dedicated hardware and computer instructions.

The computer program product for performing the resource optimization method in baseband processing provided by the embodiment of the present invention includes a computer-readable storage medium storing non-volatile program code executable by the processor, and the instructions included in the program code can be used for The methods described in the foregoing method embodiments are performed. For specific implementation, reference may be made to the method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed method, apparatus and electronic device may be implemented in other manners. The apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-executable non-volatile computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

Finally, it should be noted that the above-mentioned embodiments are only specific implementations of the present invention, and are used to illustrate the technical solutions of the present invention, but not to limit them. The protection scope of the present invention is not limited thereto, although referring to the foregoing The embodiment has been described in detail the present invention, those of ordinary skill in the art should understand: any person skilled in the art who is familiar with the technical field within the technical scope disclosed by the present invention can still modify the technical solutions described in the foregoing embodiments. Or can easily think of changes, or equivalently replace some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be covered in the present invention. within the scope of protection. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A resource optimization method in baseband processing, wherein the method is applied in a DVB-T2 system transmitter, and the method comprises: Get the data to be transmitted; Write the data to be transmitted into the RAM according to the writing rule of the cell interleaving; Read out the written data to be transmitted from the RAM according to the output rule of time interleaving; A constellation mapping operation is performed on the data to be transmitted read out from the RAM to obtain constellation point data corresponding to the data to be transmitted. 2. The method according to claim 1, wherein the acquiring the data to be transmitted comprises: Receive the to-be-transmitted data output by the serial-to-parallel conversion module; the to-be-transmitted data is composed of corresponding cells after serial-to-parallel conversion of a plurality of forward error correction FEC blocks. 3. The method according to claim 2, wherein the data to be transmitted that is written according to the output rule of time interleaving is read out from the RAM, comprising: According to the output rule of time interleaving, the out-of-order cells of the data to be transmitted are directly read from the RAM. 4. The method according to claim 3, wherein the method further comprises: After performing a ping-pong operation on the constellation point data, a constellation rotation operation is performed to obtain the constellation point data after the constellation rotation. 5. The method according to claim 2, wherein the data to be transmitted that is written according to the output rule of time interleaving is read out from the RAM, comprising: Read two interleaved data from the RAM, the two interleaved data are two consecutive cells before cell interleaving, and one of the interleaved data is directly read from the RAM according to the output rule of time interleaving The cell after the data to be transmitted is out of sequence; The constellation point data includes two channels of constellation data corresponding to the two channels of interleaved data, and the method further includes: Perform a constellation rotation operation on the two-way constellation data to obtain constellation point data after constellation rotation. 6. A resource optimization device in baseband processing, wherein the device is applied in a DVB-T2 system transmitting end, and the device comprises a cell interleaving and time interleaving fusion module, the cell interleaving and time interleaving Fusion modules include: a data acquisition unit, used to acquire the data to be transmitted; a writing unit, for writing the data to be transmitted into the RAM according to the writing rule of the cell interleaving; a read-out unit, configured to read out the written data to be transmitted from the RAM according to the output rule of time interleaving; A constellation mapping module, configured to perform a constellation mapping operation on the data to be transmitted read out from the readout unit to obtain constellation point data corresponding to the data to be transmitted. 7. The device according to claim 6, wherein the data acquisition unit is specifically used for: The to-be-transmitted data output by the serial-to-parallel conversion module is received; the to-be-transmitted data is composed of corresponding cells after serial-to-parallel conversion of a plurality of forward error correction FEC blocks. 8. The device according to claim 7, wherein the readout unit is specifically used for: According to the output rule of time interleaving, the out-of-order cells of the data to be transmitted are directly read from the RAM. 9. The device according to claim 7, wherein the readout unit is specifically used for: Read two interleaved data from the RAM, the two interleaved data are two consecutive cells before cell interleaving, and one of the interleaved data is directly read from the RAM according to the output rule of time interleaving The cell after the data to be transmitted is out of sequence; The constellation point data includes two channels of constellation data corresponding to the two channels of interleaved data, and the device further includes: The constellation rotation module is used for performing a constellation rotation operation on the two-way constellation data to obtain the constellation point data after the constellation rotation. 10. An electronic device comprising a memory and a processor, wherein a computer program that can be run on the processor is stored in the memory, wherein the processor implements claim 1 when executing the computer program to the method of any one of 5.

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