CN108039362B - Transistor, clamping circuit and integrated circuit - Google Patents

Abstract

The invention discloses a transistor, a clamping circuit and an integrated circuit. The transistor comprises: a substrate, an oxide layer and a silicon layer; A doping type of heavy doping; a polysilicon gate is arranged on the channel region; the gate is sequentially divided into a first segment region, a second segment region and a third segment region along the first direction, wherein the first direction is the source The direction from the region to the drain region, wherein the first segment region is heavily doped with the second doping type, the second segment region is all undoped polysilicon, and the third segment region is heavily doped with the first doping type The first doping type is different from the second doping type. The device and circuit provided by the present invention are used to solve the technical problem that the MOSFET used for electrostatic protection in the prior art cannot take into account both the electrostatic protection capability and the leakage control. The technical effect of reducing leakage current is achieved on the basis of ensuring the ESD protection capability.

Description

Transistor, clamping circuit and integrated circuit

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a transistor, a clamp circuit, and an integrated circuit.

Background

With the progress of integrated circuit technology, the feature size of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is getting smaller and smaller, and the thickness of a gate Oxide layer is getting thinner and thinner, and under this trend, it is very important to use a high performance electrostatic Discharge (ESD) protection device to Discharge electrostatic charges to protect the gate Oxide layer. ESD is a transient process in which a large amount of static charge is poured into an integrated circuit from the outside inwards when the pins of the integrated circuit are floating, and the whole process takes about 1 us. High voltages of hundreds or even thousands of volts are generated during the electrostatic discharge of the integrated circuit, and the gate oxide of the input stage in the integrated circuit is broken down. In order to be able to withstand such high esd voltages, integrated circuit products must typically use esd protection devices with high performance and high endurance.

With the rapid progress of Silicon-On-Insulator (SOI) technology On insulating substrates, ESD protection of SOI integrated circuits has become a major reliability design issue. The Clamp circuit Power Clamp shown in fig. 1 is often used for ESD protection between the SOI integrated circuit VDD and VSS, and a typical RC triggered Power Clamp, a RC time constant based control circuit, is designed to control the turn-on of an NMOS device having its drain (drain) connected to VDD and its source (source) connected to VSS. When an ESD voltage appears across the VDD and VSS power lines, the NMOS device is turned on to form a temporary low impedance path between VDD and VSS, and ESD discharge current is drained by the NMOS device. By using the ESD clamping circuit, ESD discharge of VDD to VSS can be effectively prevented.

In order to effectively discharge ESD current, a relatively large mos (BigFET) is required for a typical RC-triggered Power clamp, and the specific structure is shown in fig. 2, where the channel width of the BigFET is about 1000um to 5000 um. Such a large BigFET placed between VDD and VSS can produce a relatively large leakage.

Currently, leakage is generally reduced by adjusting the BigFET channel length L and channel width W in Power Clamp. Increasing the channel length L and decreasing the channel width W may reduce the leakage to some extent, but increasing the channel length L and decreasing the channel width W may reduce the ESD protection capability of the Power Clamp.

That is, the MOSFET used for electrostatic protection in the related art has a technical problem that electrostatic protection capability and leakage control cannot be compatible.

Disclosure of Invention

The invention provides a transistor, a clamping circuit and an integrated circuit, and solves the technical problem that the electrostatic protection capability and the electric leakage control of a MOSFET (metal oxide semiconductor field effect transistor) for electrostatic protection in the prior art cannot be considered at the same time.

On one hand, in order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:

a metal oxide semiconductor field effect transistor comprising:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

Optionally, the transistor is a field effect transistor BigFET with a channel width greater than 2000 um.

Optionally, the first doping type is N + doping, and the second doping type is P + doping; or, the first doping type is P + doping, and the second doping type is N + doping.

Optionally, a silicon dioxide layer is disposed between the polysilicon and the channel region.

Optionally, under the condition that the gate is not powered on, a first overlapping region is formed between the channel region and the source region, and a second overlapping region is formed between the channel region and the drain region; the second section area and the third section area all cover the second overlapping area, and a boundary of the second section area and the third section area is located above the second overlapping area.

Optionally, the transistor is used for a clamp circuit.

In another aspect, a clamp circuit is provided, the clamp circuit including a metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor including:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

Optionally, the clamp circuit is a detection circuit triggered clamp circuit.

In yet another aspect, a silicon-on-insulator (SOI) integrated circuit on an insulating substrate is provided, the circuit comprising a clamp for electrostatic protection, the clamp comprising a metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor comprising:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

Optionally, the clamp circuit is a detection circuit triggered clamp circuit.

One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

in the transistor, the clamp circuit and the integrated circuit provided by the embodiment of the application, the second section region and the third section region of the gate polycrystalline silicon, which are close to the drain region, adopt the non-doped polycrystalline silicon and the heavily doped staggered structure with the same doping type as the source and drain regions, so that the electric field of the gate-drain overlapped region is reduced, the gate-induced drain leakage current (GIDL) is reduced, the doping types of the first section region of the gate polycrystalline silicon and the channel region are further set to be different, the threshold voltage of the channel region is properly improved, and the sub-threshold leakage is further reduced. The leakage is reduced by improving the doping of the polysilicon, the channel length L or the channel width W does not need to be adjusted, and the leakage can be reduced on the basis of ensuring the ESD protection capability.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a circuit diagram of a prior art BigFET for a clamp circuit;

FIG. 2 is a block diagram of a prior art BigFET;

FIG. 3 is a structural diagram of a BigFET in an embodiment of the present application;

FIG. 4 is a first circuit diagram of a BigFET for a clamp circuit according to an embodiment of the present application;

FIG. 5 is a second circuit diagram of a BigFET for a clamp circuit according to an embodiment of the present application;

fig. 6 is a third circuit diagram of the BigFET used in the clamp circuit in the embodiment of the present application.

Detailed Description

The embodiment of the application provides a transistor, a clamping circuit and an integrated circuit, and solves the technical problem that an MOSFET for electrostatic protection in the prior art cannot give consideration to electrostatic protection capability and leakage control. The technical effect of reducing electric leakage is realized on the basis of ensuring the ESD protection capability.

In order to solve the above technical problem, the general idea of the technical solution provided in the embodiments of the present application is as follows:

the present application provides a metal oxide semiconductor field effect transistor, comprising:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

In the transistor, the clamp circuit and the integrated circuit provided by the embodiment of the application, the second section region and the third section region of the gate polycrystalline silicon, which are close to the drain region, adopt the non-doped polycrystalline silicon and the heavily doped staggered structure with the same doping type as the source and drain regions, so that the electric field of the gate-drain overlapped region is reduced, the gate-induced drain leakage current (GIDL) is reduced, the doping types of the first section region of the gate polycrystalline silicon and the channel region are further set to be different, the threshold voltage of the channel region is properly improved, and the sub-threshold leakage is further reduced. The leakage is reduced by improving the doping of the polysilicon, the channel length L or the channel width W does not need to be adjusted, and the leakage can be reduced on the basis of ensuring the ESD protection capability.

In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and the embodiments of the present invention are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and the embodiments of the present application may be combined with each other without conflict.

Example one

In the present embodiment, there is provided a metal oxide semiconductor field effect transistor, as shown in fig. 3, including:

a substrate 1, an oxide layer 2 located on the substrate 1, a silicon layer 3 located on the oxide layer 2;

a source region 4 and a drain region 5 are arranged on the silicon layer 3, and a channel region 6 is arranged between the source region 4 and the drain region 5, wherein the source region 4 and the drain region 5 are both heavily doped with a first doping type;

the channel region 6 is provided with a polysilicon 7, and the polysilicon 7 is a grid electrode of the metal oxide semiconductor field effect transistor;

the gate is sequentially divided into a first section area 71, a second section area 72 and a third section area 73 along a first direction, wherein the first direction is the direction from the source area 4 to the drain area 5, the first section area 71 is heavily doped with a second doping type, the second section area 72 is undoped polysilicon, the third section area 73 is heavily doped with the first doping type, and the first doping type is different from the second doping type.

In the embodiment of the application, the transistor is used for clamping a circuit Power clamp to carry out ESD protection on the SOI integrated circuit. Further, in order to achieve effective ESD current discharge, the transistor is a field effect transistor BigFET with a channel width greater than 2000um, and certainly, in a specific implementation process, the transistor may also be a MOSFET with a common size, which is not limited herein.

Before describing the transistor provided in this embodiment in detail, the following prior art bigfets will be described. The conventional RC Power Clamp is shown in fig. 1, wherein the transistor 101 is a conventional BigFET, and the specific device structure is shown in fig. 2, the gate polysilicon is doped in a single type, the doping type of the gate polysilicon is the same as the doping type of the source, the doping type of the gate polysilicon is the same as the doping type of the drain, when the gate polysilicon is NMOS, the doping is N + doping, and when the gate polysilicon is PMOS, the doping is P + doping. The leakage of the existing BigFET of this structure is mainly composed of sub-threshold leakage and GIDL.

The existing BigFET structure is improved, grid polycrystalline silicon is changed into multi-doping in different areas, a third section area 73 closest to the drain area 5 is set to be heavily doped with a first doping type, a second section area 72 closer to the drain area is set to be undoped polycrystalline silicon, the rest first section area 71 is set to be heavily doped with a second doping type, and the first doping type is the same as the doping type of the source area 4 and the doping type of the drain area 5.

In the specific implementation process, the heavy doping means that the doping concentration is 1 x 10¹⁹cm^-3The doping is carried out.

In the embodiment of the present application, as shown in fig. 3, when the MOSFET is an NMOS, the first doping type is N + doping, and the second doping type is P + doping; when the MOSFET is a PMOS, the first doping type is P + doping, and the second doping type is N + doping.

Further, since a first overlap region 61 is formed between the channel region 6 and the source region and a second overlap region 62 is formed between the channel region 6 and the drain region under the condition that the gate polysilicon 7 is not energized; the second overlap region 62 is completely covered by the area formed by the second section area 72 and the third section area 73, and as shown in fig. 3, the third section area 73 is completely located on the second overlap region 62, and the second section area 72 is completely or partially located on the second overlap region 62.

Specifically, considering the NMOS device on the deep submicron SOI integrated circuit, the leakage of the NMOS device mainly comprises GIDL leakage and subthreshold leakage, the third section region 73, closest to the drain region 5, of the grid polycrystalline silicon 7 is set to be heavily doped with the same doping type as the source region and the drain region, the influence of the alignment error in the process on the leakage of the device can be reduced, and the injection of the drain region is ensured to be the same as the doping type of the region. The undoped polysilicon in the second segment region 72 of the second overlap region 62 can reduce the electric field in the gate-drain overlap region, thereby reducing the tunneling current caused by GIDL, and further the doping types of the first segment region 71 of the gate polysilicon 7 and the channel region are set to be different, so as to properly improve the threshold voltage of the channel region, further reduce the sub-threshold leakage, and reduce the sub-threshold leakage and the GIDL tunneling leakage at the same time.

In the present embodiment, silicon dioxide 8 is disposed between the polysilicon 7 and the channel region 6.

Based on the same inventive concept, the present application further provides a clamp circuit including the transistor in the first embodiment, which is described in detail in the second embodiment.

Example two

The present embodiment provides a clamp circuit, as shown in fig. 4 to 6, the clamp circuit includes a metal oxide semiconductor field effect transistor 401, and the metal oxide semiconductor field effect transistor 401 includes:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

In the embodiment of the present application, the clamp is a detection circuit triggered clamp, and is an ESD protection circuit used in an SOI integrated circuit.

In a specific implementation process, the clamp circuit may have various circuit structures, and 3 types are listed as examples below:

first, as shown in fig. 4, when a large current is generated by ESD, the mosfet 401 normally turns on a channel to drain an ESD current, and after the current reaches a certain level, a parasitic Bipolar Junction Transistor (BJT) of the mosfet 401 turns on to drain the ESD current, so that even if the threshold voltage Vth is increased, the capability of normally turning on the drain current is reduced, but the final total ESD current drain capability is not reduced.

Secondly, as shown in fig. 5, the circuit has a simple structure, so that the response is fast, and the protection effect of the static electricity of the device charging model is good.

Thirdly, as shown in fig. 6, the circuit adopts a substrate triggering technology, which can reduce the turn-on voltage of the mosfet 401 and increase the ESD current discharging capability of the mosfet 401 in the normal on mode.

Since the mosfet in the circuit described in this embodiment is described in detail in the first embodiment, the description thereof will not be repeated. The clamp circuit including the mosfet provided in the first embodiment of the present invention is within the protection scope of the present application.

Based on the same inventive concept, the present application provides an SOI integrated circuit including the clamp circuit of embodiment two, as detailed in embodiment three.

EXAMPLE III

The present embodiment provides a silicon-on-insulator SOI integrated circuit on an insulating substrate, the circuit including the clamp circuit for electrostatic protection described in the second embodiment, the clamp circuit including the mosfet described in the first embodiment, the mosfet including:

the semiconductor device comprises a substrate, an oxide layer positioned on the substrate, and a silicon layer positioned on the oxide layer;

a source region and a drain region are arranged on the silicon layer, a channel region is arranged between the source region and the drain region, and the source region and the drain region are both heavily doped with a first doping type;

the channel region is provided with polycrystalline silicon, and the polycrystalline silicon is a grid electrode of the metal-oxide semiconductor field effect transistor;

the grid electrode is sequentially divided into a first section area, a second section area and a third section area along a first direction, wherein the first direction is the direction from the source area to the drain area, the first section area is heavily doped with a second doping type, the second section area is undoped polysilicon, the third section area is heavily doped with the first doping type, and the first doping type is different from the second doping type.

In the embodiment of the present application, the clamp circuit is a detection circuit triggered clamp circuit.

Since the clamp circuit in the SOI integrated circuit described in this embodiment is described in detail in the second embodiment, it will not be described in detail here. The clamp circuit described in the second embodiment is included in the protection scope of the present application.

The technical scheme in the embodiment of the application at least has the following technical effects or advantages:

in the transistor, the clamp circuit and the integrated circuit provided by the embodiment of the application, the second section region and the third section region of the gate polycrystalline silicon, which are close to the drain region, adopt the non-doped polycrystalline silicon and the heavily doped staggered structure with the same doping type as the source and drain regions, so that the electric field of the gate-drain overlapped region is reduced, the gate-induced drain leakage current (GIDL) is reduced, the first section region of the gate polycrystalline silicon is further set to be different from the doping type of the channel region, the threshold voltage of the channel region is properly improved, and the sub-threshold leakage is further reduced. The leakage is reduced by improving the doping of the polysilicon, the channel length L or the channel width W does not need to be adjusted, and the leakage can be reduced on the basis of ensuring the ESD protection capability.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. a metal oxide semiconductor field effect transistor, is characterized in that, comprises: a substrate, an oxide layer on the substrate, and a silicon layer on the oxide layer; Wherein, a source region and a drain region are arranged on the silicon layer, and a channel region is formed between the source region and the drain region, wherein the source region and the drain region are both of the first doping type heavily doped; polysilicon is arranged on the channel region, and the polysilicon is the gate of the metal oxide semiconductor field effect transistor; The gate is sequentially divided into a first segment region, a second segment region and a third segment region along a first direction, wherein the first direction is a direction from the source region to the drain region, wherein the The first segment region is heavily doped with the second doping type, the second segment region is all undoped polysilicon, the third segment region is heavily doped with the first doping type, and the third segment region is heavily doped with the first doping type. a doping type is different from the second doping type; When the gate is not powered on, a first overlapping region is formed between the channel region and the source region, and a second overlapping region is formed between the channel region and the drain region; Wherein, the second segment area and the third segment area all cover the second overlapping area, and the boundary line between the second segment area and the third segment area is located between the second overlapping area superior. 2 . The transistor of claim 1 , wherein the transistor is a BigFET with a channel width greater than 2000um. 3 . 3. The transistor of claim 1, wherein: The first doping type is N+ doping, and the second doping type is P+ doping; or, The first doping type is P+ doping, and the second doping type is N+ doping. 4. The transistor of claim 1, wherein a silicon dioxide layer is disposed between the polysilicon and the channel region. 5. The transistor of claim 1, wherein the transistor is used in a clamp circuit. 6. A clamp circuit, wherein the clamp circuit comprises a metal oxide semiconductor field effect transistor, and the metal oxide semiconductor field effect transistor comprises: a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer; A source region and a drain region are arranged on the silicon layer, and a channel region is formed between the source region and the drain region, wherein the source region and the drain region are both heavily doped with the first doping type miscellaneous; polysilicon is arranged on the channel region, and the polysilicon is the gate of the metal oxide semiconductor field effect transistor; The gate is sequentially divided into a first segment region, a second segment region and a third segment region along a first direction, wherein the first direction is a direction from the source region to the drain region, wherein the The first segment region is heavily doped with the second doping type, the second segment region is all undoped polysilicon, the third segment region is heavily doped with the first doping type, and the third segment region is heavily doped with the first doping type. a doping type is different from the second doping type; When the gate is not powered on, a first overlapping region is formed between the channel region and the source region, and a second overlapping region is formed between the channel region and the drain region; Wherein, the second segment area and the third segment area all cover the second overlapping area, and the boundary line between the second segment area and the third segment area is located between the second overlapping area superior. 7 . The clamping circuit of claim 6 , wherein the clamping circuit is a detection circuit trigger type clamping circuit. 8 . 8. A silicon SOI integrated circuit on an insulating substrate, wherein the circuit comprises a clamp circuit for electrostatic protection, the clamp circuit comprises a metal oxide semiconductor field effect transistor, and the metal oxide Semiconductor field effect transistors include: a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer; A source region and a drain region are arranged on the silicon layer, and a channel region is formed between the source region and the drain region, wherein the source region and the drain region are both heavily doped with the first doping type miscellaneous; polysilicon is arranged on the channel region, and the polysilicon is the gate of the metal oxide semiconductor field effect transistor; The gate is sequentially divided into a first segment region, a second segment region and a third segment region along a first direction, wherein the first direction is a direction from the source region to the drain region, wherein the The first segment region is heavily doped with the second doping type, the second segment region is all undoped polysilicon, the third segment region is heavily doped with the first doping type, and the third segment region is heavily doped with the first doping type. a doping type is different from the second doping type; When the gate is not powered on, a first overlapping region is formed between the channel region and the source region, and a second overlapping region is formed between the channel region and the drain region; Wherein, the second segment area and the third segment area all cover the second overlapping area, and the boundary line between the second segment area and the third segment area is located between the second overlapping area superior. 9 . The integrated circuit of claim 8 , wherein the clamp circuit is a detection circuit trigger type clamp circuit. 10 .

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