CN108021521B - A system and cascade configuration method for changing system topology configuration based on BMC - Google Patents
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Abstract
本发明提供一种基于BMC更改系统拓扑配置的系统以及级联配置方法，BMC管理模块的信号输出端与总线端口模块信号输入端连接，总线端口模块与第一输入输出模块信号输入端连接，第一输入输出模块信号输出端与第一切换模块信号输入端连接，第二输入输出模块与第二切换模块第一信号输入端连接，第三输入输出模块与第二切换模块第二信号输入端连接；通过BMC管理模块实现不同配置之间的切换，实现对服务器不同场景中的应用。避免了现有的方案将STRAP pin信号连接至3‑pin跳帽，实际应用中，用户需要进入现场打开机箱并手动调整跳帽位置才能实现对拓扑结构的更换。实现对芯片端口状态配置的更改，方便用户操作。
The invention provides a system for changing system topology configuration based on BMC and a cascade configuration method. The signal output end of the BMC management module is connected with the signal input end of the bus port module, the bus port module is connected with the signal input end of the first input and output module, A signal output end of an input and output module is connected to the signal input end of the first switching module, a second input and output module is connected to the first signal input end of the second switching module, and a third input and output module is connected to the second signal input end of the second switching module ; Realize the switch between different configurations through the BMC management module, and realize the application in different scenarios of the server. It avoids the existing solution to connect the STRAP pin signal to the 3‑pin jumper cap. In practical applications, the user needs to enter the site to open the chassis and manually adjust the jumper cap position to replace the topology. Realize the change of the chip port state configuration, which is convenient for the user to operate.
Description
Technical Field
The invention relates to the field of servers, in particular to a system for changing system topology configuration based on BMC and a cascade configuration method.
Background
In the server based on the Intel platform, each CPU supports a maximum of 48 channels (Lane), which is sufficient for the traditional server, but obviously the resource cannot meet the requirement for the high-density server. Generally, X16 channels are usually required for high-end explicit caine 3D operation throughput, such server platforms have special requirements for PCIE resources, and PCIE Switch is developed to cope with the limitation of the number of channels. When the server system is configured with a plurality of chips, a user can switch the interconnection topological structure between the chips according to the actual application scene so as to meet the performance requirement.
To implement topology switching, current server designs typically employ a method of reserving a hop cap. The concrete design is as follows: and leading out related STRAP signals of the chip and respectively connecting the related STRAP signals to the 3-pin jump cap. The server uses a jump cap to lock the signal in a default state according to the requirement; the user can manually adjust the position of the jump cap, change the voltage of the STRAP pins signal to configure the state of the PCIE Switch port, and the change of the system topology can be realized after the Switch is started.
When the jump cap is used for changing topology in drop and oscillation tests, the risk of falling off of the jump cap is easily caused; meanwhile, the case needs to be opened when the jump cap is manually adjusted, and operation of a user is not facilitated.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a system for changing the topology configuration of a system based on BMC, which comprises: the system comprises a BMC management module, a bus port module, a first input/output module, a second input/output module, a third input/output module, a first switching module, a second switching module and a CPU;
the signal output end of the BMC management module is connected with the signal input end of the bus port module, the first signal output end of the bus port module is connected with the signal input end of the first input/output module, the second signal output end of the bus port module is connected with the signal input end of the second input/output module, the third signal output end of the bus port module is connected with the signal input end of the third input/output module, the signal output end of the first input/output module is connected with the signal input end of the first switching module, the signal output end of the second input/output module is connected with the first signal input end of the second switching module, and the signal output end of the third input/output module is connected with the second signal input end of the second switching module;
the signal output end of the first switching module is connected with the first signal input end of the CPU, and the signal output end of the second switching module is connected with the second signal input end of the CPU;
the first switching module is provided with a first interconnection port connected with the second switching module;
the second switching module is provided with a second interconnection port connected with the first switching module;
the first switching module and the second switching module are interconnected with the second interconnection port through the first interconnection port.
Preferably, the BMC management module adopts an AST2500 chip;
the bus port module adopts a PCA9555 chip;
the SCL pin of the BMC management module is connected with the first end of the resistor R1 and the SCL pin of the bus port module respectively; the second end of the resistor R1 is connected with the power supply;
an SDA pin of the BMC management module is respectively connected with a first end of a resistor R2 and an SDA pin of the bus port module; the second end of the resistor R2 is connected with the power supply.
Preferably, the first input-output module, the second input-output module and the third input-output module respectively adopt an SN74AUP1G07 chip;
the first input/output module, the second input/output module and the third input/output module are single input/output equipment respectively;
the bus port module is provided with a first output pin group and a second output pin group, and an IOO _ O pin of the first output pin group of the bus port module is connected with the signal input end of the first input/output module;
the IOO _1 pin of the first output pin group of the bus port module is connected with the signal input end of the second input/output module;
the IOO _7 pin of the second pin set of the bus port module is connected to the signal input terminal of the third input/output module.
Preferably, the first switching module and the second switching module respectively adopt PEX9797 chips;
the signal output end of the first input and output module is connected with the STRAP _ STNX _ PORTCDFG1 pin of the first switching module;
the signal output end of the second input/output module is connected with a STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module;
the signal output end of the third input-output module is connected with the pin STRAP _ VS0_ UPSTRM _ PORTSEL0 of the second switching module.
Preferably, the first switching module and the second switching module are respectively provided with four groups of expansion hard disk connection ports.
Preferably, the first interconnection port of the first switching module includes: the first cascade port, the second cascade port, the third cascade port, the fourth cascade port and the fifth cascade port;
the first interconnection port of the second switching module includes: the first cascade two port, the second cascade two port, the third cascade two port, the fourth cascade two port and the fifth cascade two port;
the first cascade one port is connected with the first cascade two port; the second cascade one port is connected with the second cascade two port; the third cascade one port is connected with the third cascade two port; the fourth cascade one port is connected with the fourth cascade two port; the fifth cascade one port is connected with the fifth cascade two port.
Preferably, the signal output end of the first switching module is connected with a pin of a PCIE Root Port2 of the CPU, and the signal output end of the second switching module is connected with a pin of a PCIE Root Port1 of the CPU.
A method for changing system cascade configuration based on BMC comprises the following steps:
executing shutdown operation under BMC Web, and performing configuration switching operation through a BMC management module;
the BMC management module pulls down the STRAP _ STNX _ PORTCDFG1 pin of the first switching module through the bus port module, and the cascade ports of the first switching module are configured to be PCIE X16;
the STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module and
pins STRAP _ VS0_ UPSTRM _ PORTSEL0 are all pulled high, and the cascade port of the second switching module is configured to be Upstream;
after the system is started, the BMC management module sets the PCIE Root Port2 of the current CPU to disable so as to ensure that the PCIE Link between the CPU and the second switching module is closed;
the BMC management module interconnects all the cascade ports of the first switching module with the cascade ports of the second switching module to realize cascade connection of the first switching module and the second switching module.
According to the technical scheme, the invention has the following advantages:
and switching between different configurations is realized through the BMC management module, and application to the server in different scenes is realized. The situation that the existing scheme connects the STRAP pin signal to the 3-pin jump cap is avoided, and in practical application, a user needs to enter a field to open a case and manually adjust the position of the jump cap to replace a topological structure. The change of the state configuration of the chip port is realized, and the operation of a user is facilitated.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an overall system for modifying a topology configuration of a system based on a BMC;
FIG. 2 is a schematic diagram of the interconnection among the BMC management module, the bus port module, and the I/O module;
FIG. 3 is a schematic diagram of the interconnection between a first input/output module and a first switching module;
FIG. 4 is a schematic diagram illustrating the interconnection of a second input/output module, a third input/output module and a second switching module;
FIG. 5 is a schematic diagram of the interconnection of the first switching module, the second switching module and the CPU;
FIG. 6 is a flow chart of a method for modifying the cascade configuration of a system based on BMC.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of this patent.
The invention provides a system for changing system topology configuration based on BMC, as shown in FIG. 1, comprising: a BMC management module 1, a bus port module 2, a first input/output module 3, a second input/output module 4, a third input/output module 5, a first switching module 6, a second switching module 7 and a CPU 8;
the signal output end of the BMC management module 1 is connected with the signal input end of a bus port module 2, the first signal output end of the bus port module 2 is connected with the signal input end of a first input/output module 3, the second signal output end of the bus port module 2 is connected with the signal input end of a second input/output module 4, the third signal output end of the bus port module 2 is connected with the signal input end of a third input/output module 5, the signal output end of the first input/output module 3 is connected with the signal input end of a first switching module 6, the signal output end of the second input/output module 4 is connected with the first signal input end of a second switching module 7, and the signal output end of the third input/output module 5 is connected with the second signal input end of the second switching module 7;
the signal output end of the first switching module 6 is connected with a first signal input end of the CPU8, and the signal output end of the second switching module 7 is connected with a second signal input end of the CPU 8; the first switching module 6 is provided with a first interconnection port connected with the second switching module 7; the second switching module 7 is provided with a second interconnection port connected with the first switching module 6; the first switching module 6 and the second switching module 7 are interconnected with the second interconnection port through the first interconnection port.
As shown in fig. 2, a BMC management module 1 employs an AST2500 chip; the bus port module 2 adopts a PCA9555 chip;
the SCL pin of the BMC management module 1 is connected with the first end of the resistor R1 and the SCL pin of the bus port module 2 respectively; the second end of the resistor R1 is connected with the power supply; an SDA pin of the BMC management module 1 is respectively connected with a first end of a resistor R2 and an SDA pin of the bus port module 2; the second end of the resistor R2 is connected with the power supply.
In this embodiment, as shown in fig. 3 and 4, the first input/output module 3, the second input/output module 4, and the third input/output module 5 respectively adopt SN74AUP1G07 chips;
the first input/output module 3, the second input/output module 4 and the third input/output module 5 are single input/output devices respectively; the bus port module 2 is provided with a first output pin group and a second output pin group, and an IOO _ O pin of the first output pin group of the bus port module 2 is connected with a signal input end of the first input/output module 3; the IOO _1 pin of the first output pin group of the bus port module 2 is connected with the signal input end of the second input/output module 4; the IOO _7 pin of the second pin group of the bus port module 2 is connected to the signal input terminal of the third input/output module 5.
In this embodiment, as shown in fig. 5, the first switching module 6 and the second switching module 7 respectively employ PEX9797 chips;
the signal output end of the first input and output module 3 is connected with the pin STRAP _ STNX _ PORTCDFG1 of the first switching module 6; the signal output end of the second input/output module 4 is connected with the STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module 7; the signal output terminal of the third input/output module 5 is connected to pin STRAP _ VS0_ UPSTRM _ PORTSEL0 of the second switching module 7.
The first switching module 6 and the second switching module 7 are respectively provided with four groups of expansion hard disk connecting ports 11. The first interconnection port of the first switching module 6 includes: a first cascade one port 21, a second cascade one port 22, a third cascade one port 23, a fourth cascade one port 24, a fifth cascade one port 25; the first interconnection port of the second switching module 7 includes: a first cascaded two port 31, a second cascaded two port 32, a third cascaded two port 33, a fourth cascaded two port 34, a fifth cascaded two port 35;
the first cascade one port 21 is connected with the first cascade two port 31; the second cascade one port 22 is connected with the second cascade two port 32; the third cascade one port 23 is connected with the third cascade two port 33; the fourth cascaded first port 24 is connected with the fourth cascaded second port 34; the fifth cascade one port 25 is connected to the fifth cascade two port 35. The signal output end 26 of the first switching module 6 is connected with a PCIE Root Port2 pin of the CPU8, and the signal output end 36 of the second switching module 7 is connected with a PCIE Root Port1 pin of the CPU 8.
In this embodiment, based on the pure platform, the port state switching is implemented through different configurations of the BMC management module to the STRAP pin level of the PCIE Switch chip, so as to change the system topology. After reading and writing PCA9555, the BMC management module configures STRAP pin through OD Buffer to determine the Station Link width and Upstream Port of the Switch chip.
The PCA9555 is a chip for the IIC application to GPIO resource expansion, and provides a bus for the application of an inductor, a switch key, an LED lamp, a fan and the like. The chip is composed of two groups of 8-bit configuration and corresponding registers, and the system can access the corresponding registers through the IIC bus to realize the configuration of the I/O ports, including input/output, Active High/Low, policy Inversion and the like. After the system in this embodiment is powered on, the AST2500 reads and writes some registers of the PCA9555 through the IIC according to the user's needs to configure the high/low state of the I/O port level.
The first input-output module 3, the second input-output module 4 and the third input-output module 5 are all SN74AUP1G07, and the chip is a single input/output device. The VCC range is 0.8V-3.6V, which is convenient for the design of users; the chip 3.6V-I/O margin may support a transition to a low level. The input of the chip is directly interconnected with GPIO of the PCA9555, after power-on, the PCA9555 outputs high level, the output of the input/output module is high, the level of an output port of the input/output module is determined by the input of a rear-stage chip, and the output of the input/output module is low when the output of the PCA9555 outputs low level.
In this embodiment, two PEX9797 chips are involved, the strp _ STN2_ portdfg 1 of the first switching module 6 is used to configure the Port Link Width of the second switching module 7, and the strp _ VS0_ UPSTRM _ Port1, strp _ VS0_ UPSTRM _ Port 0 of the second switching module 7 are used to select the Upstream Port, and the like. The output of the input/output module is directly interconnected with the STRAP Pin of the switching module, and the PCA9555 is different from the VCC voltage of the switching module, so that the input/output module is used for level isolation.
In practical application of the server, the signal output end 26 of the first switch module 6 is connected to the PCIE Port2 pin of the CPU8, and the signal output end 36 of the second switch module 7 is connected to the PCIE Port1 pin of the CPU 8. After the system is powered on, the BMC management module configures the PCA9555 register through the IIC, then pulls the strp _ STN2_ portdfg 1 of the first switching module 6 high, pulls the strp _ VS0_ UPSTRM _ port1 pin and the strp _ VS0_ UPSTRM _ port 0 pin of the second switching module 7 low, and configures the signal output end 36 of the second switching module 7 as an Upstream port.
The signal output end 26 of the first switching module 6 is configured to be connected with four NVME hard disks through four groups of expansion hard disk connection ports 11, so as to realize storage expansion.
The invention also provides a method for changing the cascade configuration of the system based on the BMC, as shown in FIG. 6, the method comprises:
s1, executing shutdown operation under BMC Web, and performing configuration switching operation through a BMC management module;
s2, the BMC management module pulls down the STRAP _ STNX _ PORTCDFG1 pin of the first switching module through the bus port module, and the cascade ports of the first switching module are configured to be PCIE X16;
s3, sum the STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module
Pins STRAP _ VS0_ UPSTRM _ PORTSEL0 are all pulled high, and the cascade port of the second switching module is configured to be Upstream;
s4, after the system is started, the BMC management module sets the PCIE Root Port2 of the current CPU to disable so as to ensure that the PCIE Link between the CPU and the second switching module is closed;
and S5, the BMC management module interconnects all the cascade ports of the first switching module and the cascade ports of the second switching module to realize cascade connection of the first switching module and the second switching module.
The modes are all realized through a BMC management module, and a user can realize the switching between different configurations of the system only through remote control and operation on a BMC web, so that the application to different scenes of the server is realized. The situation that the existing scheme connects the STRAP pin signal to the 3-pin jump cap is avoided, and in practical application, a user needs to enter a field to open a case and manually adjust the position of the jump cap to replace a topological structure.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A system for changing a topology configuration of a system based on BMC, comprising: the system comprises a BMC management module (1), a bus port module (2), a first input/output module (3), a second input/output module (4), a third input/output module (5), a first switching module (6), a second switching module (7) and a CPU (8);
the signal output end of the BMC management module (1) is connected with the signal input end of the bus port module (2), the first signal output end of the bus port module (2) is connected with the signal input end of the first input/output module (3), the second signal output end of the bus port module (2) is connected with the signal input end of the second input/output module (4), the third signal output end of the bus port module (2) is connected with the signal input end of the third input/output module (5), the signal output end of the first input/output module (3) is connected with the signal input end of the first switching module (6), the signal output end of the second input/output module (4) is connected with the first signal input end of the second switching module (7), and the signal output end of the third input/output module (5) is connected with the second signal input end of the second switching module (7);
the signal output end of the first switching module (6) is connected with the first signal input end of the CPU (8), and the signal output end of the second switching module (7) is connected with the second signal input end of the CPU (8);
the first switching module (6) is provided with a first interconnection port connected with the second switching module (7);
the second switching module (7) is provided with a second interconnection port connected with the first switching module (6);
the first switching module (6) and the second switching module (7) are interconnected with each other through the first interconnection port and the second interconnection port;
the BMC management module (1) adopts an AST2500 chip;
the bus port module (2) adopts a PCA9555 chip;
the SCL pin of the BMC management module (1) is respectively connected with the first end of the resistor R1 and the SCL pin of the bus port module (2); the second end of the resistor R1 is connected with the power supply;
an SDA pin of the BMC management module (1) is respectively connected with a first end of a resistor R2 and an SDA pin of the bus port module (2); the second end of the resistor R2 is connected with the power supply;
the first input-output module (3), the second input-output module (4) and the third input-output module (5) respectively adopt SN74AUP1G07 chips;
the first input/output module (3), the second input/output module (4) and the third input/output module (5) are single input/output equipment respectively;
the bus port module (2) is provided with a first output pin group and a second output pin group, and an IO0_0 pin of the first output pin group of the bus port module (2) is connected with a signal input end of the first input/output module (3);
an IO0_1 pin of a first output pin group of the bus port module (2) is connected with a signal input end of the second input/output module (4);
an IO0_7 pin of a second output pin group of the bus port module (2) is connected with a signal input end of the third input/output module (5);
the first switching module (6) and the second switching module (7) respectively adopt a PEX9797 chip;
the signal output end of the first input/output module (3) is connected with the STRAP _ STNX _ PORTCDFG1 pin of the first switching module (6);
the signal output end of the second input/output module (4) is connected with a STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module (7);
the signal output end of the third input-output module (5) is connected with the STRAP _ VS0_ UPSTRM _ PORTSEL0 pin of the second switching module (7).
2. The BMC-based system for changing system topology configuration based on claim 1,
the first switching module (6) and the second switching module (7) are respectively provided with four groups of expansion hard disk connecting ports (11).
3. The BMC-based system for changing system topology configuration based on claim 1,
the first interconnection port of the first switching module (6) comprises: a first cascade one port (21), a second cascade one port (22), a third cascade one port (23), a fourth cascade one port (24), a fifth cascade one port (25);
the first interconnection port of the second switching module (7) comprises: a first cascaded two port (31), a second cascaded two port (32), a third cascaded two port (33), a fourth cascaded two port (34), a fifth cascaded two port (35);
the first cascade one port (21) is connected with the first cascade two port (31); the second cascade one port (22) is connected with the second cascade two port (32); the third cascade one port (23) is connected with the third cascade two port (33); the fourth cascade one port (24) is connected with the fourth cascade two port (34); the fifth cascade one port (25) is connected with the fifth cascade two port (35).
4. The BMC-based system for changing system topology configuration based on claim 3,
the signal output end (26) of the first switching module (6) is connected with a PCIE Root Port2 pin of the CPU (8), and the signal output end (36) of the second switching module (7) is connected with a PCIE Root Port1 pin of the CPU (8).
5. A method for changing system cascade based on BMC is characterized in that the method comprises the following steps:
executing shutdown operation under BMC Web, and performing configuration switching operation through a BMC management module;
the BMC management module pulls down the STRAP _ STNX _ PORTCDFG1 pin of the first switching module through the bus port module, and the cascade ports of the first switching module are configured to be PCIE X16;
the STRAP _ VS0_ UPSTRM _ PORTSEL1 pin of the second switching module and
pins STRAP _ VS0_ UPSTRM _ PORTSEL0 are all pulled high, and the cascade port of the second switching module is configured to be Upstream;
after the system is started, the BMC management module sets the PCIE Root Port2 of the current CPU to disable so as to ensure that the PCIE Link between the CPU and the second switching module is closed;
the BMC management module interconnects the cascade ports of the first switching module and the cascade ports of the second switching module to realize cascade connection of the first switching module and the second switching module;
the BMC management module adopts an AST2500 chip; the first switching module and the second switching module respectively adopt a PEX9797 chip.
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|---|---|---|---|---|
| JP4398386B2 (en) * | 2005-01-28 | 2010-01-13 | 富士通株式会社 | Device for interconnecting multiple processing nodes via serial bus |
| CN201562273U (en) * | 2009-11-20 | 2010-08-25 | 四川长虹电器股份有限公司 | High-speed parallel port interface circuit |
| CN102694719B (en) * | 2011-03-25 | 2017-08-15 | 研祥智能科技股份有限公司 | The port configuration method of micro telecommunication computing architecture system, support plate hub module and PCI E exchangers |
| CN103181133B (en) * | 2012-10-26 | 2015-12-02 | 华为技术有限公司 | The server system that Based PC IE exchanges and reverse method and equipment |
| CN104202194B (en) * | 2014-09-10 | 2018-05-29 | 华为技术有限公司 | The collocation method and device of PCIe topologys |
| CN104579772B (en) * | 2014-12-30 | 2018-12-14 | 华为技术有限公司 | The configuring management method of computer equipment and computer equipment |
| CN105721357B (en) * | 2016-01-13 | 2019-09-03 | 华为技术有限公司 | Switching equipment, peripheral parts interconnected High Speed System and its initial method |
| US10387346B2 (en) * | 2016-05-06 | 2019-08-20 | Quanta Computer Inc. | Dynamic PCIE switch reconfiguration mechanism |
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2017
- 2017-12-01 CN CN201711250531.6A patent/CN108021521B/en active Active
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| CN108021521A (en) | 2018-05-11 |
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