CN108011703A - A kind of parallel interface sequential control method and device - Google Patents

Abstract

The embodiment of the present invention discloses a parallel interface timing control method and device, wherein the parallel interface timing control device includes: a register configuration module, a rate self-adaptation module, an interface timing control module, and a data and timing processing module, for realizing Parallel interface rate adaptive configuration.

Description

A parallel interface timing control method and device

technical field

The invention relates to the communication field, in particular to a method and device for controlling the sequence of a parallel interface.

Background technique

JESD207 is the radio front end-Baseband Digital Parallel (RBDP, Radio front end-Baseband Digital Parallel) interface between the RF front-end integrated circuit (RFIC, Radio Front end Integrated Circuit) and the baseband integrated circuit (BBIC, Baseband Integrated Circuit). Transmit digital waveform data of RFIC and BBIC. This interface supports single-antenna and dual-antenna data transmission and reception in time division duplex (TDD, Time Division Duplex) and frequency division duplex mode (FDD, Frequency Division Duplex). Figure 1 shows JESD207 data Interface connection diagram, where MCLK is the channel-associated clock of data sent from RFIC to BBIC, FCLK is the channel-associated clock of data sent from BBIC to RFIC, TXNRX is the data direction indication signal, and ENABLE signal is the start and end indication of data burst transmission , DIQ[11:0] and DIQ[9:0] signals are two-way data transmission buses, which support the transmission of 12bit and 10bit data formats respectively, and can be selected according to needs. All data adopt double data rate (DDR, Double Data Rate).

The JESD207 data interface has the characteristics of occupying less pin resources, low interface rate, and low design difficulty. Although FCLK can be regarded as the MCLK homologous clock for the BBIC interface level, you don’t need to care about the frequency of the clock, you only need to perform the received MCLK It can be output after a delay, but for the post-stage circuit of the BBIC interface, specific MCLK clock cycle information is still needed to understand the data communication rate, so as to provide a data communication rate that matches the post-stage circuit of the BBIC interface to ensure the communication between RFIC and BBIC Therefore, when it is necessary to replace different RFICs during testing, it is necessary to configure the interface rate according to the requirements of each RFIC, which brings inconvenience to testing.

Contents of the invention

In order to solve the existing technical problems, the embodiments of the present invention expect to provide a parallel interface timing control method and device, so as to realize the self-adaptive configuration of the parallel interface rate.

In order to achieve the above object, the technical solution of the embodiment of the present invention is achieved in this way:

In the first aspect, an embodiment of the present invention provides a parallel interface timing control device, the parallel interface timing control device includes: a register configuration module, a rate adaptive module, an interface timing control module, and a data and timing processing module, wherein,

The register configuration module is used to obtain configuration information of the system;

The rate adaptation module is used to generate an updated data communication rate and an adaptive flag through the period information of the MCLK sent by the opposite end when detecting that the first configuration information in the register configuration module is valid, and transfer the updated The data communication rate and the self-adaptation flag are sent to the register configuration module;

The register configuration module is also configured to configure the current data communication rate according to the adaptive flag;

The interface timing control module is configured to generate interface timing according to the second configuration information and MCLK information in the register configuration module;

The data and timing processing module is used to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.

In the above embodiment, the configuration information includes: interface module enablement, number of channels, default data communication rate, TDD mode subframe type, adaptive function enablement, number of times of successful self-adaptation detection, times of self-adaptation failure detection; wherein, The adaptive function enabling corresponds to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.

In the above embodiment, the adaptive flag includes: an adaptive success flag and an adaptive failure flag.

In the above embodiment, the rate adaptation module includes: an MCLK cycle detection submodule, an MCLK clock stability detection submodule, a rate adaptation failure detection submodule, and a rate adaptation information update submodule; wherein,

The MCLK cycle detection submodule is used to obtain the cycle information of the MCLK through the working clock, and send the cycle information of the MCLK to the MCLK clock stability detection submodule and the rate adaptive information update submodule in real time;

The MCLK clock stability detection sub-module is used to trigger the rate adaptive information update sub-module to generate an updated data communication rate when detecting that the cycle information consistency times of two consecutive MCLKs meet the preset adaptive success value , and sending the updated data communication rate to the register configuration module;

The MCLK clock stability detection sub-module is also used to trigger the rate self-adaptation information update sub-module to turn off the self-adaptation function when it is detected that the times of inconsistency of cycle information of two consecutive MCLKs meet the self-adaptation failure value.

Further, the MCLK clock stability detection submodule is specifically used for,

When the period information of two consecutive MCLKs is detected to be consistent, the internal clock stabilization counter performs an accumulation count to obtain a first accumulation count value;

And, when the first accumulated count value reaches a pre-configured adaptive success value, generate a rate adaptive success flag;

And, sending the rate adaptation success flag to the rate adaptation information update submodule and register configuration module;

The rate adaptation information update submodule is used to convert the period information of MCLK into a data communication rate when the rate adaptation success flag is detected;

And, sending the data communication rate converted from the period information of MCLK to the register configuration module as the updated data communication rate.

Further, the MCLK clock stability detection submodule is also used for,

When the cycle information of two consecutive MCLKs is detected to be inconsistent, the internal clock stabilization counter executes a cumulative counting reset to generate an MCLK change flag;

And, sending the MCLK change flag to the rate adaptive failure detection submodule;

The rate adaptive failure detection submodule is used to detect the MCLK change flag, and its internal clock change counter performs an accumulation count operation to obtain a second accumulation count value;

And, when the second accumulated count value reaches a pre-configured adaptive failure value, generating a rate adaptive failure flag;

And, sending the rate adaptation failure flag to the rate adaptation information update submodule and register configuration module;

The rate adaptation information updating sub-module is further configured to disable the rate adaptation function when a rate adaptation failure flag is detected.

In the above embodiment, the register configuration module is also used to:

Configure the current data communication rate as the updated data communication rate according to the adaptive success flag;

And, configure the current data communication rate according to the self-adaptation failure flag as the default data communication rate sent by the system to the register configuration module.

In the above embodiment, the interface timing control module is specifically used for:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, it is used to generate an interface sequence corresponding to uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, it is used to generate the interface timing corresponding to the downlink data communication, and generate the same FCLK timing as the MCLK timing according to the MCLK information delay .

In the above embodiment, the data and timing processing module is specifically used for:

When the data communication type is uplink data communication, receive the uplink data transmitted by the interface timing control module according to the interface timing corresponding to the uplink data communication, and transfer the uplink data according to the number of channels in the register configuration module and the current data communication rate The data is sent to the post-stage circuit of BBIC;

And, when the data communication type is downlink data communication, receive the downlink data transmitted by the subsequent circuit of the BBIC according to the interface timing corresponding to the downlink data communication, and set the said register configuration module according to the number of channels and the current data communication rate. The downlink data is sent to the interface timing control module.

In the second aspect, an embodiment of the present invention provides a parallel interface timing control method, the method is used in a parallel interface timing control device, and the parallel interface timing control device includes: a register configuration module, a rate adaptive module, an interface timing control module and data and timing processing module, the method includes:

The register configuration module acquires configuration information of the system;

When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag through the period information of the MCLK sent by the opposite end, and sends The updated data communication rate and adaptive flag are sent to the register configuration module;

The register configuration module configures the current data communication rate according to the adaptive flag;

The interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module;

The data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.

In the above embodiment, the configuration information includes: interface module enablement, number of channels, default data communication rate, time division duplex TDD mode subframe type, adaptive function enablement, number of times of successful self-adaptation detection, times of self-adaptive failure detection ; Wherein, the adaptive function enabling corresponds to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.

In the above embodiment, the adaptive flag includes: an adaptive success flag and an adaptive failure flag.

In the above embodiment, when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate through the period information of the MCLK sent by the opposite end and adaptive flags, and send the updated data communication rate and adaptive flags to the register configuration module, specifically including:

The rate adaptation module obtains the cycle information of MCLK through the working clock;

When the rate adaptation module detects that the cycle information consistency times of two consecutive MCLKs meet the preset adaptive success value, an updated data communication rate is generated, and the updated data communication rate is sent to the register configuration module;

When the rate adaptation module detects that the number of inconsistencies in the cycle information of two consecutive MCLKs satisfies the adaptive failure value, the adaptive function is turned off.

Further, when the rate adaptation module detects that the number of times the cycle information of the MCLK is consistent twice in a row satisfies the preset adaptive success value, an updated data communication rate is generated and the updated data communication rate is sent to Configure the module for the register, specifically including:

When the rate adaptation module detects that the cycle information of two consecutive MCLKs is consistent, the internal clock stabilization counter of the rate adaptation module performs an accumulation count, and the rate adaptation module obtains a first accumulation count value;

When the first accumulated count value reaches the adaptive success value preconfigured by the rate adaptive module, the rate adaptive module generates a rate adaptive success flag;

When the rate adaptation module detects the rate adaptation success flag, the rate adaptation module converts the period information of MCLK into a data communication rate;

The rate adaptation module sends the data communication rate converted from the period information of MCLK to the register configuration module as an updated data communication rate.

Further, when the MCLK clock stability detection submodule detects that the cycle information inconsistency of two consecutive MCLKs meets the adaptive failure value, trigger the rate adaptive information update submodule to turn off the adaptive function, specifically including:

When the rate adaptation module detects that the period information of two consecutive MCLKs is inconsistent, the internal clock stabilization counter of the rate adaptation module executes an accumulated count clearing, and the rate adaptation module generates an MCLK change flag;

When the rate adaptation module detects the MCLK change flag, the clock change counter in the rate adaptation module performs an accumulation count operation, and the rate adaptation module obtains a second accumulation count value;

When the second accumulated count value reaches the adaptive failure value preconfigured by the rate adaptive module, the rate adaptive module generates a rate adaptive failure flag;

The rate adaptation module sends the rate adaptation failure flag to the register configuration module;

When the rate adaptation module detects the rate adaptation failure flag, the rate adaptation module disables the rate adaptation function.

In the above embodiment, the register configuration module configures the current data communication rate according to the adaptive flag, specifically including:

The register configuration module configures the current data communication rate as the updated data communication rate according to the adaptive success flag;

The register configuration module configures the current data communication rate as the default data communication rate sent by the system to the register configuration module according to the self-adaptation failure flag.

In the above embodiment, the interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module, specifically including:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface timing control module generates an interface timing corresponding to uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface timing control module generates interface timing corresponding to downlink data communication, and the interface timing control module according to the MCLK information The delay generates the same FCLK timing as the MCLK timing.

In the above embodiment, the data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate, specifically including:

When the data communication type is uplink data communication, the data and timing processing module receives the uplink data transmitted by the interface timing control module according to the interface timing corresponding to the uplink data communication, and the data and timing processing module configures the module according to the register The number of channels in and the current data communication rate send the uplink data to the subsequent circuit of the BBIC;

When the data communication type is downlink data communication, the data and timing processing module receives the downlink data transmitted by the subsequent circuit of the BBIC according to the interface timing corresponding to the downlink data communication, and the data and timing processing module according to the register configuration module The number of channels and the current data communication rate send the downlink data to the interface timing control module.

Embodiments of the present invention provide a parallel interface timing control method and device, the method is used in a parallel interface timing control device, and the parallel interface timing control device includes: a register configuration module, a rate adaptive module, an interface timing control module and A data and timing processing module, the method includes: the register configuration module acquires system configuration information; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module The cycle information of the MCLK sent by the opposite end generates an updated data communication rate and an adaptive sign, and sends the updated data communication rate and the adaptive sign to the register configuration module; the register configuration module is based on the adaptive sign Configure the current data communication rate; the interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, according to the The register configures the current data communication rate of the module to process data, so as to realize the self-adaptive configuration of the parallel interface rate.

Description of drawings

Fig. 1 is the JESD207 data interface connection figure that the embodiment of the present invention provides;

FIG. 2 is a schematic diagram of communication interaction between a parallel interface timing control device and a radio frequency front-end integrated circuit provided by an embodiment of the present invention;

Fig. 3 is the JESD207 data transmission start sequence diagram that the embodiment of the present invention provides;

Fig. 4 is the JESD207 data sending end sequence diagram provided by the embodiment of the present invention;

Fig. 5 is the JESD207 data receiving start sequence diagram that the embodiment of the present invention provides;

FIG. 6 is a sequence diagram of the end of JESD207 data reception provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a parallel interface timing control circuit provided by an embodiment of the present invention;

FIG. 8 is a structural block diagram of a parallel interface timing control device provided by an embodiment of the present invention;

FIG. 9 is a structural block diagram of a rate adaptation module provided by an embodiment of the present invention;

FIG. 10 is a flow chart of a parallel interface timing control method provided by an embodiment of the present invention;

Fig. 11 is a flow chart of generating an updated data communication rate by an adaptive module provided by an embodiment of the present invention;

FIG. 12 is a flow chart of data processing by a data and timing processing module provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the invention with reference to the drawings in the embodiments of the invention.

Referring to Fig. 2, it shows a schematic diagram of communication interaction between a parallel interface timing control device and RFIC provided by an embodiment of the present invention. The embodiment of the invention makes any specific limitations. It can be seen from the figure that the parallel interface timing control device is located on the BBIC side, and the parallel interface timing control device corresponds to the RBDP-related circuit in the BBIC in FIG. 1 .

Figure 3 and Figure 4 show the timing of JESD207's data transmission operation, and Figure 5 and Figure 6 show the timing of JESD207's data receiving operation. From the above timing diagram, it can be seen that the reception or transmission of JESD207 interface data uses a pair of ENABLE signals as an indication of the start and end, and the TXNRX signal indicates the direction of data transmission. High level indicates transmission, and low level indicates low reception. For sending data, RFIC uses FCLK for sampling, and for receiving data, BBIC uses MCLK for sampling.

Based on the above schematic diagram, an embodiment of the present invention provides a parallel interface timing control method. The parallel interface timing control method is used in a parallel interface timing control device. FIG. 7 is a specific structural schematic diagram of a parallel interface timing control circuit. The present invention The basic idea of the embodiment is: the register configuration module obtains the configuration information of the system; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module sends The cycle information of the MCLK generates the updated data communication rate and the adaptive sign, and sends the updated data communication rate and the adaptive sign to the register configuration module; the register configuration module configures the current data according to the adaptive sign Communication rate; the interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, and according to the current configuration of the register configuration module Process data at the data communication rate, thereby realizing the adaptive configuration of the parallel interface rate.

Embodiment one

Referring to FIG. 8 , it shows the structure of a parallel interface timing control device 80 provided by an embodiment of the present invention. The parallel interface timing control device 80 includes: a register configuration module 801, a rate adaptation module 802, and an interface timing control module. 803 and data and timing processing module 804, wherein,

The register configuration module 801 is configured to acquire system configuration information;

The rate adaptation module 802 is configured to generate an updated data communication rate and an adaptive flag through the period information of the MCLK sent by the opposite end when detecting that the first configuration information in the register configuration module is valid, and set the The updated data communication rate and adaptive flag are sent to the register configuration module;

The register configuration module 801 is also configured to configure the current data communication rate according to the adaptive flag;

The interface timing control module 803 is configured to generate interface timing according to the second configuration information and MCLK information in the register configuration module;

The data and timing processing module 804 is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.

For the register configuration module 801, the configuration information includes: interface module enablement, number of channels, default data communication rate, TDD mode subframe type, adaptive function enabling, adaptive success detection times, adaptive failure detection times ;

Wherein, enabling the adaptive function corresponds to the first configuration information, and the validity of the first configuration information specifically refers to enabling the adaptive function in the register configuration module to be valid, for example: the adaptive function is enabled when the high level is valid; TDD mode subframe The type corresponds to the second configuration information.

For the rate adaptation module 802, the period information of the MCLK sent by the peer specifically refers to the period information of the MCLK sent by the RFIC;

The adaptive flags include: an adaptive success flag and an adaptive failure flag.

The block diagram of the rate adaptation module 802 is shown in Figure 9, the rate adaptation module 802 includes: MCLK period detection sub-module 8021, MCLK clock stability detection sub-module 8022, rate adaptation failure detection sub-module 8023 and Rate adaptive information update sub-module 8024;

For the rate adaptation module detection 802, wherein,

The MCLK cycle detection sub-module 8021 is used to obtain the cycle information of the MCLK through the working clock, and send the cycle information of the MCLK to the MCLK clock stability detection sub-module 8022 and the rate adaptive information update sub-module 8024 in real time; The working clock is not less than 2 times the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;

The MCLK clock stability detection sub-module 8022 is used to trigger the rate self-adaptation information update sub-module 8024 to generate an updated data communication rate when detecting that the cycle information of two consecutive MCLKs meets the preset adaptive success value. Send to the register configuration module 801;

And, it is used to trigger the rate adaptation information update submodule 8024 to turn off the adaptation function when detecting that the number of times of inconsistency of the cycle information of two consecutive MCLKs meets the adaptive failure value; wherein,

The MCLK clock stability detection submodule 8022 is specifically used for,

When the period information of two consecutive MCLKs is detected to be consistent, the internal clock stabilization counter performs an accumulation count to obtain a first accumulation count value;

And, when the first accumulated count value reaches a pre-configured adaptive success value, generate a rate adaptive success flag;

And, send the rate adaptation success flag to the rate adaptation information update submodule 8024 and the register configuration module 801 .

The rate adaptation information update sub-module 8024 is used to convert the period information of MCLK into a data communication rate when the rate adaptation success flag is detected;

And, send the data communication rate converted from the period information of MCLK to the register configuration module 801 as an updated data communication rate.

It should be noted that when it is detected that the period information of two consecutive MCLKs is consistent, the above-mentioned MCLK clock stability detection submodule 8022 and the rate adaptation information update submodule 8024 are used to generate an updated data communication rate and send it to the The specific process of the register configuration module 801.

The MCLK clock stability detection sub-module 8022 is also used to trigger the rate self-adaptation information update sub-module 8024 to turn off the self-adaptation function when detecting that the cycle information inconsistencies of two consecutive MCLKs meet the self-adaptation failure value;

The MCLK clock stability detection sub-module 8022 is also specifically used for,

When the cycle information of two consecutive MCLKs is detected to be inconsistent, the internal clock stabilization counter executes a cumulative counting reset to generate an MCLK change flag;

And, send the MCLK change flag to the rate adaptation failure detection submodule 8023 .

The rate adaptive failure detection sub-module 8023 is used to detect the MCLK change flag, and its internal clock change counter performs an accumulative counting operation to obtain a second accumulative count value;

And, when the second accumulated count value reaches a pre-configured adaptive failure value, generating a rate adaptive failure flag;

And, send the rate adaptation failure flag to the rate adaptation information update submodule 8024 and the register configuration module 801 .

The rate adaptation information update sub-module 8024 is also configured to disable the rate adaptation function when a rate adaptation failure flag is detected.

It should be noted that when the period information of two consecutive MCLKs is detected to be inconsistent, the above-mentioned MCLK clock stability detection submodule 8022, the rate adaptation failure detection submodule 8023 and the rate adaptation information update submodule 8024 are used to realize the automatic shutdown The specific process of adaptation function.

The register configuration module 801 is also specifically configured to:

Configure the current data communication rate as the updated data communication rate according to the adaptive success flag;

Configuring the current data communication rate according to the self-adaptation failure flag is configured as a default data communication rate sent by the system to the register configuration module.

For the interface timing control module 803, the communication type includes: uplink communication and downlink communication;

The interface timing specifically refers to the interface timing that meets the requirements of the JESD207 protocol;

Further, the interface timing control module 803 is specifically used to:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, it is used to generate an interface sequence corresponding to uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, it is used to generate the interface timing corresponding to the downlink data communication, and generate the same FCLK timing as the MCLK timing according to the MCLK information delay .

The data and timing processing module 804 is specifically used to:

When the data communication type is uplink data communication, the uplink data transmitted by the interface timing control module 803 is received according to the interface timing corresponding to the uplink data communication, and the uplink data transmitted by the interface timing control module 803 is received according to the number of channels in the register configuration module 801 and the current data communication rate. The above-mentioned uplink data is sent to the post-stage circuit of BBIC;

Specifically, the data sent by the interface timing control module 803 to the data and timing processing module 804 specifically refers to that the interface timing control module 803 receives the corresponding TXNRX, ENABLE timing signals, and MCLK timing signals from the peer through DIQ according to the uplink data communication. The data of the DDR sent by the interface, the interface timing control module 803 converts the data of the DDR into data of a single data rate (SDR, Single Data Rate) and sends it to the data and timing processing module 804 for data processing, and the data The timing processing module 804 finally sends the processed SDR data to the subsequent circuit of the BBIC according to the uplink data communication corresponding to the TXNRX, ENABLE timing signals and the MCLK timing;

And, when the data communication type is downlink data communication, receive the downlink data transmitted by the subsequent circuit of the BBIC according to the interface timing corresponding to the downlink data communication, and set the channel number and the current data communication rate according to the number of channels in the register configuration module 801 The downlink data is sent to the interface timing control module 803;

Specifically, the data sent by the post-stage circuit of the BBIC to the data and timing processing module 804 is SDR data, which specifically refers to that the post-stage circuit of the BBIC sends the corresponding TXNRX, ENABLE timing signals and MCLK timing according to the downlink data communication. The SDR data is sent to the data and timing processing module 804, and the data of the SDR processed by the data and timing processing module 804 is finally converted into DDR data through the interface timing control module 803, and the data of the DDR is determined by the The interface timing control module 803 sends the TXNRX, ENABLE timing signals and FCLK corresponding to the downlink data communication to the opposite end through the DIQ interface.

In addition, this embodiment also aims at the problem of frequent update of data communication rate information caused by frequent jitter of MCLK, adopting the rate adaptation module 802 to generate a rate adaptation failure flag to disable the rate adaptation function; specifically, when the MCLK clock stability detection submodule When 8022 detects that the frequency of MCLK frequent jitter meets the pre-configured number of rate adaptive jitter off, a rate adaptive failure flag is generated and sent to the register configuration module 801 and the rate adaptive information update submodule 8024, and the rate adaptive information update The sub-module 8024 disables the rate adaptation function after detecting the rate adaptation failure flag.

This embodiment provides a parallel interface timing control device, the register configuration module 801 is used to acquire system configuration information, and the rate adaptation module 802 is used to detect the first configuration in the register configuration module When the information is valid, an updated data communication rate and an adaptive sign are generated through the period information of the MCLK sent by the opposite end, and the updated data communication rate and the adaptive sign are sent to the register configuration module, the register configuration module 801, It is used to configure the current data communication rate according to the adaptive flag, and the interface timing control module 803 is used to generate interface timing according to the second configuration information and MCLK information in the register configuration module, and the data and timing processing Module 804, configured to transmit data according to the interface timing, and process data according to the current data communication rate of the register configuration module, so as to realize adaptive configuration of parallel interface rate.

Embodiment two

Referring to FIG. 10 , it shows a parallel interface timing control method provided by an embodiment of the present invention, the method is used in a parallel interface timing control device, and the parallel interface timing control device includes: a register configuration module, a rate adaptive module, interface timing control module and data and timing processing module, the method includes:

S1001: The register configuration module acquires system configuration information;

S1002: When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptation flag through the cycle information of MCLK sent by the opposite end, and sending the updated data communication rate and adaptive flag to the register configuration module;

S1003: The register configuration module configures the current data communication rate according to the adaptive flag;

S1004: The interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module;

S1005: The data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.

For step S1001, the configuration information includes: interface module enablement, channel number, default data communication rate, TDD mode subframe type, adaptive function enablement, number of times of successful self-adaptation detection, times of self-adaptation failure detection;

Wherein, enabling the adaptive function corresponds to the first configuration information, and the validity of the first configuration information specifically refers to enabling the adaptive function in the register configuration module to be valid, for example: the adaptive function is enabled when the high level is valid; TDD mode subframe The type corresponds to the second configuration information.

For step S1002, the rate adaptation module includes: an MCLK period detection submodule, an MCLK clock stability detection submodule, a rate adaptation failure detection submodule, and a rate adaptation information update submodule;

The period information of the MCLK sent by the opposite end specifically refers to the period information of the MCLK sent by the RFIC;

The adaptive flags include: an adaptive success flag and an adaptive failure flag.

For step S1002, FIG. 11 is a flow chart of generating an updated data communication rate for the adaptive module. When the rate adaptive module detects that the first configuration information in the register configuration module is valid, the rate adaptive module passes the The period information of the MCLK sent by the terminal generates an updated data communication rate and an adaptive sign, and sends the updated data communication rate and the adaptive sign to the register configuration module, specifically including:

S10021: The rate adaptation module obtains the period information of MCLK through the working clock; the working clock is not less than twice the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;

S10022: When the rate adaptation module detects that the cycle information of MCLK twice in a row matches the preset adaptive success value, perform steps S10023 to S10027; when the MCLK clock stability detection sub-module detects two consecutive When the number of cycle information inconsistencies of the second MCLK meets the self-adaptation failure value, execute step S10028 to step S100212;

S10023: The clock stabilization counter inside the rate adaptation module performs an accumulation count, and the rate adaptation module obtains a first accumulation count value;

S10024: When the first accumulated count value reaches the adaptive success value preconfigured by the rate adaptive module, the rate adaptive module generates a rate adaptive success flag;

S10025: The rate adaptation module sends the rate adaptation success flag to the register configuration module;

S10026: When the rate adaptation module detects a rate adaptation success flag, the rate adaptation module converts the period information of MCLK into a data communication rate;

S10027: The rate adaptation module sends the data communication rate converted from the period information of MCLK to the register configuration module as an updated data communication rate;

It should be noted that steps S10023 to S10027 are aimed at generating an updated data communication rate and sending it to the The specific implementation process of the register configuration module.

S10028: The clock stabilization counter inside the rate adaptation module clears the accumulative count once, and the rate adaptation module generates an MCLK change flag;

S10029: When the rate adaptation module detects the MCLK change flag, the clock change counter in the rate adaptation module performs an accumulative counting operation, and the rate adaptation module obtains a second accumulative count value;

S100210: When the second accumulated count value reaches the adaptive failure value preconfigured by the rate adaptive module, the rate adaptive module generates a rate adaptive failure flag;

S100211: The rate adaptation module sends the rate adaptation failure flag to the register configuration module;

S100212: When the rate adaptation module detects the rate adaptation failure flag, the rate adaptation module disables a rate adaptation function.

It should be noted that, step S10028 to step S100212 are specific implementation processes for disabling the adaptive function when the rate adaptive module detects that the number of times of inconsistency of cycle information of the MCLK twice in a row satisfies the adaptive failure value.

For step S1003, the register configuration module configures the current data communication rate according to the adaptive flag, specifically including:

The register configuration module configures the current data communication rate as the updated data communication rate according to the adaptive success flag;

The register configuration module configures the current data communication rate as the default data communication rate sent by the system to the register configuration module according to the self-adaptation failure flag.

For step S1004, the communication type includes: uplink communication and downlink communication;

The interface timing specifically refers to the interface timing that meets the requirements of the JESD207 protocol;

Further, the interface timing control module generates interface timing according to the second configuration information and MCLK information in the register configuration module, specifically including:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface timing control module generates an interface timing corresponding to uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface timing control module generates interface timing corresponding to downlink data communication, and the interface timing control module according to the MCLK information The delay generates the same FCLK timing as the MCLK timing.

For step S1005, the data includes uplink received data and downlink sent data;

For step S1005, FIG. 12 is a flow chart of data processing by the data and timing processing module. The data and timing processing module transmits data according to the interface timing, and processes according to the number of channels in the register configuration module and the current data communication rate. Data, specifically:

S10051: When the data communication type is uplink data communication, the data and timing processing module receives the uplink data transmitted by the interface timing control module according to the interface timing corresponding to the uplink data communication, and the data and timing processing module receives the uplink data according to the register The number of channels in the configuration module and the current data communication rate send the uplink data to the subsequent circuit of the BBIC;

S10052: When the data communication type is downlink data communication, the data and timing processing module receives the downlink data transmitted by the subsequent circuit of the BBIC according to the interface timing corresponding to the downlink data communication, and the data and timing processing module configures according to the register The number of channels in the module and the current data communication rate send the downlink data to the interface timing control module.

Specifically, for step S10051, specifically, the data sent by the interface timing control module to the data and timing processing module specifically refers to that the interface timing control module receives the corresponding TXNRX, ENABLE timing signal and MCLK timing according to the uplink data communication. The DDR data sent by the opposite end through the DIQ interface, the interface timing control module converts the DDR data into SDR data and sends it to the data and timing processing module for data processing, and the data and timing processing module finally follows the uplink data The communication corresponds to the TXNRX, ENABLE timing signal and the processed SDR data of the MCLK timing and sends it to the subsequent circuit of the BBIC;

Specifically, for step S10052, the data sent by the subsequent stage circuit of the BBIC to the data and timing processing module is SDR data, specifically referring to that the subsequent stage circuit of the BBIC corresponds to TXNRX, ENABLE timing signals and MCLK timing sends SDR data to the data and timing processing module, and the data of the SDR processed by the data and timing processing module is finally converted into DDR data through the interface timing control module, and the data of the DDR is determined by the DDR. The interface timing control module sends the corresponding TXNRX, ENABLE timing signals and FCLK to the opposite end through the DIQ interface according to the downlink data communication.

In addition, this embodiment also aims at the problem of frequent update of data communication rate information caused by frequent jitter of MCLK, and adopts the rate adaptive module to generate a rate adaptive failure flag to disable the rate adaptive function; specifically, when the MCLK clock stability detection sub-module detects the MCLK When the number of frequent jitters meets the pre-configured number of rate-adaptive jitters off, a rate-adaptive failure flag is generated and sent to the register configuration module and the rate-adaptive information update sub-module, and the rate-adaptive information update sub-module detects the rate-adaptive failure flag Then turn off the rate adaptation function.

This embodiment provides a timing control method for a parallel interface. The register configuration module acquires configuration information of the system. When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate automatically Adaptation module generates updated data communication rate and self-adaptation sign by the period information of MCLK sent by opposite end, and sends the data communication rate and self-adaptation sign of described update to register configuration module, and described register configuration module is according to described self-adaptation The adaptation flag configures the current data communication rate, the interface timing control module selects the communication type and the timing signal required by the communication type according to the second configuration information in the register configuration module, and the data and timing processing module selects the communication type according to the interface The data is transmitted in time sequence, and the data is processed according to the current data communication rate of the register configuration module, so as to realize the self-adaptive configuration of the parallel interface rate.

Those skilled in the art should understand that the embodiments of the present invention may provide methods, systems, or computer program products. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each flow and/or block in the program diagram and/or block diagram, and the flow and/or combinations in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, yes, generated by the instructions executed by the processor of the computer or other programmable data processing device Means for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in computer readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computing and readable memory produce an article of manufacture comprising instruction means. The instruction means implements the functions specified in one or more procedures in the flowchart and/or one or more blocks in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable processing equipment, so that the instructions executed on the computer or other programmable equipment are used to implement a process or multiple processes in the flowchart and/or a block in the block diagram or Steps for functions specified in multiple boxes.

The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (18)

1. A parallel interface timing control apparatus, comprising: a register configuration module, a rate self-adapting module, an interface time sequence control module and a data and time sequence processing module, wherein,

the register configuration module is used for acquiring configuration information of the system;

the rate self-adapting module is used for generating an updated data communication rate and a self-adapting mark through the period information of the MCLK sent by the opposite terminal when the first configuration information in the register configuration module is detected to be effective, and sending the updated data communication rate and the self-adapting mark to the register configuration module;

the register configuration module is further configured to configure the current data communication rate according to the adaptive flag;

the interface time sequence control module is used for generating an interface time sequence according to the second configuration information and the MCLK information in the register configuration module;

and the data and time sequence processing module is used for transmitting data according to the interface time sequence and processing the data according to the number of channels in the register configuration module and the current data communication rate.

2. The apparatus of claim 1, wherein the configuration information comprises: enabling an interface module, the number of channels, the default data communication rate, the TDD mode subframe type, enabling an adaptive function, the adaptive successful detection times and the adaptive failure detection times; the adaptive function enables corresponding to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.

3. The apparatus of claim 1, wherein the adaptive flag comprises: an adaptation success flag and an adaptation failure flag.

4. The apparatus of claim 1, wherein the rate adaptation module comprises: the system comprises an MCLK period detection submodule, an MCLK clock stability detection submodule, a rate self-adaptive failure detection submodule and a rate self-adaptive information updating submodule; wherein,

the MCLK period detection submodule is used for acquiring MCLK period information through a working clock and sending the MCLK period information to the MCLK clock stability detection submodule and the rate self-adaption information updating submodule in real time;

the MCLK clock stability detection submodule is used for triggering the rate self-adaption information updating submodule to generate an updated data communication rate when the number of times of detecting the consistency of the MCLK period information which is continuously detected twice meets a preset self-adaption success value, and sending the updated data communication rate to the register configuration module;

the MCLK clock stability detection submodule is further used for triggering the rate self-adaption information updating submodule to close the self-adaption function when the number of times of inconsistency of the MCLK period information detected for two consecutive times meets a self-adaption failure value.

5. The apparatus of claim 4, wherein the MCLK clock stability detection submodule, in particular to,

when the period information of the MCLK which is continuously detected twice is consistent, an internal clock stability counter executes one-time accumulation counting to obtain a first accumulation counting value;

and generating a rate adaptation success flag when said first accumulated count value reaches a preconfigured adaptation success value;

sending the rate self-adaption success mark to the rate self-adaption information updating submodule and the register configuration module;

the rate self-adaptive information updating submodule is used for converting the period information of the MCLK into the data communication rate when the rate self-adaptive success mark is detected;

and sending the data communication rate converted by the period information of the MCLK to the register configuration module as an updated data communication rate.

6. The apparatus of claim 4, wherein the MCLK clock stability detection submodule is further configured to,

when the period information of the MCLK which is continuously carried out twice is detected to be inconsistent, an internal clock stability counter executes one-time accumulated counting zero clearing to generate an MCLK change mark;

and sending the MCLK change mark to the rate adaptive failure detection submodule;

the rate self-adaptive failure detection submodule is used for carrying out one-time accumulated counting operation on a clock change counter inside the rate self-adaptive failure detection submodule when the MCLK change mark is detected to obtain a second accumulated counting value;

and generating a rate adaptation failure flag when said second accumulated count value reaches a preconfigured adaptation failure value;

sending the rate self-adaption failure mark to the rate self-adaption information updating submodule and the register configuration module;

and the rate adaptation information updating submodule is also used for closing the rate adaptation function when the rate adaptation failure mark is detected.

7. The apparatus of claim 1, wherein the register configuration module is further configured to,

configuring the current data communication rate as the updated data communication rate according to the self-adaptive success flag;

and configuring the current data communication rate according to the self-adaptive failure flag to configure the default data communication rate sent to the register configuration module by the system.

8. The apparatus according to claim 1, wherein the interface timing control module is specifically configured to,

when the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, generating an interface time sequence corresponding to the uplink data communication;

and when the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the register configuration module is used for generating an interface time sequence corresponding to the downlink data communication and generating an FCLK time sequence which is the same as the MCLK time sequence according to the MCLK information delay.

9. The apparatus according to claim 1, wherein the data and timing processing module is specifically configured to,

when the data communication type is uplink data communication, receiving uplink data transmitted by the interface time sequence control module according to an interface time sequence corresponding to the uplink data communication, and sending the uplink data to a rear-stage circuit of the BBIC according to the number of channels in the register configuration module and the current data communication rate;

and when the data communication type is downlink data communication, receiving downlink data transmitted by a rear-stage circuit of the BBIC according to an interface time sequence corresponding to the downlink data communication, and sending the downlink data to the interface time sequence control module according to the number of channels in the register configuration module and the current data communication rate.

10. A parallel interface timing control method is used for a parallel interface timing control device, and the parallel interface timing control device comprises: the method comprises a register configuration module, a rate self-adaption module, an interface time sequence control module and a data and time sequence processing module, and comprises the following steps:

the register configuration module acquires configuration information of a system;

when the rate self-adaptive module detects that the first configuration information in the register configuration module is valid, the rate self-adaptive module generates an updated data communication rate and a self-adaptive flag through the period information of the MCLK sent by the opposite terminal, and sends the updated data communication rate and the updated self-adaptive flag to the register configuration module;

the register configuration module configures the current data communication rate according to the self-adaptive flag;

the interface time sequence control module generates an interface time sequence according to the second configuration information and the MCLK information in the register configuration module;

and the data and time sequence processing module transmits data according to the interface time sequence and processes the data according to the number of channels in the register configuration module and the current data communication rate.

11. The method of claim 10, wherein the configuration information comprises: the method comprises the following steps of enabling an interface module, the number of channels, the default data communication rate, the type of a Time Division Duplex (TDD) mode subframe, enabling a self-adaptive function, the self-adaptive successful detection times and the self-adaptive failure detection times; the adaptive function enables corresponding to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.

12. The method of claim 10, wherein the adaptive flag comprises: an adaptation success flag and an adaptation failure flag.

13. The method according to claim 10, wherein when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptation flag according to the period information of the MCLK sent from the opposite end, and sends the updated data communication rate and the adaptation flag to the register configuration module, specifically comprising:

the rate self-adaptive module acquires the period information of the MCLK through a working clock;

when the rate adaptation module detects that the number of times of the period information consistency of the MCLK which is continuously carried out twice meets a preset adaptive success value, generating an updated data communication rate, and sending the updated data communication rate to the register configuration module;

and when the rate self-adaptive module detects that the inconsistent times of the period information of the MCLK which is continuously carried out twice meet the self-adaptive failure value, closing the self-adaptive function.

14. The method according to claim 13, wherein the generating an updated data communication rate when the rate adaptation module detects that the number of times of the period information coincidence of the MCLK which is performed twice consecutively meets a preset adaptation success value and sending the updated data communication rate to the register configuration module specifically comprises:

when the rate self-adaptive module detects that the period information of MCLK which is continuously carried out twice is consistent, a clock stabilization counter inside the rate self-adaptive module carries out accumulation counting once, and the rate self-adaptive module obtains a first accumulation counting value;

when the first accumulated count value reaches a pre-configured adaptation success value of the rate adaptation module, the rate adaptation module generates a rate adaptation success flag;

when the rate adaptation module detects the rate adaptation success flag, the rate adaptation module converts the period information of the MCLK into a data communication rate;

and the rate self-adapting module sends the data communication rate converted by the period information of the MCLK to the register configuration module as an updated data communication rate.

15. The method according to claim 13, wherein when the number of times that the MCLK clock stability detection submodule detects that the period information of the two consecutive MCLK is inconsistent satisfies the adaptive failure value, the method triggers the rate adaptive information update submodule to turn off the adaptive function, specifically comprising:

when the rate self-adaptive module detects that the period information of MCLK which is continuous twice is inconsistent, a clock stabilization counter inside the rate self-adaptive module carries out one-time accumulated counting and clearing, and the rate self-adaptive module generates an MCLK change mark;

when the rate self-adaptive module detects the MCLK change mark, a clock change counter in the rate self-adaptive module carries out one-time accumulation counting operation, and the rate self-adaptive module obtains a second accumulation count value;

when the second accumulated count value reaches a pre-configured adaptive failure value of the rate adaptation module, the rate adaptation module generates a rate adaptation failure flag;

the rate adaptation module sends the rate adaptation failure flag to the register configuration module;

the rate adaptation module turns off the rate adaptation function when the rate adaptation module detects the rate adaptation failure flag.

16. The method according to claim 10, wherein the configuring the current data communication rate by the register configuration module according to the adaptive flag specifically comprises:

the register configuration module configures the current data communication rate as the updated data communication rate according to the adaptive success flag;

and the register configuration module configures the current data communication rate into the default data communication rate which is sent to the register configuration module by the system according to the self-adaptive failure flag.

17. The method of claim 10, wherein the interface timing control module generates the interface timing according to the second configuration information and the MCLK information in the register configuration module, and specifically includes:

when the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface time sequence control module generates an interface time sequence corresponding to the uplink data communication;

when the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface time sequence control module generates an interface time sequence corresponding to the downlink data communication, and the interface time sequence control module generates an FCLK time sequence which is the same as the MCLK time sequence according to the MCLK information delay.

18. The method of claim 10, wherein the data and timing processing module transmits data according to the interface timing and processes data according to the number of channels in the register configuration module and a current data communication rate, and specifically comprises:

when the data communication type is uplink data communication, the data and time sequence processing module receives uplink data transmitted by the interface time sequence control module according to an interface time sequence corresponding to the uplink data communication, and the data and time sequence processing module sends the uplink data to a rear-stage circuit of the BBIC according to the number of channels in the register configuration module and the current data communication rate;

and when the data communication type is downlink data communication, the data and time sequence processing module receives downlink data transmitted by a rear-stage circuit of the BBIC according to an interface time sequence corresponding to the downlink data communication, and the data and time sequence processing module sends the downlink data to the interface time sequence control module according to the number of channels in the register configuration module and the current data communication rate.