CN108011620B - Fast clock recovery circuit based on FPGA - Google Patents
Fast clock recovery circuit based on FPGA Download PDFInfo
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- CN108011620B CN108011620B CN201610931405.6A CN201610931405A CN108011620B CN 108011620 B CN108011620 B CN 108011620B CN 201610931405 A CN201610931405 A CN 201610931405A CN 108011620 B CN108011620 B CN 108011620B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a fast clock recovery circuit based on an FPGA. The FPGA-based fast clock recovery circuit generates a plurality of reference clock signals with the same frequency and different phases with the input data, judges the phase relation between the input data and the feedback clock signals, quantifies the phase difference between the input data and the feedback clock signals, and selects and outputs a reference clock signal with the phase closest to the input data as a recovered clock signal according to the phase relation between the input data and the feedback clock signals and the phase difference. The invention can rapidly complete the synchronization of the clock signal and the input data, and the clock recovery process generates less burrs.
Description
Technical Field
The invention relates to the technical field of clock recovery, in particular to a fast clock recovery circuit based on an FPGA.
Background
With the continuous development of serial communication technology, the amount of serial data in a network is continuously increased, however, clock jitter is inevitably generated in the data transmission process, and the jitter brings about deviation to data transmission, so that clock recovery is necessary, and then the clock recovery is used for data re-timing. With the continuous development of integrated circuits, the clock recovery realized by using the FPGA (Field Programmable Gate Array ) can avoid using additional hardware circuits, reduce circuit area, improve integration level, and greatly shorten design period and save design cost.
In the process of realizing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the existing clock recovery circuit based on the FPGA needs continuous clock switching to recover the clock signal, so that the clock with the phase closest to that of the input data is finally output as the recovered clock, the time required for clock recovery is long, and the clock signal is more in burrs due to the fact that the output clock signal needs to be switched for many times.
Disclosure of Invention
The FPGA-based rapid clock recovery circuit provided by the invention can rapidly complete the synchronization of the clock signal and the input data, and less burrs are generated in the clock recovery process.
The invention provides a fast clock recovery circuit based on an FPGA, which comprises:
the clock generation module is used for generating a plurality of reference clock signals with the same frequency and different phases with the input data;
the phase judging module is used for receiving input data and a feedback clock signal, outputting two high-level signals reflecting the phase relation and the phase difference of the input data and the feedback clock signal, quantizing the width of the high-level signals, converting the width of the high-level signals into narrow pulses, counting the narrow pulses and outputting count values C1 and C2;
the clock adjustment module is used for receiving the count values C1 and C2 output by the phase discrimination module, selecting and outputting a clock signal from the reference clock signals generated by the clock generation module according to the magnitude relation of the count values C1 and C2, and outputting a high-level reset signal;
and the reset module is used for receiving the reset high level output by the clock adjustment module after the clock adjustment module completes one-time adjustment, converting the reset high level into a reset narrow pulse and resetting the count values C1 and C2 of the phase judgment module.
Optionally, the clock generating module includes:
the system clock circuit is used for receiving clock signals generated by the FPGA crystal oscillator, outputting one path of clock signals as clock input of the management clock circuit and one path of clock signals as clock input of the reset module;
the management clock circuit is used for receiving the clock signal output by the system clock circuit, outputting one path of clock signal as the input of the phase-locked loop circuit and one path of clock signal as the clock signal input by the phase discrimination module;
and the phase-locked loop circuit is used for receiving the clock signals output by the management clock circuit and outputting a plurality of reference clock signals with the same frequency and different phases with the input data.
Optionally, the phase difference between any adjacent two of all reference clock signals is the same, and the phase difference between all reference clock signals is at most 360 °.
Optionally, the phase discrimination module includes:
the Hogge linear phase discriminator circuit is used for receiving the input data and the feedback clock signal and outputting two high-level signals reflecting the phase relation and the phase difference of the input data and the feedback clock signal;
the pulse generation circuit is used for receiving the two high-level signals, respectively quantizing the widths of the high-level signals and converting the widths into narrow pulses;
and the pulse counting circuit is used for counting the narrow pulses generated by the pulse generating circuit and outputting count values C1 and C2.
Optionally, the phase discrimination module further includes: and the selector circuit is used for selecting the clock signal output by the management clock circuit when the clock signal is input to the phase discrimination module for the first time, and then selecting the feedback clock signal output by the clock adjustment module.
Optionally, when C1< C2, the phase of the reference clock signal leads the phase of the input data; when C1> C2, the phase of the reference clock signal lags the phase of the input data; when c1=c2, the input data is the same phase as the reference clock signal.
Optionally, when the feedback clock signal leads the input data, the clock adjustment module selects and outputs a reference clock signal lagging the feedback clock signal from all the reference clock signals generated by the clock generation module according to the value of C2-C1, wherein the reference clock signal is used as a new feedback clock signal and is used as an input of the phase discrimination module;
when the feedback clock signal lags the input data, the clock adjustment module selects and outputs a reference clock signal which leads the feedback clock signal from all the reference clock signals generated by the clock generation module according to the magnitude of the value of C1-C2, and the reference clock signal is used as a new feedback clock signal and is used as the input of the phase discrimination module, wherein the magnitude of the difference value between C1 and C2 reflects the magnitude of the phase difference between the input data and the feedback clock signal.
The FPGA-based fast clock recovery circuit provided by the embodiment of the invention generates a plurality of reference clock signals with the same frequency and different phases as input data, judges the phase relation between the input data and the feedback clock signals, quantifies the phase difference between the input data and the feedback clock signals, and selects and outputs a path of reference clock signal with the phase closest to the input data as a recovered clock signal according to the phase relation and the phase difference between the input data and the feedback clock signals. Compared with the prior art, the invention not only can judge the phase relation between the input data and the feedback clock signal, but also can obtain the phase difference between the input data and the feedback clock signal, thereby realizing the quick recovery of the clock signal and generating less burrs in the clock recovery process.
Drawings
FIG. 1 is a schematic diagram of an FPGA-based fast clock recovery circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a Hogge linear phase detector circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a pulse generating circuit according to an embodiment of the invention;
fig. 4 is a schematic circuit diagram of a reset module according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a fast clock recovery circuit based on an FPGA, as shown in figure 1, comprising:
a clock generation module 101 for generating a plurality of reference clock signals having the same frequency and different phases as the input data;
the phase discrimination module 102 is configured to receive input data and a feedback clock signal, output two high-level signals reflecting a phase relationship and a phase difference between the input data and the feedback clock signal, quantize a width of the high-level signals, convert the quantized width into a narrow pulse, count the narrow pulse, and output count values C1 and C2;
a clock adjustment module 103, configured to receive the count values C1 and C2 output by the phase discrimination module 102, select and output a clock signal from the reference clock signals generated by the clock generation module 101 according to the magnitude relation of the count values C1 and C2, and output a high-level reset signal;
the reset module 104 is configured to receive a reset high level rst_0 output by the clock adjustment module 103 after the clock adjustment module 103 completes one-time adjustment, convert the reset high level into a reset narrow pulse rst, and reset the count values C1 and C2 of the phase discrimination module 102.
The FPGA-based fast clock recovery circuit provided by the embodiment of the invention generates a plurality of reference clock signals with the same frequency and different phases as input data, judges the phase relation between the input data and the feedback clock signals, quantifies the phase difference between the input data and the feedback clock signals, and selects and outputs a path of reference clock signal with the phase closest to the input data as a recovered clock signal according to the phase relation and the phase difference between the input data and the feedback clock signals. Compared with the prior art, the invention not only can judge the phase relation between the input data and the feedback clock signal, but also can obtain the phase difference between the input data and the feedback clock signal, thereby realizing the quick recovery of the clock signal and generating less burrs in the clock recovery process.
Optionally, the clock generation module 101 includes:
the system clock circuit is used for receiving clock signals generated by the FPGA crystal oscillator, outputting one path of clock signals as clock input of the management clock circuit and one path of clock signals as clock input of the reset module 104;
the management clock circuit is used for receiving the clock signal output by the system clock circuit, outputting one path of clock signal as the input of the phase-locked loop circuit, and one path of clock signal as the clock signal input by the phase discrimination module 102;
and the phase-locked loop circuit is used for receiving the clock signals output by the management clock circuit and outputting a plurality of reference clock signals with the same frequency and different phases with the input data.
Optionally, the phase-locked loop circuit includes a first phase-locked loop circuit and a second phase-locked loop circuit, for respectively generating 6 reference clock signals with the same frequency and different phases as the input data.
Optionally, the phase difference between any adjacent two of all reference clock signals is the same, and the phase difference between all reference clock signals is at most 360 °.
Optionally, the phase discrimination module 102 includes:
a Hogge linear phase discriminator circuit 301, configured to receive the input data and the feedback clock signal, and output two high-level signals reflecting the phase relationship and the phase difference between the input data and the feedback clock signal;
a pulse generating circuit 302, configured to receive the two high-level signals, respectively quantize the widths of the high-level signals, and convert the quantized widths into narrow pulses;
the pulse counting circuit 303 counts the narrow pulses generated by the pulse generating circuit, and outputs count values C1 and C2.
Optionally, the phase discrimination module 102 further includes:
a selector circuit 304, configured to select the clock signal output by the management clock circuit when the clock signal is input to the phase discrimination module 102 for the first time, and then select the feedback clock signal output by the clock adjustment module 103.
Optionally, as shown in fig. 2, the Hogge linear phase detector 301 receives the input data datain and the feedback clock signal recclk output by the clock adjustment module 103, and outputs two high levels datacq and clkcq.
Optionally, the width of the high level clkcq is constant throughout and exactly equal to half the feedback clock signal refclk clock period; when the feedback clock signal refclk phase advances from the input data datain, the width of the high level dataq will be smaller than the width of the high level clkcq; when the feedback clock signal refclk is phase-lagged to the input data, the datacq width will be greater than the clkcq width; when the refclk clock rising edge is just aligned in the middle of the datain high, then the locked state is reached, where the width of the high datacq will be equal to the width of the high clkcq.
Thus, by comparing the widths of the two high levels datacq and clkcq, the phase relationship of the input data datain and the feedback clock signal refclk can be judged, and the larger the widths of the two high levels datacq and clkcq differ, the larger the phase difference of the input data datain and the feedback clock signal refclk.
Optionally, as shown in fig. 3, the pulse generating circuit 302 generates the number of narrow pulses in proportion to the length of the high level shuru when the input clock signal dclk is constant; when the length of the high level shuu is fixed, the higher the frequency of the input clock signal dclk is, the more pulses are generated by the same high level, and the higher the phase accuracy of the recovered clock signal is.
Optionally, the frequency of the input clock signal dclk is a limit frequency that can be tolerated by the FPGA.
Optionally, when C1< C2, the phase of the reference clock signal leads the phase of the input data; when C1> C2, the phase of the reference clock signal lags the phase of the input data; when c1=c2, the input data is the same phase as the reference clock signal.
Optionally, when the feedback clock signal leads the input data, the clock adjustment module 103 selects and outputs a reference clock signal lagging the feedback clock signal from all the reference clock signals generated by the clock generation module 101 according to the magnitude of the value of C2-C1, wherein the reference clock signal is used as a new feedback clock signal and is used as an input of the phase discrimination module 102;
when the feedback clock signal lags the input data, the clock adjustment module 103 selects and outputs a reference clock signal that leads the feedback clock signal from all the reference clock signals generated by the clock generation module 101 according to the magnitude of the value of C1-C2, and the reference clock signal is used as a new feedback clock signal and is used as an input of the phase discrimination module 102, wherein the magnitude of the difference between C1 and C2 reflects the magnitude of the phase difference between the input data and the feedback clock signal.
Alternatively, since the width of the reset high level rst_0 output by the clock adjustment module 103 is larger, which may affect the count of the next round, the reset module 104 converts the reset high level rst_0 into the reset narrow pulse rst, and resets the count value.
Optionally, as shown in fig. 4, the circuit structure of the reset module 104 converts the reset high level rst_0 into the input clock signal of the reset narrow pulse rst, dclk; the frequency of the input clock signal dclk is the limit frequency which can be born by the FPGA.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (6)
1. A fast FPGA-based clock recovery circuit comprising:
the clock generation module is used for generating a plurality of reference clock signals with the same frequency and different phases with the input data; the clock generation module includes: the system clock circuit is used for receiving clock signals generated by the FPGA crystal oscillator, outputting one path of clock signals as clock input of the management clock circuit and one path of clock signals as clock input of the reset module; the management clock circuit is used for receiving the clock signals output by the system clock circuit, outputting one path of clock signals as the input of the phase-locked loop circuit and one path of clock signals as the clock signals input by the phase discrimination module; the phase-locked loop circuit is used for receiving the clock signals output by the management clock circuit and outputting a plurality of reference clock signals with the same frequency and different phases with the input data;
the phase judging module is used for receiving input data and a feedback clock signal, outputting two high-level signals reflecting the phase relation and the phase difference of the input data and the feedback clock signal, quantizing the width of the high-level signals, converting the width of the high-level signals into narrow pulses, counting the narrow pulses and outputting count values C1 and C2;
the clock adjustment module is used for receiving the count values C1 and C2 output by the phase discrimination module, selecting and outputting a clock signal from the reference clock signals generated by the clock generation module according to the magnitude relation of the count values C1 and C2, and outputting a high-level reset signal;
and the reset module is used for receiving the reset high level output by the clock adjustment module after the clock adjustment module completes one-time adjustment, converting the reset high level into a reset narrow pulse and resetting the count values C1 and C2 of the phase judgment module.
2. The FPGA-based fast clock recovery circuit of claim 1, wherein any adjacent two of the reference clock signals have the same phase difference and the phase difference of all reference clock signals is at most 360 °.
3. The FPGA-based fast clock recovery circuit of claim 1, wherein the phase discrimination module comprises:
the Hogge linear phase discriminator circuit is used for receiving the input data and the feedback clock signal and outputting two high-level signals reflecting the phase relation and the phase difference of the input data and the feedback clock signal;
the pulse generation circuit is used for receiving the two high-level signals, respectively quantizing the widths of the high-level signals and converting the widths into narrow pulses;
and the pulse counting circuit is used for counting the narrow pulses generated by the pulse generating circuit and outputting count values C1 and C2.
4. The FPGA-based fast clock recovery circuit of claim 3, wherein the phase discrimination module further comprises:
and the selector circuit is used for selecting the clock signal output by the management clock circuit when the clock signal is input to the phase discrimination module for the first time, and then selecting the feedback clock signal output by the clock adjustment module.
5. The FPGA-based fast clock recovery circuit of claim 3, wherein a phase of the reference clock signal leads a phase of the input data when C1< C2; when C1> C2, the phase of the reference clock signal lags the phase of the input data; when c1=c2, the input data is the same phase as the reference clock signal.
6. The FPGA-based fast clock recovery circuit according to claim 5, wherein when the feedback clock signal is ahead of the input data, the clock adjustment module selects and outputs a reference clock signal lagging the feedback clock signal from all reference clock signals generated by the clock generation module as a new feedback clock signal and as an input of the phase discrimination module according to the magnitude of the value of C2-C1;
when the feedback clock signal lags the input data, the clock adjustment module selects and outputs a reference clock signal which leads the feedback clock signal from all the reference clock signals generated by the clock generation module according to the magnitude of the value of C1-C2, and the reference clock signal is used as a new feedback clock signal and is used as the input of the phase discrimination module, wherein the magnitude of the difference value between C1 and C2 reflects the magnitude of the phase difference between the input data and the feedback clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610931405.6A CN108011620B (en) | 2016-10-31 | 2016-10-31 | Fast clock recovery circuit based on FPGA |
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| CN201610931405.6A CN108011620B (en) | 2016-10-31 | 2016-10-31 | Fast clock recovery circuit based on FPGA |
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| CN108011620B true CN108011620B (en) | 2023-08-08 |
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| WO2021102927A1 (en) * | 2019-11-29 | 2021-06-03 | 华为技术有限公司 | Clock generation circuit |
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