CN108010900A - A kind of HSIP14 encapsulating leads - Google Patents
A kind of HSIP14 encapsulating leads Download PDFInfo
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- CN108010900A CN108010900A CN201711387759.XA CN201711387759A CN108010900A CN 108010900 A CN108010900 A CN 108010900A CN 201711387759 A CN201711387759 A CN 201711387759A CN 108010900 A CN108010900 A CN 108010900A
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- chip
- base island
- voltage stabilizing
- stabilizing circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供了一种HSIP14封装引线框架，其封装与标准的HSIP14的封装完全相同，可以广泛使用，用一个芯片封装集成了多个芯片器件，在应用时减少了外部连线，提高了性能的稳定性，降低制造成本，包括框架，框架的中心位置设置有中心基岛，中心基岛上设有芯片DS4440，引脚一至引脚十四分布在中心基岛的四周，芯片DS4440上设有焊盘，焊盘与引脚二至引脚十三之间通过引线连接，框架上设有第二基岛和第三基岛，第二基岛和第三基岛上设有稳压电路芯片，一个稳压电路芯片通过引线连接引脚一和芯片DS4440，另一个稳压电路芯片通过引线连接引脚十四和芯片DS4440，两个稳压电路芯片之间通过引线连接。
The invention provides a HSIP14 package lead frame, the package of which is exactly the same as the package of the standard HSIP14, can be widely used, and integrates multiple chip devices with one chip package, which reduces external wiring and improves performance in application Stability, reduce manufacturing cost, including the frame, the center of the frame is provided with a center base island, the center base island is provided with a chip DS4440, pins 1 to 14 are distributed around the center base island, and the chip DS4440 is provided with a solder The pad is connected to the pins 2 to 13 by wires, the frame is provided with a second base island and a third base island, and the second base island and the third base island are provided with voltage stabilizing circuit chips. One voltage stabilizing circuit chip is connected to pin one and the chip DS4440 through a wire, the other voltage stabilizing circuit chip is connected to pin fourteen and the chip DS4440 through a wire, and the two voltage stabilizing circuit chips are connected through a wire.
Description
技术领域technical field
本发明涉及半导体封装的技术领域，具体为一种HSIP14封装引线框架。The invention relates to the technical field of semiconductor packaging, in particular to an HSIP14 packaging lead frame.
背景技术Background technique
标准的HSIP14封装型式的引线框架为单基岛，其基岛的中心位置放置有一个芯片，但是，伴随着产品的不断复杂化，在应用时为了功能的完善需要连接组合的附加元件，再通过外部引线连接，这样的设置使得性能稳定性差；且由于使用了多个封装器件，其使得产品的芯片封装体积大，且增加了成本，若重新设计封装引线框架则会涉及到设计、产线改造带来的成本问题。The lead frame of the standard HSIP14 package type is a single base island, and a chip is placed in the center of the base island. However, with the continuous complexity of the product, it is necessary to connect additional components in order to improve the function during application, and then through External lead connection, such a setting makes the performance stability poor; and due to the use of multiple packaged devices, it makes the chip package of the product bulky and increases the cost. If the package lead frame is redesigned, it will involve design and production line transformation cost issues.
发明内容Contents of the invention
针对上述问题，本发明提供了一种HSIP14封装引线框架，其封装与标准的HSIP14的封装完全相同，可以广泛使用，用一个芯片封装集成了多个芯片器件，在应用时减少了外部连线，提高了性能的稳定性，减少了器件的使用数量，降低制造成本，并适应了目前电子行业小型化、微型化的发展需求。In view of the above problems, the present invention provides a HSIP14 package lead frame, the package of which is exactly the same as the standard HSIP14 package, can be widely used, and integrates multiple chip devices with one chip package, reducing external wiring during application. The stability of performance is improved, the number of devices used is reduced, the manufacturing cost is reduced, and the current development needs of miniaturization and miniaturization of the electronic industry are adapted.
其技术方案是这样的：一种HSIP14封装引线框架，包括框架，所述框架的中心位置设置有中心基岛，所述中心基岛上设有芯片DS4440，引脚一至引脚十四分布在所述中心基岛的四周，所述芯片DS4440上设有焊盘，所述焊盘与引脚二至引脚十三之间通过引线连接，其特征在于：所述框架上设有第二基岛和第三基岛，所述第二基岛和所述第三基岛上分别设有稳压电路芯片，其中一个稳压电路芯片通过引线连接引脚一和所述芯片DS4440，另一个所述稳压电路芯片通过引线连接引脚十四和所述芯片DS4440，两个所述稳压电路芯片之间通过引线连接。The technical solution is as follows: a HSIP14 package lead frame includes a frame, a central base island is arranged at the center of the frame, and a chip DS4440 is arranged on the central base island, and pins 1 to 14 are distributed on the Around the central base island, the chip DS4440 is provided with pads, and the pads are connected to pins 2 to 13 by wires. It is characterized in that: the frame is provided with a second base island and the third base island, the second base island and the third base island are respectively provided with a voltage stabilizing circuit chip, wherein one of the voltage stabilizing circuit chips is connected to pin one and the chip DS4440 through a wire, and the other is the The voltage stabilizing circuit chip is connected to pin 14 and the chip DS4440 through wires, and the two voltage stabilizing circuit chips are connected through wires.
进一步的，所述第二基岛和所述第三基岛分别设置在引脚一和引脚十四上。Further, the second base island and the third base island are respectively arranged on pin one and pin fourteen.
进一步的，所述稳压电路芯片为7133芯片。Further, the voltage stabilizing circuit chip is a 7133 chip.
进一步的，所述稳压电路芯片为6206A33 芯片。Further, the voltage stabilizing circuit chip is a 6206A33 chip.
进一步的，所述稳压电路芯片为与所述芯片DS4440相匹配的三极管电路芯片。Further, the voltage stabilizing circuit chip is a triode circuit chip matching the chip DS4440.
进一步的，所述引线为金线。Further, the lead wires are gold wires.
进一步的，所述芯片DS4440和所述稳压电路芯片分装在塑封层中。Further, the chip DS4440 and the voltage stabilizing circuit chip are separately packaged in the plastic packaging layer.
本发明的HSIP14封装引线框架具有以下有点：在整体外型和外引脚间距不变的情况下，利用的原有的封装中空闲的引脚，将与芯片DS4440有关联的稳压电路芯片组合封装在一个塑封体内,节约了封装成本，实现电子系统的高性能和高可靠性，特别适合于汽车音响电子系统要求苛刻的场合；生产成本低、市场投放周期短，各功能模块可预先分别设计，并可大量采用市场现有的通用集成芯片和模块，有效地降低了成本、设计周期变短，投放市场较快；性能优良，可靠性高，该发明减少了各功能部件之间的连接，使得由于连接之间的各种损耗、干扰降低到最小，同时综合利用了微电子、固体电子等多项工艺技术，充分发挥了各种工艺的优势。从而提高了系统的综合性能。The HSIP14 package lead frame of the present invention has the following advantages: under the condition that the overall appearance and the pitch of the outer pins remain unchanged, the idle pins in the original package are used to combine the voltage stabilizing circuit chip associated with the chip DS4440 Encapsulated in a plastic package, which saves packaging costs and achieves high performance and high reliability of the electronic system, especially suitable for demanding occasions of car audio electronic systems; low production cost, short market launch cycle, and each functional module can be designed separately in advance , and a large number of existing general-purpose integrated chips and modules in the market can be used, which effectively reduces the cost, shortens the design cycle, and puts it on the market faster; it has excellent performance and high reliability, and the invention reduces the connection between various functional components. The various losses and interferences between the connections are minimized, and at the same time, multiple technologies such as microelectronics and solid-state electronics are comprehensively utilized to give full play to the advantages of various processes. Thereby improving the overall performance of the system.
附图说明Description of drawings
图1为本发明的HSIP14封装引线框架的示意图。FIG. 1 is a schematic diagram of the HSIP14 package lead frame of the present invention.
具体实施方式Detailed ways
见图1，本发明的一种HSIP14封装引线框架，包括框架1，框架1的中心位置设置有中心基岛2，中心基岛2上设有芯片3，其型号为DS4440，引脚一401、引脚二402、引脚三403至引脚十四414分布在中心基岛的四周，芯片3上设有焊盘4，焊盘4与引脚二402至引脚十三413之间通过引线5连接，框架1上设有第二基岛和第三基岛，第二基岛和第三基岛分别设置在引脚一401和引脚十四414上，第二基岛和第三基岛上分别设有稳压电路芯片61、62，其中一个稳压电路芯片61通过引线5连接引脚一401和芯片3，另一个稳压电路芯片62通过引线5连接引脚十四414和芯片3，两个稳压电路芯片61、62之间通过引线4连接，稳压电路芯片采用7133芯片、6206A33 芯片或与芯片DS4440相匹配的三极管电路芯片，在本实施例中引线为金线，芯片DS4440和稳压电路芯片分装在塑封层中。See Fig. 1, a kind of HSIP14 package lead frame of the present invention comprises frame 1, and the central position of frame 1 is provided with center base island 2, and center base island 2 is provided with chip 3, and its model is DS4440, and pin one 401, Pin 2 402 , pin 3 403 to pin 14 414 are distributed around the center base island, chip 3 is provided with pad 4 , pad 4 and pin 2 402 to pin 13 413 are connected by wires 5 connections, the frame 1 is provided with a second base island and a third base island, the second base island and the third base island are respectively set on pin one 401 and pin fourteen 414, the second base island and the third base island The island is respectively provided with voltage stabilizing circuit chips 61, 62, wherein one voltage stabilizing circuit chip 61 connects pin one 401 and chip 3 through lead wire 5, and the other voltage stabilizing circuit chip 62 connects pin fourteen 414 and chip through lead wire 5 3. The two voltage stabilizing circuit chips 61 and 62 are connected by wire 4. The voltage stabilizing circuit chip adopts a 7133 chip, a 6206A33 chip or a triode circuit chip matching the chip DS4440. In this embodiment, the lead wire is a gold wire, and the chip DS4440 and the voltage regulator circuit chip are packaged in the plastic packaging layer.
本发明的HSIP14封装引线框架，对原框架结构进行了改造，利用了原封装中空闲的引脚一和引脚十四，将原设计的一个基岛结构改为三个基岛，框架的整体长度和宽度不变，外引脚间距不变，在一个框架中封装多个芯片，节约了封装成本，实现电子系统的高性能和高可靠性，特别适合于电子系统要求苛刻的场合；生产成本低、市场投放周期短，各功能模块可预先分别设计，并可大量采用市场现有的通用集成芯片和模块，有效地降低了成本、设计周期变短，投放市场较快；性能优良，可靠性高，该发明减少了各功能部件之间的连接，使得由于连接之间的各种损耗、干扰降低到最小，同时综合利用了微电子、固体电子等多项工艺技术，充分发挥了各种工艺的优势。从而提高了系统的综合性能。The HSIP14 package lead frame of the present invention has transformed the original frame structure, utilized the idle pins 1 and 14 in the original package, and changed the originally designed one base island structure into three base islands. The length and width remain unchanged, and the pitch of the outer pins remains unchanged. Multiple chips are packaged in one frame, which saves packaging costs and achieves high performance and high reliability of the electronic system. It is especially suitable for occasions with demanding electronic systems; production costs Low cost, short market launch cycle, each functional module can be designed separately in advance, and a large number of existing general-purpose integrated chips and modules in the market can be used, which effectively reduces costs, shortens the design cycle, and puts the market faster; excellent performance, reliability High, the invention reduces the connection between the various functional components, so that the various losses and interference between the connections are reduced to the minimum, and at the same time, it comprehensively utilizes multiple technologies such as microelectronics and solid-state electronics, and fully utilizes various technologies. The advantages. Thereby improving the overall performance of the system.
以上，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人在本发明所揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any changes or substitutions that can be easily imagined by anyone familiar with the technology within the technical scope disclosed in the present invention are all Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711387759.XA CN108010900A (en) | 2017-12-20 | 2017-12-20 | A kind of HSIP14 encapsulating leads |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711387759.XA CN108010900A (en) | 2017-12-20 | 2017-12-20 | A kind of HSIP14 encapsulating leads |
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| CN108010900A true CN108010900A (en) | 2018-05-08 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202712172U (en) * | 2012-07-25 | 2013-01-30 | 深圳市气派科技有限公司 | Multi-chip dual-base island SOP package structure |
| CN103137594A (en) * | 2011-12-05 | 2013-06-05 | 正文电子(苏州)有限公司 | Novel semiconductor lead frame |
| CN203871320U (en) * | 2014-05-20 | 2014-10-08 | 安徽国晶微电子有限公司 | Packaging structure of AC-DC power supply circuit |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
| CN207719197U (en) * | 2017-12-20 | 2018-08-10 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
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2017
- 2017-12-20 CN CN201711387759.XA patent/CN108010900A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137594A (en) * | 2011-12-05 | 2013-06-05 | 正文电子(苏州)有限公司 | Novel semiconductor lead frame |
| CN202712172U (en) * | 2012-07-25 | 2013-01-30 | 深圳市气派科技有限公司 | Multi-chip dual-base island SOP package structure |
| CN203871320U (en) * | 2014-05-20 | 2014-10-08 | 安徽国晶微电子有限公司 | Packaging structure of AC-DC power supply circuit |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
| CN207719197U (en) * | 2017-12-20 | 2018-08-10 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
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Application publication date: 20180508 |