CN108010840B - Method for manufacturing doped semiconductor device and semiconductor device - Google Patents
Method for manufacturing doped semiconductor device and semiconductor device Download PDFInfo
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- CN108010840B CN108010840B CN201610947670.3A CN201610947670A CN108010840B CN 108010840 B CN108010840 B CN 108010840B CN 201610947670 A CN201610947670 A CN 201610947670A CN 108010840 B CN108010840 B CN 108010840B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000011241 protective layer Substances 0.000 claims abstract description 33
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 239000002994 raw material Substances 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 29
- 229910010271 silicon carbide Inorganic materials 0.000 description 29
- 238000001556 precipitation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a preparation method of a doped semiconductor device and the semiconductor device. The method according to the invention comprises the following steps: step one, after doping the semiconductor substrate, Si is formed on the surface of the semiconductor substrate3N4A protective layer; step two, carrying Si3N4And annealing the semiconductor substrate of the protective layer. According to the method of the invention, Si is used3N4As an annealing protection layer for semiconductor substrates. After annealing, Si may be annealed3N4The layer is used as an insulating layer of a semiconductor device, thereby eliminating the need for Si3N4The layers are completely removed, which simplifies the production steps.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a preparation method of a doped semiconductor. The invention also relates to a semiconductor device prepared by using the method.
Background
In the fabrication of some semiconductor devices, such as IGBTs, doping of the semiconductor substrate is required to form an N-type semiconductor or a P-type semiconductor. For example, ion implantation is performed on a SiC (silicon carbide) semiconductor substrate.
In particular, for SiC semiconductor substrates, the doping is substantially at the interstitial sites of the crystal lattice. In order to allow these doped ions to be displaced into lattice site locations, a high temperature activation anneal is required. For example, the annealing temperature of the N-type impurity is generally higher than 1400 ℃ to 1800 ℃, and the annealing temperature of the P-type impurity is generally 1600 ℃ to 1800 ℃. At such high annealing temperatures, Si in SiC may precipitate and redeposit, resulting in step clusters on the surface of the annealed wafer, deteriorating the surface topography of the wafer, and thus seriously affecting the performance of the semiconductor device.
In the prior art, a carbon film is generally formed on the wafer surface before annealing to suppress the precipitation of Si. However, after the annealing is finished, the carbon film needs to be removed. This results in a very complicated manufacturing method of the semiconductor device, and even incomplete removal of the carbon film may have a great adverse effect on the current distribution in the semiconductor device, which may further affect the performance stability of the semiconductor device, and even may cause damage to the semiconductor device.
Disclosure of Invention
In order to solve the problems, the invention provides a preparation method of a doped semiconductor device. According to the method of the invention, Si is used3N4As an annealing protection layer for semiconductor substrates. After annealing, Si may be annealed3N4The layer is used as an insulating layer of a semiconductor device, thereby eliminating the need for Si3N4The layers are completely removed, which simplifies the production steps. The invention also provides a semiconductor device prepared by using the method.
A method of manufacturing a doped semiconductor device according to the first aspect of the invention comprises the steps of: step one, after doping the semiconductor substrate, Si is formed on the surface of the semiconductor substrate3N4A protective layer; step two, carrying Si3N4And annealing the semiconductor substrate of the protective layer.
Due to Si3N4The material has a high hardness at high temperature, e.g. between 9 and 9.5 mohs hardness, and Si3N4The material will decompose at temperatures above 1900 ℃, which allows Si to be annealed during semiconductor substrate (e.g., SiC substrate) annealing3N4The protective layer can effectively prevent the precipitation of Si, so that the surface appearance of the semiconductor substrate is not damaged. More importantly, Si3N4The material has a resistivity of up to 1015 Ω · cm to 1016 Ω · cm. Thus, Si on the semiconductor substrate3N4The layer may also serve as an insulating layer in a subsequent step, thereby eliminating the need for Si3N4The layers are completely removed, which greatly simplifies the production steps of the semiconductor device.
In one embodiment, after step two, in Si3N4Etching a window region on the protective layer to expose the semiconductor substrate, Si at the window region and not etched away3N4And a metal electrode is arranged on the protective layer. By this step, Si not etched away3N4The protective layer actually forms an insulating layer between the metal electrode and the semiconductor substrate.
In one embodiment, in step one, Si3N4The thickness of the protective layer is between 200nm and 2000 nm. Si of such thickness3N4The protective layer is sufficient to prevent the precipitation of Si. In addition, Si of this thickness3N4The protective layer is particularly suitable for use as an insulating layer in a semiconductor device, thereby avoiding further processing of the Si in subsequent steps3N4And (3) a layer.
In one embodiment, the annealing temperature is between 1700 ℃ and 1800 ℃. In one embodiment, the semiconductor substrate is SiC. At 1700 to 1800 ℃ of Si3N4The material does not decompose and chemically react with SiC and impurity species doped within the semiconductor substrate, and therefore does not introduce contamination into the semiconductor substrate during annealing, which protects the semiconductor device.
In one embodiment, in step one, the Si is prepared using an LPCVD method or a PECVD method3N4And a protective layer. In the LPCVD method, the raw material used is N2And SiH4The temperature is 400 ℃ and 800 ℃, and the pressure is 0.1-3 torr. SiH4The flow rate of (2) is 30-70sccm, N2The flow rate of (2) is 40-90 sccm.
According to a second aspect of the present invention, a semiconductor device is proposed, which is made by the above-described method of manufacturing a doped semiconductor device. The semiconductor device comprises a semiconductor substrate, an active region and a junction termination region formed on the semiconductor substrate, and Si as an insulating layer formed on the surface of the junction termination region3N4Si on the surface of the layer, the active region and the junction termination region3N4A metal electrode is disposed on the layer.
In the semiconductor device, Si on the surface of the junction termination region3N4Layer shapeForming an insulating layer between the metal electrode and the semiconductor substrate.
Compared with the prior art, the invention has the advantages that: (1) using Si3N4As an annealing protection layer of the semiconductor substrate, the annealing protection layer can effectively prevent the precipitation of Si, thereby protecting the surface appearance of the semiconductor substrate from being damaged. (2) After annealing, Si may be annealed3N4The layer is used as an insulating layer of a semiconductor device, thereby eliminating the need for Si3N4The layers are completely removed, which simplifies the production steps. (3) At annealing temperature, Si3N4The material does not decompose and chemically react with SiC and impurity species doped within the semiconductor substrate, and therefore does not introduce contamination into the semiconductor substrate during annealing, which protects the semiconductor device.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 schematically shows the steps of a method for manufacturing a doped semiconductor device according to the invention.
Fig. 2 schematically shows an embodiment of a semiconductor device according to the invention.
In the drawings, like parts are provided with like reference numerals. The drawings are not to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
Fig. 1 schematically shows the steps of a method for the preparation of a doped semiconductor device according to the invention, wherein the semiconductor substrate is SiC.
In fig. 1, state 1 schematically shows a state after ion implantation is performed on the SiC substrate 10. SiC substrate 10 may include a SiC substrate 11 and a SiC epitaxial layer 12, with dopant ions 13 implanted within SiC epitaxial layer 12. In one embodiment, the implanted doping element may be Al or N, P. The concentration of the implanted ions can be adjusted according to actual needs. Ion implantation methods are well known to those skilled in the art and will not be described in detail herein.
State 2 schematically shows the formation of Si in the SiC epitaxial layer 123N4Condition of the protective layer 20. Si3N4The protective layer 20 completely covers the SiC epitaxial layer 12, which prevents Si from being precipitated in the SiC epitaxial layer 12 during annealing of the SiC substrate 10. In one embodiment, the Si may be prepared using an LPCVD process (i.e., low pressure chemical vapor deposition)3N4And a protective layer 20. In the LPCVD method, the temperature is 400-800 ℃ and the pressure is 0.1-3 torr. The SiH4The flow rate of (2) is 30-70sccm, N2The flow rate is 40-90 sccm. In a preferred embodiment, Si is prepared3N4The thickness of the protective layer 20 is between 200nm and 2000 nm. Si of such thickness3N4The protective layer 20 is sufficient to prevent Si precipitation in the SiC epitaxial layer 12 during annealing. Furthermore, Si is added subsequently3N4In the step of patterning the protective layer 20, a part of the SiC epitaxial layer 12 can be etched away relatively quickly, thereby speeding up the production of the semiconductor device.
State 3 shows a state after the SiC substrate 10 is annealed. In one embodiment, the annealing temperature may be between 1700 ℃ and 1800 ℃. Due to Si3N4Is very stable and does not decompose until temperatures above 1900 deg.C, so that at this annealing temperature, Si is present3N4The protective layer 20 is still well present on the SiC epitaxial layer 12.
Table 1 illustrates the preparation of doped semiconductor devices according to the present invention in three specific examples. As can be seen from Table 1, Si is present when the SiC base material 10 is annealed3N4The material can be used as a protective layer for the SiC substrate 10.
TABLE 1
Optional steps may also be preferably performed after state 3, as shown by the dashed boxes in fig. 1 for states 4, 5 and 6. Si can be converted by the steps shown in states 4, 5 and 63N4For protective layer 20As an insulating layer for subsequently fabricated semiconductor devices.
State 4 shows that in Si3N4 An etching mask 40 is provided on a partial region of the protective layer 20. Thus, Si without the mask 40 can be etched3N4Region 41 of protective layer 20 is etched away to form window region 51 and then mask 40 is removed, thus realizing Si3N4Patterning of the protective layer 20, as shown in state 5. Etching methods are well known to those skilled in the art, and for example, wet etching may be performed using hydrofluoric acid, phosphoric acid, or the like, or CF may be used4And SF6The mixed gas of (2) is subjected to dry etching, which is not described in detail herein. Window region 51 partially exposes SiC epitaxial layer 12. State 6 shows that in window region 51 and Si3N4Metal electrodes 61, 62, 63 are provided on the remaining regions of the protective layer 20, respectively. Thus, Si3N4The protective layer 20 forms an insulating layer between the metal electrodes 61, 63 and the SiC epitaxial layer 12. Due to Si3N4The material has a resistivity of as high as 1015 Ω · cm to 1016 Ω · cm, so it can be fully used as an insulating layer.
Fig. 2 schematically shows an SBD device 200 prepared according to the method of the present invention. The SBD device 200 includes a SiC body 202, a drift layer 203 is epitaxially grown on one side of the SiC substrate material 202, and an active region 204 and a junction termination region 205 are formed on the drift layer 203 by doping as shown in fig. 1. Si is formed as an insulating layer on the surface of the junction termination region 2053N4Layer 206. An anode electrode 208 is formed on the source region 204 and the insulating layer 206 in a partial region. A passivation layer 207 is formed on the insulating layer 206 and the anode electrode 208 in a partial region, and a cathode electrode 201 is formed on the other side of the SiC substrate.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as no conflict exists. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (6)
1. A method of making a doped semiconductor device comprising the steps of:
step one, after doping a SiC semiconductor base material comprising a SiC substrate and a SiC epitaxial layer, forming Si on the surface of the SiC epitaxial layer3N4A protective layer;
step two, carrying the Si3N4Annealing the SiC semiconductor substrate of the protective layer at 1700-1800 ℃ to prevent Si from being separated out from the SiC epitaxial layer;
step three, in the Si3N4Etching a window region on the protective layer to expose the SiC semiconductor substrate, Si not etched away and at the window region3N4A metal electrode is arranged on the protective layer, wherein the Si which is not etched away3N4A protective layer forms an insulating layer between the metal electrode and the SiC epitaxial layer.
2. The production method according to claim 1, wherein in the first step, the Si is present3N4The thickness of the protective layer is between 200nm and 2000 nm.
3. The method according to claim 1 or 2, wherein in the first step, the Si is prepared using an LPCVD method or a PECVD method3N4And a protective layer.
4. The production method according to claim 3, wherein in the LPCVD method, the raw material used is N2And SiH4The temperature is 400 ℃ and 800 ℃, and the pressure is 0.1-3 torr.
5. The method of claim 4, wherein the SiH is4The flow rate of (2) is 30-70sccm, N2The flow rate of (2) is 40-90 sccm.
6. A semiconductor device produced by the production method according to any one of claims 1 to 5, comprising a semiconductor base body on which an active region and a junction termination region are formed,
si is formed as an insulating layer on the surface of the junction termination region3N4A layer of a material selected from the group consisting of,
si on the surface of the active region and junction termination region partial region3N4A metal electrode is disposed on the layer.
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| CN201610947670.3A CN108010840B (en) | 2016-11-02 | 2016-11-02 | Method for manufacturing doped semiconductor device and semiconductor device |
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