CN107996000A - Epitaxial source regions for uniform threshold voltages of vertical transistors in 3D memory devices - Google Patents

Abstract

Body is alternately stacked what substrate formed insulating layer and sacrificial material layer.Memory stacking body structure is formed through body is alternately stacked.Dorsal part groove is formed, and sacrificial material layer is replaced with conductive layer.Formed in the trench after insulation gap body, grow extension base construction from the semiconductor portions below dorsal part groove.Source area is formed by the way that dopant is incorporated into extension base construction and following semiconductor portions during and/or after epitaxial growth.Alternately, dorsal part groove can be simultaneously formed with forming memory opening.Extension base construction can be formed with forming epi channels partial concurrence at the bottom of each memory opening.After being formed in dorsal part groove and subsequently removing illusory trench fill structure, source area is formed by the way that dopant is incorporated into extension base construction.

Description

Epitaxial sources for uniform threshold voltages of vertical transistors in 3D memory devices polar region

Cross References to Related Applications

This application claims priority to US Application No. 14/867,351, filed September 28, 2015, the disclosure of which is incorporated herein by reference in its entirety.

technical field

The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabrication thereof.

Background technique

In the article entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" published in IEDM Proc. (2001) 33-36 by T. Endoh et al. 3D vertical NAND strings.

Contents of the invention

According to aspects of the present disclosure, there is provided a three-dimensional memory device comprising alternating stacks of insulating layers and conductive layers over a substrate; a memory stack structure extending through the alternating stacks; and a source The source region includes a substrate source portion in the substrate, and an epitaxial pedestal source portion overlying and aligned with the epitaxial source portion of the substrate.

According to another aspect of the present disclosure, a method of manufacturing a three-dimensional memory device is provided. An alternating stack comprising insulating layers and layers of sacrificial material is formed over the single crystalline semiconductor material portion of the substrate. A memory stack structure is formed extending through the alternating stacks. Backside trenches are formed through the alternating stack. The top surface of the portion of the single crystal semiconductor material is physically exposed at the bottom of the backside trench. An epitaxial pedestal structure is formed on the top surface of the single crystal semiconductor material portion in epitaxial alignment with the single crystal semiconductor material portion. The source region is formed by doping the epitaxial pedestal structure and the surface region of the portion of monocrystalline semiconductor material underlying the epitaxial pedestal structure. The step of doping occurs during the step of forming the epitaxial pedestal structure, after the step of forming the epitaxial pedestal structure, or during the step of forming the epitaxial pedestal structure and after the step of forming the epitaxial pedestal structure.

Description of drawings

1 is a vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers and memory openings extending through the alternating stacks according to a first embodiment of the present disclosure.

2A-2H are sequential vertical cross-sectional views of memory openings within the first exemplary structure during various process steps used to form the memory stack structure according to the first embodiment of the present disclosure.

3 is a vertical cross-sectional view of a first exemplary structure after forming a memory stack structure according to the first embodiment of the present disclosure.

4 is a vertical cross-sectional view of the first exemplary structure after forming the set of stepped surfaces and reverse-stepped dielectric material portions according to the first embodiment of the present disclosure.

5 is a vertical cross-sectional view of a first exemplary structure after forming a dielectric column structure according to the first embodiment of the present disclosure.

6A is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

6B is a perspective top view of the first exemplary structure of FIG. 6A. Vertical plane A-A' is the plane of the vertical cross-sectional view of Fig. 6A.

7 is a vertical cross-sectional view of the first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

8 is a vertical cross-sectional view of the first exemplary structure after deposition of conductive material in the backside recesses and backside trenches according to the first embodiment of the present disclosure.

9 is a vertical cross-sectional view of the first exemplary structure after removal of conductive material from the backside trenches according to the first embodiment of the present disclosure.

10 is a vertical cross-sectional view of the first exemplary structure after forming insulating spacers according to the first embodiment of the present disclosure.

11 is a vertical cross-sectional view of the first exemplary structure after forming the epitaxial column structure according to the first embodiment of the present disclosure.

12A is a vertical vertical cross-sectional view of the first exemplary structure after forming a source region according to the first embodiment of the present disclosure. FIG. 12B is a vertical cross-sectional view of an enlarged region M in FIG. 12A.

Figure 12C illustrates various types of vertical dopant concentration profiles in the source region of Figure 12A.

12D and 12E are schematic current-voltage diagrams of memory devices according to the prior art and according to embodiments of the present disclosure, respectively.

13 is a vertical cross-sectional view of the first exemplary structure after forming the backside contact via structure according to the first embodiment of the present disclosure.

14A is a vertical cross-sectional view of the first exemplary structure after forming various additional contact via structures according to an embodiment of the present disclosure.

14B is a perspective top view of the first exemplary structure of FIG. 14A. Vertical plane A-A' is the plane of the vertical cross-sectional view of Fig. 14A.

15A is a vertical cross-sectional view of a second exemplary structure after forming memory openings and backside trenches according to the second embodiment of the present disclosure.

15B is a perspective top view of the exemplary structure of FIG. 15A. Vertical plane A-A' is the plane of the vertical cross-sectional view of Fig. 15A.

16 is a vertical cross-sectional view of a second exemplary structure after forming epitaxial channel portions and epitaxial column structures according to the second embodiment of the present disclosure.

17 is a vertical cross-sectional view of a second exemplary structure after forming a memory stack structure and a dummy trench filling structure according to a second embodiment of the present disclosure.

18 is a vertical cross-sectional view of a second exemplary structure after formation of a stepped surface, a reverse-stepped dielectric material portion, and a second contact-level dielectric layer according to a second embodiment of the present disclosure.

19 is a vertical cross-sectional view of the second exemplary structure after removing the dummy trench-fill structure and the recess of the optional epitaxial pillar structure according to the second embodiment of the present disclosure.

20 is a vertical cross-sectional view of a second exemplary structure after forming insulating spacers according to a second embodiment of the present disclosure.

21 is a vertical cross-sectional view of a second exemplary structure after forming a source region according to a second embodiment of the present disclosure.

22A is a vertical cross-sectional view of the second exemplary structure after forming the backside contact via structure and the additional contact via structure according to the second embodiment of the present disclosure.

FIG. 22B is a vertical cross-sectional view of an enlarged region M in FIG. 22A.

Detailed ways

As discussed above, the present disclosure relates to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabrication thereof, aspects of which are described below. Embodiments of the present disclosure may be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional monolithic memory array devices including multiple NAND memory strings. The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be duplicated unless expressly described or clearly indicated to the contrary that there is no duplication of the element. Ordinal numbers such as "first", "second" and "third" are used only to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. As used herein, a first element being "on" a second element may be on the exterior side of the surface of the second element or on the interior side of the second element. As used herein, a first element is "directly on" a second element if there is physical contact between a surface of the first element and a surface of the second element.

As used herein, "layer" refers to a portion of material comprising regions of substantially uniform thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than that of the continuous structure. For example, a layer may lie between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically, and/or along the tapered surface. A substrate can be a layer, can contain one or more layers therein, and/or can have one or more layers thereon, above, and/or below.

As used herein, "field effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows at a current density modulated by an external electric field. . As used herein, "active region" refers to the source region of a field effect transistor or the drain region of a field effect transistor. "Top active region" refers to the active region of a field effect transistor located above the active region of another field effect transistor. "Bottom active region" refers to the active region of a field effect transistor located below the active region of another field effect transistor. A monolithic three-dimensional memory array is one in which multiple memory levels are formed over a single substrate, such as a semiconductor wafer, without intervening substrates. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each underlying level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form non-monolithic memory devices. For example, non-monolithically stacked memories have been formed by forming memory levels on separate substrates and stacking the memory levels vertically, as described in US Patent No. 5,915,167, entitled "Three-dimensional Structure Memory." The substrates may be thinned or removed from the memory levels prior to bonding, but because the memory levels are initially formed on separate substrates, such memories are not true monolithic three-dimensional memory arrays. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using various embodiments described herein.

Referring to FIG. 1 , there is illustrated a first exemplary structure according to an embodiment of the present disclosure, which may be used, for example, to fabricate device structures including vertical NAND memory devices. Exemplary structures include a substrate, which may be a semiconductor substrate (eg, a single crystal silicon wafer). The substrate may include a substrate semiconductor layer 10 . The substrate semiconductor layer 10 may be an upper portion of the substrate (e.g., the top portion of the silicon wafer) or it may be a layer of semiconductor material located on top of the substrate (e.g., above the top surface of the silicon wafer), and may comprise at least one elemental semiconductor material (e.g., silicon, such as single crystal silicon), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or the present Other semiconductor materials known in the art.

As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range from 1.0 x ^10-6 S/cm to 1.0 x ¹⁰⁵ S/cm, and upon appropriate doping with an electrical dopant, Doped materials can then be produced with conductivities ranging from 1.0 S/cm to 1.0×10 ⁵ S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. miscellaneous agent. As used herein, "conductive material" refers to a material with an electrical conductivity greater than 1.0×10 ⁵ S/cm. As used herein, "insulating material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 ⁻⁶ S/cm. All measurements of conductivity were performed under standard conditions. The substrate semiconductor layer 10 may include at least one doped well (not explicitly shown) having a substantially uniform dopant concentration therein.

Exemplary structures can have multiple regions to build different types of devices. Such regions may include, for example, device region 100 , contact region 300 , and peripheral device region 200 . In one embodiment, the substrate semiconductor layer 10 may contain at least one doped well in the device region 100 . As used herein, "doped well" refers to a doped portion of a semiconductor material having the same conductivity type (which may be p-type or n-type) and substantially the same level of dopant concentration throughout. The doped well may be the same as the substrate semiconductor layer 10 or may be a part of the substrate semiconductor layer 10 . The conductivity type of the doped well is referred to herein as the first conductivity type, which may be p-type or n-type. The dopant concentration level at which the wells are doped is referred to herein as the first dopant concentration level. In one embodiment, the first dopant concentration level may range from 1.0×10 ¹⁵ /cm ³ to 1.0×10 ¹⁸ /cm ³ , although lower or higher dopant concentration levels may also be used. . As used herein, a dopant concentration level refers to the average dopant concentration for a given region.

The peripheral device 210 may be formed in or on a portion of the substrate semiconductor layer 10 located within the peripheral device region 200 . The peripheral devices may include various devices to operate memory devices to be formed in the device region 100 and may include, for example, driving circuits for various components of the memory devices. Peripheral devices 210 may include, for example, field effect transistors and/or passive components such as resistors, capacitors, inductors, diodes, and the like.

Optionally, a gate dielectric layer 12 may be formed over the substrate semiconductor layer 10 . The gate dielectric layer 12 may serve as a gate dielectric for the first source select gate electrode. The gate dielectric layer 12 may comprise, for example, silicon oxide and/or a dielectric metal oxide (such as HfO ₂ , ZrO ₂ , LaO _{2 ,} etc.). The thickness of the gate dielectric layer 12 may range from 3 nm to 30 nm, although smaller or larger thicknesses may also be used.

Alternating stacks of first material layers (which may be insulating layers 32 ) and second material layers (which are referred to as spacer material layers) are formed on the top surface of the substrate, which may be, for example, on top of the gate dielectric layer 12 . On the surface. As used herein, "material layer" refers to a layer whose entirety comprises material. As used herein, a "layer of spacer material" refers to a layer of material positioned between two other layers of material (ie, between an upper layer of material and a lower layer of material). The layer of spacer material may be formed as a conductive layer, or may be replaced with a conductive layer in a subsequent process step.

As used herein, an alternating stack of first and second elements refers to a structure in which instances of the first element alternate with instances of the second element. Each instance of an end element in the first element that is not an alternating multiplicity is bordered on both sides by two instances of the second element, and each instance of an end element in the second element that is not an alternating multiplicity is bordered on both sides by The two instances of the first element adjoin. The first elements may have the same thickness therebetween, or may have different thicknesses. The second elements may have the same thickness therebetween, or may have different thicknesses. Alternating multiple layers of first material and layers of second material may begin with instances of the first material layer or begin with instances of the second material layer, and may end with instances of the first material layer or with instances of the second material layer instance. In one embodiment, instances of a first element and instances of a second element may form a unit that repeats periodically within an alternating multiplicity.

Each first material layer comprises a first material, and each second material layer comprises a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32 and each second material layer may be a sacrificial material layer 42 . In this case, the stack may comprise an alternating plurality of insulating layers 32 and sacrificial material layers 42 and constitute a prototype stack comprising alternating layers of insulating layers 32 and sacrificial material layers 42 . As used herein, a "prototype" structure or an "in-process" structure refers to a temporary structure that is subsequently modified in the shape or composition of at least one constituent therein.

A stack of alternating multiples is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack ( 32 , 42 ) may include an insulating layer 32 composed of a first material, and a sacrificial material layer 42 composed of a second material different from the material of the insulating layer 32 . The first material of the insulating layer 32 may be at least one insulating material. Thus, each insulating layer 32 may be a layer of insulating material. Insulating materials that may be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin Dielectric coated materials, dielectric metal oxides and silicates thereof, dielectric metal oxynitrides and Silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

The second material of the sacrificial material layer 42 is a sacrificial material that can be removed selectively to the first material of the insulating layer 32 . As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material "of. The ratio of the rate of removal of the first material to the rate of removal of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material.

The layer of sacrificial material 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of sacrificial material layer 42 may subsequently be replaced with a conductive electrode, which may function, for example, as a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials such as amorphous silicon, and polycrystalline semiconductor materials such as polycrystalline silicon. In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride, or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the insulating layer 32 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

The sacrificial material layer 42 may be suitably patterned such that the portion of conductive material that will be subsequently formed by replacement of the sacrificial material layer 42 may serve as a conductive electrode, such as a control gate electrode that will be subsequently formed of a monolithic three-dimensional NAND string memory device. . The sacrificial material layer 42 may include a portion having a stripe shape extending substantially parallel to the top surface of the substrate.

The thickness of insulating layer 32 and sacrificial material layer 42 may range from 20 nm to 50 nm, although smaller or larger thicknesses may be employed for each insulating layer 32 and for each sacrificial material layer 42 . The number of repetitions of pairs of insulating layer 32 and sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 may range from 2 to 1024, and typically from 8 to 256, although larger values may also be used. number of repetitions. The top and bottom gate electrodes in the stack can be used as select gate electrodes. In one embodiment, each layer of sacrificial material 42 in the alternating stack ( 32 , 42 ) may have a uniform thickness that is substantially constant within each respective layer of sacrificial material 42 .

Optionally, an insulating cap layer 70 may be formed over the alternating stacks (32, 42). The insulating cap layer 70 comprises a different dielectric material than the material of the sacrificial material layer 42 . In one embodiment, the insulating cap layer 70 may comprise a dielectric material, which may be used for the insulating layer 32 described above. The insulating cap layer 70 may be thicker than each of the insulating layers 32 . The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

A stack of photoresist material (not shown) comprising at least a layer of photoresist may be formed over the insulating cap layer 70 and the alternating stacks (32, 42) and may be photolithographically patterned to An opening is formed therein. The pattern in the photoresist material stack can be transferred through the insulating cap layer 70 and through the alternating stacks (32, 42) by at least one anisotropic etch using the patterned photoresist material stack as an etch mask Overall. The portions of the alternating stacks ( 32 , 42 ) underlying the openings in the patterned stack of photoresist material are etched to form first memory openings 49 . In other words, the transfer of the pattern in the patterned photoresist material stack through the alternating stacks (32, 42) forms a first memory opening extending through the alternating stacks (32, 42). The chemistry of the anisotropic etching process used to etch materials through the alternating stack (32, 42) may be alternated to optimize the etching of the first material and the second material in the alternating stack (32, 42). Anisotropic etching can be, for example, a series of reactive ion etching. Optionally, the gate dielectric layer 12 may act as an etch stop layer between the alternating stacks (32, 42) and the substrate. The sidewalls of the first reservoir opening may be substantially vertical, or may be tapered. The patterned lithographic material stack can be subsequently removed, for example by ashing.

A memory stack structure may be formed in each memory opening. 2A-2H illustrate sequential vertical cross-sectional views of a memory opening during formation of an exemplary memory stack structure. Formation of the exemplary memory stack structure may be performed within each of the memory openings 49 in the exemplary structure shown in FIG. 1 .

Referring to FIG. 2A , a memory opening 49 is illustrated. The memory opening 49 extends through the insulating cap layer 70 , the alternating stacks ( 32 , 42 ), and the gate dielectric layer 12 , and optionally into an upper portion of the substrate semiconductor layer 10 . The recess depth of the bottom surface of each memory opening 49 relative to the top surface of the substrate semiconductor layer 10 may range from 0 nm to 30 nm, although greater recess depths may be used. Alternatively, the layer of sacrificial material 42 may be partially laterally recessed, for example by isotropic etching, to form lateral recesses (not shown).

Referring to FIG. 2B , epitaxial channel portions 11 may optionally be formed at the bottom of each memory opening 49 by selective epitaxy of semiconductor material. During the selective epitaxy process, reactant gas and etchant gas may flow into the process chamber simultaneously or alternately. The semiconducting and dielectric surfaces of the exemplary structures provide different nucleation rates of the semiconducting material. By setting the etch rate of the semiconductor material (determined by the etchant gas flow) to be greater than the nucleation rate of the semiconductor material on the dielectric surface and less than the nucleation rate of the semiconductor material on the semiconductor surface, the semiconductor material can be removed from the physically exposed semiconductor Surface (ie, from the physically exposed surface of the substrate semiconductor layer 10 at the bottom of each memory opening 49 ) grows. Each portion of the deposited semiconductor material constitutes an epitaxial channel portion 11 comprising a single crystal semiconductor material (for example, single crystal silicon) in epitaxial alignment with the single crystal semiconductor material (for example, single crystal silicon) of the substrate semiconductor layer 10 . Thus, epitaxial channel portion 11 is formed at the bottom of each memory opening 49 directly on the single crystal semiconductor surface of substrate semiconductor layer 10 which is the topmost portion of the substrate. Each epitaxial channel portion 11 serves as a part of a channel of a vertical field effect transistor. The top surface of epitaxial channel portion 11 may be between the pair of sacrificial material layers 42 . In other words, the periphery of each epitaxial channel portion 11 may be in physical contact with the sidewall of insulating layer 32 . A cavity 49' exists above the epitaxial channel portion 11 in each memory opening 49.

Referring to FIG. 2C, a series of layers comprising at least one blocking dielectric layer (501L, 503L), continuous memory material layer 504, tunneling dielectric layer 506L, and optional first semiconductor channel layer 601L may be sequentially deposited on the memory In the opening 49. The at least one blocking dielectric layer (501L, 503L) may comprise, for example, a first blocking dielectric layer 501L and a second blocking dielectric layer 503L.

In an illustrative example, a first blocking dielectric layer 501L may be deposited on the sidewalls of each memory opening 49 by conformal deposition. The first blocking dielectric layer 501L includes a dielectric material, which may be a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the first blocking dielectric layer 501L may include a dielectric metal oxide having a dielectric constant greater than 7.9, ie, having a dielectric constant greater than that of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (LaO ₂ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide ( Ta ₂ O ₅ ), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The first blocking dielectric layer 501L may be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. The thickness of the first blocking dielectric layer 501L may range from 1 nm to 20 nm, although smaller or larger thicknesses may also be used. The first blocking dielectric layer 501L may then serve as a portion of dielectric material that blocks leakage of stored charge to the control gate electrode. In one embodiment, the first blocking dielectric layer 501L includes aluminum oxide.

The second blocking dielectric layer 503L may be formed on the first blocking dielectric layer 501L. The second blocking dielectric layer 503L may contain a different dielectric material than that of the first blocking dielectric layer 501L. In one embodiment, the second blocking dielectric layer 503L may comprise silicon oxide, a dielectric metal oxide having a different composition than the first blocking dielectric layer 501L, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the second blocking dielectric layer 503L may include silicon oxide. The second blocking dielectric layer 503L may be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the second blocking dielectric layer 503L may range from 1 nm to 20 nm, although smaller or larger thicknesses may also be used. Alternatively, the first blocking dielectric layer 501L and/or the second blocking dielectric layer 503L may be omitted, and the blocking dielectric layer may be formed after forming the backside recess on the surface of the memory film to be formed later.

The continuous memory material layer 504, the tunnel dielectric layer 506L, and the optional first semiconductor channel layer 601L may be sequentially formed. In one embodiment, the continuous memory material layer 504 may be a charge trapping material comprising a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the continuous memory material layer 504 may comprise a conductive material such as doped polysilicon or a metallic material that is patterned into a plurality of electrically isolated portions (e.g., floating gate). In one embodiment, the continuous memory material layer 504 includes a silicon nitride layer.

The continuous memory material layer 504 may be formed as a single memory material layer of homogeneous composition, or may comprise a stack of multiple memory material layers. The multiple layers of memory material, if employed, may include multiple spaced apart layers of floating gate material containing conductive materials such as, for example, tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and other Alloyed metals, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and/or semiconductor materials (e.g., containing at least one Polycrystalline or amorphous semiconductor materials of elemental semiconductor elements or at least one compound semiconductor material). Alternatively, or in addition, the continuous layer of memory material 504 may comprise an insulating charge trapping material, such as one or more segments of silicon nitride. Alternatively, the continuous memory material layer 504 may comprise conductive nanoparticles such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. Continuous memory material layer 504 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique to store charge therein. The thickness of the continuous memory material layer 504 may range from 2nm to 20nm, although smaller or larger thicknesses may also be used.

Tunneling dielectric layer 506L comprises a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 506L may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 506L may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 506L may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 506L may range from 2nm to 20nm, although smaller or larger thicknesses may also be used.

The optional first semiconductor channel layer 601L contains a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material , or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601L includes amorphous silicon or polycrystalline silicon. The first semiconductor channel layer 601L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601L may range from 2 nm to 10 nm, although smaller or larger thicknesses may also be used. A cavity 49' is formed in the volume of each reservoir opening 49 not filled with the deposited material layer (501L, 503L, 504L, 506L, 601L).

Referring to FIG. 2D, at least one anisotropic etching process is used to sequentially anisotropically etch the optional first semiconductor channel layer 601L, the tunneling dielectric layer 506L, the continuous memory material layer 504, at least one blocking dielectric layer ( 501L, 503L). The first semiconductor channel layer 601L, the tunneling dielectric layer 506L, the continuous memory material layer 504, and at least one blocking dielectric layer (501L, 503L) located on the insulating cap layer 70 may be removed by at least one anisotropic etching process. the portion above the top surface. Furthermore, horizontal portions of the first semiconductor channel layer 601L, the tunneling dielectric layer 506L, the continuous memory material layer 504, and at least one blocking dielectric layer (501L, 503L) at the bottom of each cavity 49' may be removed, to form openings in the remainder of it. Each of the first semiconductor channel layer 601L, the tunneling dielectric layer 506L, the continuous memory material layer 504, and the at least one blocking dielectric layer (501L, 503L) may be etched by an anisotropic etching process.

Each remaining portion of the first semiconductor channel layer 601L constitutes the first semiconductor channel portion 601 . Each remaining portion of tunneling dielectric layer 506L constitutes tunneling dielectric 506 . Each remaining portion of the continuous memory material layer 504 is referred to herein as a memory material layer 504 . The memory material layer 504 may include charge trapping material or floating gate material. In one embodiment, each layer of memory material 504 may comprise a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the memory material layer 504 may be a charge storage layer, wherein each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region. Each remaining portion of the second blocking dielectric layer 503L is referred to herein as a second blocking dielectric 503 . Each remaining portion of the first blocking dielectric layer 501L is referred to herein as a first blocking dielectric 501 .

The surface of the epitaxial channel portion 11 (or the surface of the substrate semiconductor layer 10 if the epitaxial channel portion 11 is not used) may pass through the first semiconductor channel portion 601, the tunneling dielectric 506, the memory material layer 504, And at least one blocking dielectric (501, 503) is physically exposed below the opening. Alternatively, the physically exposed semiconductor surface at the bottom of each cavity 49' may be vertically recessed such that the recessed semiconductor surface below the cavity 49' is removed from the epitaxial channel portion 11 (or without the epitaxial channel portion 11 11, the topmost surface of the substrate semiconductor layer 10 is vertically offset by the recess distance. Tunneling dielectric 506 is over layer 504 of memory material. The combination of at least one blocking dielectric (501, 503) in memory opening 49, memory material layer 504, and tunneling dielectric 506 constitutes memory film 50, which includes a plurality of charge storage regions (implemented as memory material layer 504), charge storage The region is insulated from surrounding material by at least one blocking dielectric (501, 503) and a tunneling dielectric 506.

In one embodiment, the first semiconductor channel portion 601 , the tunneling dielectric 506 , the memory material layer 504 , the second blocking dielectric 503 , and the first blocking dielectric 501 may have vertically coincident sidewalls. As used herein, a first surface is "perpendicularly coincident" with a second surface if there is a vertical plane that includes both the first surface and the second surface. Such a vertical plane may or may not have horizontal curvature, but does not contain any curvature along the vertical direction, ie extending straight up or down.

Referring to FIG. 2E, the second semiconductor channel layer 602L may be deposited directly on the semiconductor surface of the epitaxial channel portion 11 (or directly on the substrate semiconductor layer 10 if the portion 11 is omitted), and deposited directly on the first on the semiconductor channel portion 601 . The second semiconductor channel layer 602L contains a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or this Other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602L includes amorphous silicon or polysilicon. The second semiconductor channel layer 602L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602L may range from 2 nm to 10 nm, although smaller or larger thicknesses may also be used. The second semiconductor channel layer 602L may partially fill the cavity 49' in each memory opening, or may completely fill the cavity in each memory opening.

Materials of the first semiconductor channel portion 601 and the second semiconductor channel layer 602L are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a group of all semiconductor materials in the first semiconductor channel portion 601 and the second semiconductor channel layer 602L.

Referring to FIG. 2F, in the event that the cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602L, a dielectric core layer 62L may be deposited in the cavity 49' to fill the cavity in each memory opening. 49' for any remainder. Dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. Dielectric core layer 62L may be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring to FIG. 2G , a horizontal portion of dielectric core layer 62L may be removed from above the top surface of insulating cap layer 70 , eg, by recess etching. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62 . In addition, the horizontal portion of the second semiconductor channel layer 602L above the top surface of the insulating cap layer 70 may be removed by a planarization process, which may employ recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602L within the memory opening constitutes a second semiconductor channel portion 602 .

Each contiguous pair of the first semiconductor channel portion 601 and the second semiconductor channel portion 602 can collectively form a semiconductor channel 60 through which current can flow when the vertical NAND device containing the semiconductor channel 60 is turned on. 60 flows. Tunneling dielectric 506 is embedded within memory material layer 504 and laterally surrounds portions of semiconductor channel 60 . Each contiguous group of first blocking dielectric 501 , second blocking dielectric 503 , memory material layer 504 , and tunneling dielectric 506 collectively constitutes memory film 50 , which is capable of storing charge with a macroscopic retention time. In some embodiments, in this step, the first blocking dielectric 501 and/or the second blocking dielectric 503 may not exist in the memory film 50, and the blocking dielectric may be formed subsequently after forming the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a persistent memory device, such as a retention time exceeding 24 hours.

Referring to FIG. 2H , the top surface of each dielectric core 62 may be further recessed within each memory opening, eg, by recess etching, to a depth between the top surface and the bottom surface of insulating cap layer 70 . Drain regions 63 may be formed by depositing a doped semiconductor material in each recessed region above dielectric core 62 . The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from above the top surface of insulating cap layer 70 to form drain region 63 , for example, by chemical mechanical planarization (CMP) or recess etching.

An exemplary memory stack structure 55 may be embedded in the exemplary structure shown in FIG. 1 . FIG. 3 illustrates an example structure incorporating multiple instances of the example memory stack structure of FIG. 2H. Memory stack structures 55 are formed over and directly above the corresponding epitaxial channel portions. Each exemplary memory stack structure 55 includes a semiconductor channel (601, 602); a tunneling dielectric layer 506 laterally surrounding the semiconductor channel (601, 602); and a vertical stack of charge storage regions laterally Surrounding tunneling dielectric layer 506 (eg implemented as memory material layer 504). Exemplary structures include semiconductor devices comprising a stack comprising alternating multiple layers of material (eg, layers of sacrificial material 42 ) and insulating layers 32 over a semiconductor substrate (eg, over substrate semiconductor layer 10 ). 32, 42), and a memory opening extending through the stack (32, 42). The semiconductor device further includes a first blocking dielectric 501 extending vertically from the bottommost layer of the stack (eg, the bottommost sacrificial material layer 42) to the topmost layer of the stack (eg, the topmost sacrificial material layer 42), and contacts the memory The sidewalls of the opening and the horizontal surface of the semiconductor substrate. Although the present disclosure has been described using the illustrated configuration of a memory stack structure, the methods of the present disclosure may be applied to alternative memory stack structures that include polycrystalline semiconductor channels.

Referring to FIG. 4 , an optional first contact level dielectric layer 71 may be formed over the substrate semiconductor layer 10 . As an optional structure, the first contact level dielectric layer 71 may or may not be formed. In the case of forming the first contact level dielectric layer 71, the first contact level dielectric layer 71 comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, porous or non-porous organosilicate glass (OSG) , or a combination thereof. If an organosilicate glass is employed, the organosilicate glass may or may not be doped with nitrogen. The first contact-level dielectric layer 71 may be formed over a horizontal plane including the top surface of the insulating cap layer 70 and the top surface of the drain region 63 . The first contact level dielectric layer 71 may be deposited by chemical vapor deposition, atomic layer deposition (ALD), spin coating, or a combination thereof. The thickness of the first contact level dielectric layer 71 may range from 10 nm to 300 nm, although smaller or larger thicknesses may also be used.

In one embodiment, the first contact level dielectric layer 71 may be formed as a dielectric material layer having a uniform thickness throughout. The first contact level dielectric layer 71 may be formed as a single layer of dielectric material, or may be formed as a stack of multiple layers of dielectric material. Alternatively, the formation of the first contact-level dielectric layer 71 may be combined with the formation of at least one line-level dielectric layer (not shown). Although the present disclosure has been described with embodiments in which the first contact-level dielectric layer 71 is a structure separate from an optional second contact-level dielectric layer or at least one line-level dielectric layer to be subsequently deposited, it is expressly contemplated herein that the first contact-level dielectric layer A contact-level dielectric layer 71 and at least one line-level dielectric layer are formed in the same process step and/or as embodiments of the same material layer.

In one embodiment, the first contact level dielectric layer 71 , the insulating cap layer 70 , and the alternating stacks ( 32 , 42 ) may be removed from the peripheral device region 200 , eg, by a masked etch process. Furthermore, a stepped cavity may be formed within the contact region 300 by patterning a portion of the alternating stacks (32, 42). As used herein, "stepped cavity" refers to a cavity with a stepped surface. As used herein, "stepped surface" refers to a group of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first edge extending upwardly from a first edge of the horizontal surface. A vertical surface is adjacent to a second vertical surface extending downward from the second edge of the horizontal surface. By "step" is meant a vertical offset in the height of the group of adjoining surfaces.

The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity in the steps varies as a function of the vertical distance from the top surface of the substrate semiconductor layer 10 . In one embodiment, a stepped cavity may be formed by repeatedly performing a set of process steps. The set of process steps may comprise, for example, a first type of etching process that vertically increases the depth of the cavity by one or more stages, and a second type of etching process that laterally expands the area to be etched vertically in a subsequent first type of etching process. Two types of etching processes. As used herein, a "level" of a structure comprising alternating stacks is defined as the relative position of pairs of first and second material layers within the structure. After the entire stepped surface has been formed, the layer of masking material used to form the stepped surface may be removed, for example by ashing. Multiple photoresist layers and/or multiple etch processes may be used to form the stepped surface.

A dielectric material, such as silicon oxide, is deposited in the stepped cavity and over the peripheral devices 210 in the peripheral device region 200 . Excess portions of the deposited dielectric material may be removed from above the top surface of the first contact level dielectric layer 71 , for example by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity in the contact region 300 and above the substrate semiconductor layer 10 in the peripheral device region 200 constitutes the reverse stepped dielectric material portion 65 . As used herein, an "inverted stepped" element refers to an element having a stepped surface whose horizontal cross-sectional area increases monotonically as a function of vertical distance from the top surface of the substrate on which the element resides. If silicon oxide is used as the dielectric material, the silicon oxide of the reverse step dielectric material portion 65 may or may not be doped with dopants such as B, P and/or F. The top surface of the reverse step dielectric material portion 65 may be coplanar with the top surface of the first contact level dielectric layer 71 .

The area above the peripheral device 210 and the area above the stepped cavity may be filled with the same dielectric material simultaneously, or in different process steps with the same dielectric material or with different dielectric materials. The cavity above the peripheral device 210 may be filled with the dielectric material before, simultaneously or after the cavity above the stepped surface of the contact region 300 is filled with the dielectric material. Although the present disclosure has been described with an embodiment in which the cavities in the peripheral device region 200 and the step cavities in the contact region 300 are filled simultaneously, it is expressly contemplated herein that the cavities in the peripheral device region 200 and the stepped cavities in the contact region 300 are filled in different process steps. An embodiment of a stepped cavity in the contact region 300 .

Referring to FIG. 5 , dielectric support posts 7P may optionally be formed through the reverse stepped dielectric material portion 65 and/or through the first contact level dielectric layer 71 and/or through the alternating stacks ( 32 , 42 ). In one embodiment, the dielectric support pillar 7P may be formed in the contact region 300 near the device region 100 . The dielectric support pillar 7P may be formed, for example, by forming an opening extending through the reverse stepped dielectric material portion 65 and/or through the alternating stack (32, 42) and reaching at least the top surface of the substrate semiconductor layer 10, And the openings are filled with a dielectric material that is resistant to the etch chemistry used to remove the sacrificial material layer 42 .

In one embodiment, the dielectric support pillar 7P may comprise silicon oxide and/or a dielectric metal oxide such as aluminum oxide. In one embodiment, the portion of the dielectric material that is deposited over the first contact-level dielectric layer 71 simultaneously with the deposition of the dielectric support posts 7P may be present over the first contact-level dielectric layer 71 as a second contact-level dielectric layer 73. Each of the dielectric support pillar 7P and the second-contact-level dielectric layer 73 is an optional structure. Thus, the second contact level dielectric layer 73 may or may not be present over the insulating cap layer 70 and the reverse step dielectric material portion 65 . The first contact-level dielectric layer 71 and the second contact-level dielectric layer 73 are collectively referred to herein as at least one contact-level dielectric layer (71, 73). In one embodiment, at least one contact-level dielectric layer (71, 73) may contain both the first and second contact-level dielectric layers (71, 73), and optionally any additional vias that may be subsequently formed level dielectric layer. In another embodiment, at least one contact-level dielectric layer (71, 73) may comprise only the first contact-level dielectric layer 71 or the second contact-level dielectric layer 73, and optionally any additional vias that may be subsequently formed. Hole level dielectric layer. Alternatively, the formation of the first and second contact level dielectric layers (71, 73) may be omitted, and at least one via level dielectric layer may be formed subsequently, ie after forming the first source contact via structure.

The second contact level dielectric layer 73 and the dielectric support pillar 7P may be formed as a single continuous structure of unitary construction, ie without any material interface therebetween. In another embodiment, portions deposited over the first contact level dielectric layer 71 concurrently with the deposition of dielectric material and the dielectric support pillars 7P may be removed, eg, by chemical mechanical planarization or recess etching. In this case, the second-contact-level dielectric layer 73 does not exist, and the top surface of the first-contact-level dielectric layer 71 may be physically exposed.

Referring to Figures 6A and 6B, a photoresist layer (not shown) may be applied over at least one contact-level dielectric layer (71, 73) and may be photolithographically patterned to provide contact between memory blocks. Openings are formed in the region. In one embodiment, the memory blocks may be laterally spaced apart from each other along a first horizontal direction hd1 (eg, the bit line direction), and each opening in the photoresist layer is sized along the first horizontal direction hd1 It may be smaller than the interval of adjacent clusters (ie, groups) of the memory stack structure 55 along the second horizontal direction hd2 (eg, word line direction). In addition, the size of each opening in the photoresist layer along the second horizontal direction hd2 (which is parallel to the longitudinal direction of each cluster of the memory stack structure 55) may be larger than each cluster of the memory stack structure 55. The range along the first horizontal direction hd1.

The pattern of openings in the photoresist layer may be transferred by transferring a pattern of openings through at least one contact level dielectric layer (71, 73), reverse stepped dielectric material portions 65, and alternating stacks (32, 42). Backside trenches 79 are formed between each adjacent pair of clusters of memory stack structures 55 . The top surface of the substrate semiconductor layer 10 may be physically exposed at the bottom of each backside trench 79 . In one embodiment, each backside trench 79 may extend along the second horizontal direction hd2 such that clusters of memory stack structures 55 are laterally spaced along the first horizontal direction hd1 . Each cluster of the memory stack structure 55 together with the portions of the alternating stacks (32, 42) surrounding the cluster constitute a memory block. Each memory block is laterally spaced from each other by backside trenches 79 .

Referring to FIG. 7 , an etchant that selectively etches the second material of the sacrificial material layer 42 with respect to the first material of the insulating layer 32 may be introduced into the backside trench 79 , for example, using an etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 has been removed. Removal of the second material of the sacrificial material layer 42 may affect the first material of the insulating layer 32, the material of the dielectric support pillar 7P, the material of the reverse step dielectric material portion 65, the semiconductor material of the substrate semiconductor layer 10, and the first The material of the outermost layer of the memory thin film 50 is selective. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32, the dielectric support pillar 7P, and the reverse stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide. In another embodiment, the sacrificial material layer 42 may include a semiconductor material such as polysilicon, and the materials of the insulating layer 32, the dielectric support pillar 7P, and the reverse stepped dielectric material portion 65 may be selected from silicon oxide, silicon nitride, and dielectric metal oxides. In this case, the depth of the backside trench 79 can be varied such that the bottommost surface of the backside trench 79 is located within the gate dielectric layer 12 , ie avoiding physical exposure of the top surface of the substrate semiconductor layer 10 .

The etching process for selectively removing the second material from the first material and the outermost layer of the first memory film 50 may be a wet etching process using a wet etching solution, or may be a process in which an etchant is introduced in a vapor phase. Vapor phase (dry) etch process into backside trench 79. For example, if sacrificial material layer 42 comprises silicon nitride, the etch process may be a wet etch process in which the exemplary structure is immersed in a wet etch bath comprising phosphoric acid for silicon oxide, silicon, and other known methods used in the art. Various other materials selectively etch silicon nitride. Dielectric support pillars 7P, reverse stepped dielectric material portion 65 , and memory stack structure 55 provide structural support, while backside recess 43 exists within the volume previously occupied by sacrificial material layer 42 .

Each backside recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 may be greater than the height of the backside recess 43 . A plurality of backside recesses 43 may be formed within the second volume of material from which the sacrificial material layer 42 has been removed. In contrast to the backside recess 43, the first memory opening in which the memory stack structure 55 is formed is referred to herein as a frontside recess or frontside cavity. In one embodiment, device region 100 includes an array of monolithic three-dimensional NAND strings having multiple device levels disposed over a substrate (eg, over substrate semiconductor layer 10 ). In this case, each backside recess 43 may define a space to receive a corresponding word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate semiconductor layer 10 . The backside recess 43 may be vertically bounded by the top surface of the lower insulating layer 32 and the bottom surface of the upper insulating layer 32 . In one embodiment, each backside depression 43 may have a uniform height throughout. Optionally, a backside blocking dielectric layer may be formed in the backside recess.

Subsequently, physically exposed surface portions of the epitaxial channel portion 11 and source region 61 may be converted to dielectric material portions by thermally and/or plasma converting the semiconductor material into a dielectric material. For example, thermal conversion and/or plasma conversion may be used to convert a surface portion of each epitaxial channel portion 11 into a dielectric spacer 116 and a surface portion of each source region 61 into a sacrificial dielectric portion 616 . In one embodiment, each dielectric spacer 116 may be topomorphic to a torus (ie, generally ring-shaped). As used herein, an element is topologically homeomorphic to a torus if its shape can be continuously stretched into the shape of a torus without destroying pores or forming new pores. Dielectric spacer 116 contains a dielectric material containing the same semiconductor element as epitaxial channel portion 11 and additionally contains at least one nonmetal element such as oxygen and/or nitrogen, so that the material of dielectric spacer 116 is a dielectric material. In one embodiment, the dielectric spacer 116 may comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the epitaxial channel portion 11 . Likewise, each sacrificial dielectric portion 616 includes a dielectric material containing the same semiconductor element as the source region 61, and additionally includes at least one non-metallic element such as oxygen and/or nitrogen, so that the material of the sacrificial dielectric portion 616 is Dielectric material. In one embodiment, sacrificial dielectric portion 616 may comprise a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of source region 61 .

A backside blocking dielectric layer (not shown) may optionally be formed. The backside blocking dielectric layer, if present, includes a dielectric material that serves as the control gate dielectric for the control gate to be subsequently formed in the backside recess 43 . Where there is at least one blocking dielectric within each memory stack structure 55, the backside blocking dielectric layer is optional. In the absence of a blocking dielectric in the memory stack structure 55, a backside blocking dielectric layer is present.

Referring to FIG. 8 , at least one conductive material is deposited in backside recess 43 and backside trench 79 using at least one conformal deposition method, such as chemical vapor deposition or atomic layer deposition. The portion of at least one conductive material deposited in the backside recess 43 constitutes the conductive layer 46 . The portion of at least one conductive material deposited in the backside trench and over the at least one contact-level dielectric layer (71, 73) constitutes a continuous layer of conductive material 46L. The continuous conductive material layer 46L is a continuous layer of at least one conductive material overlying the sidewalls of the backside trench 79 and the at least one contact-level dielectric layer (71, 73).

The at least one conductive material may comprise a conductive metal compound material that functions as a diffusion barrier material and/or an adhesion promoter material. For example, the conductive metal compound material may include a conductive metal nitride (such as TiN, TaN, or WN) or a conductive metal carbide (such as TiC, TaC, or WC). The at least one conductive material may also include a conductive metal filler material, such as Cu, W, Al, Co, Ni, Ru, Mo, Pt, or combinations thereof. In one embodiment, the at least one conductive material may comprise a stack of a conductive metal compound material such as TiN and a conductive metal filler material such as W or Co. The thickness of the deposited at least one conductive material is selected such that the conductive layer 46 fills the entirety of the backside recess 43, while a backside cavity 79' exists in each backside trench 79 after forming the continuous conductive material layer 46L.

Referring to FIG. 9 , the continuous layer of conductive material 46L may be etched back and forth by an etching process without a substantial portion of each conductive layer 46 being etched. In one embodiment, an anisotropic or isotropic etch may be used to remove the material(s) of the continuous layer of conductive material 46L. For example, wet etch chemistries employing a mixture of hydrofluoric acid and nitric acid, a mixture of nitric acid and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, sulfuric acid, or aqua regia can be used to isotropically etch back a continuous conductive material Metallic material(s) of layer 46L. The continuous conductive material layer 46L is removed by an etching process from inside the backside trench 79 and from above the at least one contact level dielectric layer (71, 73). The conductive layer 46 remains in the volume of the backside recess 43 after the etching process.

Subsequently, sacrificial dielectric portion 616 may be removed by anisotropic etching. After removal of the sacrificial dielectric portion 616 , the top surface of the monocrystalline semiconductor material portion within the substrate semiconductor layer 10 is physically exposed at the bottom of each backside trench 79 .

Each conductive layer 46 may function as a combination of a plurality of control gate electrodes and a word line electrically connecting (ie, electrically shorting) the plurality of control gate electrodes. The plurality of control gate electrodes within each conductive layer 46 may include a control gate electrode located at the same level as the vertical memory device comprising the memory stack structure 55 . In other words, each conductive layer 46 may be a word line that serves as a common control gate electrode for multiple vertical memory devices.

Referring to Figure 10, a layer of insulating material is conformally deposited in the backside trench 79 and over at least one contact level dielectric layer (71, 73). The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and/or dielectric metal oxide. The thickness of the layer of insulating material is chosen such that after deposition of the layer of insulating material there is a backside cavity 79' within each backside trench 79.

The layer of insulating material is anisotropically etched to remove horizontal portions. Each remaining vertical portion of the layer of insulating material constitutes an insulating spacer 74 laterally surrounding the respective backside cavity 79'.

Referring to FIG. 11 , a selective epitaxy process is employed to form epitaxial pillar structures 61 ′ at the bottom of each backside cavity 79 ′. The epitaxial pillar structure 61' includes a semiconductor material, which may be a single semiconductor material (such as silicon or germanium), a compound semiconductor material (such as silicon germanium), or a combination thereof. In one embodiment, the epitaxial pillar structure 61' may comprise undoped semiconductor material or doped semiconductor material. As used herein, "undoped semiconductor material" refers to a semiconductor material deposited by a deposition process that does not provide any dopant gas into the process chamber. The undoped semiconductor material may be intrinsic, or may have a low level of autodoping, ie, doping by residual dopants provided by the substrate or process chamber during the deposition process. "Doped semiconductor material" refers to a semiconductor material having a high level of doping, eg, due to the presence of electrical dopants at an atomic concentration greater than 1.0 x ¹⁰¹⁶ / ^cm3 .

Selective epitaxy processes employ concurrent or alternate flows of at least one reactant gas and at least one etchant gas. The at least one reactant gas may comprise, for example, _SiH4 , _SiH2Cl2 , _SiHCl3 , _{SiCl4 , Si2H6} , _GeH4 , _Ge2H6 , any other known _organic or _inorganic precursor for semiconductor materials gas, or a combination thereof. An example of an etchant gas is HCl. The semiconductor surface and the dielectric surface provide different nucleation rates and thus different deposition rates for the deposition of semiconductor material derived from at least one reactant gas. In particular, semiconductor surfaces provide higher nucleation rates, and thus higher deposition rates, than dielectric surfaces. The etch rate of semiconductor materials is independent of the underlying surface.

The flow rates of at least one of the reactant gas and the etchant gas are selected such that the deposition rate is greater than the etch rate on the semiconductor surface and the deposition rate is less than the etch rate on the dielectric surface. Thus, deposition of semiconductor material initially only occurs on the physically exposed semiconductor surface of the substrate semiconductor layer 10 to form the in-process epitaxial pillar structure, while semiconductor material is not deposited on the insulating spacers 74 and the at least one contact-level dielectric layer ( 71, 73) on physically exposed dielectric surfaces. Once the in-process epitaxial column structure is formed, the deposition of semiconductor material occurs only on the surface of the in-process epitaxial column structure, and the semiconductor material is not deposited on the physically exposed portions of the insulating spacers 74 and at least one contact-level dielectric layer (71, 73). on the dielectric surface.

The selective deposition process continues until the height of the epitaxial column structure in the process reaches the target height, thereby completing the formation of the epitaxial pedestal structure 61'. Each epitaxial pedestal structure 61 ′ is formed in epitaxial alignment on the top surface of the portion of single crystal semiconductor material underlying the backside trench 79 and present in the upper portion of the substrate semiconductor layer 10 section. Each epitaxial pedestal structure 61' contacts the sidewall of the corresponding insulating spacer 74. The height of the top surface of the epitaxial pedestal structure 61' may be higher than the height of the bottom surface of the bottommost conductive layer 46S, and may be higher than the height of the top surface of the bottommost conductive layer 46S. Layer 46S may include the select gate electrodes of the source side select transistors, as described in more detail below. Alternatively, the height of the top surface of the epitaxial pedestal structure 61' may be at or above the height of the top surface of the second conductive layer 46 from the bottom (ie, the conductive layer 46 directly above the bottommost conductive layer 46S). . The height of the top surface of the epitaxial pedestal structure 61' may be higher than the height of the top surface of the epitaxial channel portion 11, if desired. The height of the top surface of the epitaxial channel portion is preferably lower than the lowest control gate electrode 46 in the stack. In other words, portion 11 may extend at the level of one or more select gate electrodes 46S, but is preferably located below control gate electrode 46 .

The semiconductor composition of the epitaxial pedestal structure 61' may be the same as or different from the semiconductor composition of the epitaxial channel portion 11. As used herein, the "semiconductor composition" of an element refers to the composition of the intrinsic composition of the semiconducting material of the element, which is the composition of the element minus all electrical dopants (i.e., p-type dopants and n-type dopants). Thus, the composition of the epitaxial pedestal structure 61' refers to the composition of all elements of the epitaxial pedestal structure 61' minus the electrical dopants in the epitaxial pedestal structure 61'.

In one embodiment, the semiconductor composition of the epitaxial pedestal structure 61' may be the same as that of the epitaxial channel portion 11. For example, the semiconductor composition of the epitaxial pedestal structure 61' and the epitaxial channel portion 11 may be 100% silicon. In another embodiment, the semiconductor composition of the epitaxial pedestal structure 61' may be different from the semiconductor composition of the epitaxial channel portion 11. For example, one of the epitaxial pedestal structure 61' and the epitaxial channel portion 11' may have a semiconductor composition of 100% silicon, and the other of the epitaxial pedestal structure 61' and the epitaxial channel portion 11' may have a silicon- Semiconducting component of germanium alloys.

In one embodiment, the semiconductor composition of the epitaxial pedestal structure 61' may be the same as that of the substrate semiconductor layer 10. For example, the semiconductor composition of the epitaxial pedestal structure 61' and the substrate semiconductor layer 10 may be 100% silicon. In another embodiment, the semiconductor composition of the epitaxial pedestal structure 61' may be different from that of the substrate semiconductor layer 10. For example, one of the epitaxial pedestal structure 61' and the substrate semiconductor layer 10 may have a semiconductor composition of 100% silicon, and the other of the epitaxial pedestal structure 61' and the substrate semiconductor layer 10 may have a silicon-germanium alloy semiconductor components.

12A and 12B, electrical dopants (ie, p-type dopants or n-type dopants s) can be introduced into the epitaxial pedestal structure 61', and optionally into the substrate semiconductor layer 10 In the portion below the backside trench 79 . Electrical dopants may be introduced by in-situ doping during selective epitaxy of the epitaxial pedestal structure 61 ′ (for example, by flowing a dopant gas simultaneously with flowing at least one semiconductor precursor gas). into the epitaxial pedestal structure 61 ′, and optionally into the underlying portion of the substrate semiconductor layer 10 . Alternatively, or additionally, electrical dopants may be introduced into the epitaxial pedestal structure 61 ′ by ion implantation after the formation of the epitaxial pedestal structure 61 ′, and optionally into the underside of the substrate semiconductor layer 10 in the section. The conductivity type of the electrical dopant introduced into the epitaxial pedestal structure 61' may be opposite to that of the substrate semiconductor layer 10 and the same as that of the drain region 63. For example, the substrate semiconductor layer 10 may have doping of a first conductivity type, and the drain region 63 and electrical dopants introduced into the epitaxial pedestal structure 61' may have a second conductivity type opposite to the first conductivity type doping. The first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa. The epitaxial channel portion 11 and the semiconductor channel (601, 602) may be undoped, or may have a doping of the first conductivity type.

The source region 61 is formed by introducing an electrical dopant of the second conductivity type into the epitaxial pedestal structure 61' and the underlying portion of the substrate semiconductor layer 10. Each source region 61 includes an entire continuous volume with doping of the second conductivity type and forms a p-n junction with a portion of the substrate semiconductor layer 10 doped with the first conductivity type. During the formation of each source region 61, the epitaxial pedestal structure 61' and the surface area of the portion of the monocrystalline semiconductor material of the substrate semiconductor layer 10 below the epitaxial pedestal structure 61' are treated with an electrical dopant of the second conductivity type doped, and becomes source region 61, which is a doped continuous portion of semiconductor material having a second conductivity type. In an alternative embodiment, the top of memory stack structure 55 may be exposed simultaneously with the top of epitaxial pedestal structure 61', for example by forming openings through layers 71 and 73. In this case, the source 61 and drain 63 regions may be formed simultaneously by implanting dopant ions of the second conductivity type (e.g. n-type) into the structures 61' and 55 during the same implantation step.

As shown in FIG. 12B , each source region 61 includes a substrate source portion 61A located in the substrate (for example, in the substrate semiconductor layer 10 ) and a substrate source portion 61A above and extending to the epitaxial pair. quasi-epitaxial pedestal source portion 61B. The substrate source portion 61A has the same semiconductor composition as the remaining portion of the substrate semiconductor layer 10 (ie, the portion of the substrate semiconductor layer 10 having doping of the first conductivity type). In particular, the substrate source portion 61A of the second conductivity type is epitaxially aligned with the horizontal channel portion HC of the first conductivity type, which is part of the channel of the field effect transistor. A field effect transistor (eg, a NAND memory device) includes a drain region 63, a semiconductor channel (601, 602) underlying and in contact with the drain region 63, an epitaxial channel in contact with the semiconductor channel (601, 602) portion 11, the horizontal channel portion HC in contact with the epitaxial channel portion 11, and the source region 61 in contact with the horizontal channel portion HC. The combination of the horizontal channel portion HC, the epitaxial channel portion 11, and the semiconductor channel (601, 602) collectively constitutes the channel of the field effect transistor. Each source region 61 is epitaxially aligned to the single crystal structure of the adjacent horizontal channel portion HC. Furthermore, each epitaxial channel portion 11 is epitaxially aligned to the adjacent horizontal channel portion HC. Portions HC and 11 form the channel of the source-side selection transistor Tr1 including the selection gate electrode 46S. The p-n junction between source region 61 and substrate semiconductor layer 10 may be vertically offset from interface 59C between substrate source portion 61A and epitaxial pedestal source portion 61B.

In the case of ion implantation, annealing is performed at elevated temperature to heal structural damage in source region 61 and by diffusing electrical dopants from interstitial sites to substitutional sites. site) to activate electrical dopants of the second conductivity type. Annealing can change the vertical doping profile because electrical dopants diffuse during annealing.

FIG. 12C illustrates various exemplary vertical doping profiles that may be used to form source regions 61 before and after annealing. In particular, a stepped or graded second conductivity type (eg n-type) dopant distribution can be achieved. For example, by in-situ doping of the silicon epitaxial pedestal structure 61' during epitaxial growth at relatively low temperatures, a stepped phosphorous doping profile can be achieved. If the growth temperature is increased, an intermediate distribution can be achieved due to the diffusion of phosphorus into the substrate semiconductor layer 10 during epitaxial growth. If phosphorus or arsenic ion implantation is used, the implanted phosphorus ions can diffuse deeper into the source region to achieve a graded dopant profile after the anneal.

In one embodiment, the epitaxial pedestal structure 61 ′ provides a more uniform threshold voltage (V _th ) distribution for the bottom select transistors (eg, Tr1 , Tr2 ) of each NAND string located in the corresponding memory opening. Figure 12D illustrates typical current-voltage ( _Icell - _Vg ) characteristics of a prior art NAND device lacking epitaxial pedestal structure 61'. As shown in the figure, the first bottom (source side) selection transistor Tr1 located closer to the source region 61 (for example, closer to the trench 79 ) has a higher voltage than the first bottom (source side) selection transistor Tr1 located farther from the source region 61 (for example, closer to the trench 79 ). The second bottom select transistor Tr2 further away from the trench 79) has a smaller effective gate length (L _eff ). Thus, the subthreshold swings of the first and second select transistors are different from each other, resulting in non-uniform performance of the NAND strings in the array.

Figure 12E illustrates the calculated current-voltage ( _Icell - _Vg ) characteristics of a NAND device comprising an embodiment of the present disclosure comprising an epitaxial pedestal structure 61'. As shown in this figure, the current-voltage (I _cell -V _g ) characteristics are improved compared to that of FIG. 12D . The gate length (L _g ) is better controlled and more uniform for both select transistors Tr1 and Tr2. Thus, the subthreshold characteristics and threshold voltages of the two select transistors are expected to be more uniform (ie, closer to each other) than in prior art devices.

Referring again to FIG. 12B, the threshold voltage of the selection transistor depends on the structure of the transistors in region A adjacent to source region 61/trench 79, and the configuration of transistors in region B adjacent to the bottom of memory opening 49. structure.

Without wishing to be bound by a particular theory, it is believed that when a gate-to-drain voltage (Vg˜Vdd) is applied, in region C in the epitaxial channel portion 11 in the memory opening 49, and directly at A strong inversion layer is formed in the horizontal channel portion HC below the selection gate electrode 46S. However, because the corners of the select gate electrodes do not have sufficient electric field to form a strong inversion layer, the insulating layer at the corners with the select gate electrode 46S (i.e., between the insulating spacers 74 and the select transistor gate dielectric A weak inversion layer is formed in regions A and B adjacent (ie, below) layer 12 . Thus, the select transistor threshold voltage is defined by the corner regions A and B of the select gate electrode.

As shown in FIG. 12B , in one embodiment of the present disclosure, source region 61 (ie, portion 61B) of the second conductivity type (eg, n-type) extends into region A. Referring to FIG. Therefore, there is no channel region of the second conductivity type (eg, p-type) under the insulating spacers 74 at the corners of the select gate electrode 46S in region A, and this region A does not affect the threshold of the select transistor Voltage.

In contrast, region B at the bottom of the memory opening is the same for all source side select transistors (eg Tr1 and Tr2 ) whether the select transistors are located closer or further from source region 61 . Thus, the dopant of the second conductivity type from the source region 61 preferably does not diffuse into the region B of each select transistor to leave a channel of the first conductivity type in region B. This makes a uniform area B a key factor for setting the threshold voltage of all source side select transistors. Thus, the epitaxial pedestal structure provides a more uniform effective gate length and improves the threshold voltage margin of the bottom (ie, source side) select transistors of the NAND device.

The above features provide an area overlap between the gate dielectric layer 12 and the source region 61 in the region B. Referring to FIG. Furthermore, the lateral extent of diffusion of dopants of the second conductivity type is controlled so that source region 61 does not extend to region B where horizontal channel portion HC contacts epitaxial channel portion 11 . The combination of the contours of the regions A and B provides a stable threshold voltage for the field effect transistors sharing the horizontal channel portion HC and the source region 61 .

Referring to Figure 13, at least one conductive material is deposited in the backside cavity 49'. The at least one conductive material may comprise a conductive metal liner material and a metal fill material. For example, the conductive metal liner material may comprise a metal nitride such as TiN, TaN, or WN, and the metal fill material may comprise a metal such as W, Cu, Al, Co, Ru, Mo, Pt, or alloys thereof. Excess portions of the at least one conductive material may be removed from above the top surface of the at least one contact-level dielectric layer (71, 73). Each remaining portion of at least one conductive material constitutes a backside contact via structure 76, which may be a source contact via structure.

14A and 14B, a photoresist layer (not shown) may be applied over the topmost layer (which may be, for example, at least one contact-level dielectric layer (71, 73)) of the first exemplary structure, And is photolithographically patterned to form various openings in the device region 100 , the peripheral device region 200 , and the contact region 300 . The locations and shapes of the various openings are selected to correspond to the electrical nodes of the various devices to be electrically contacted by the contact via structures. In one embodiment, a single photoresist layer can be used to pattern all the openings corresponding to the contact via cavities to be formed, and at least An anisotropic etch process to simultaneously form all contact via cavities. In another embodiment, multiple photoresist layers may be used in combination with multiple anisotropic etch processes to form different sets of contact via cavities with different patterns of openings in the photoresist layers. . The photoresist layer(s) may be removed after a corresponding anisotropic etch process which transfers the pattern in the respective photoresist layer through the underlying dielectric material layer and to the top surface of the corresponding conductive structure.

In an illustrative example, drain contact via cavities may be formed over each memory stack structure 55 in device region 100 such that the top surface of drain region 63 is at the bottom of each drain contact via cavity physical exposure. The wordline contact via cavities may be formed to the stepped surfaces of the alternating stacks ( 32 , 46 ) such that the top surface of conductive layer 46 is physically exposed at the bottom of each wordline contact via cavity in contact region 300 . A device contact via cavity may be formed to each electrical node of the peripheral device 210 to be contacted by the contact via structure in the peripheral device region.

The various via cavities can be filled with at least one conductive material, which can be a combination of a conductive metal liner material (such as TiN, TaN, or WN) and a metal fill material (such as W, Cu, or Al). Excess portions of the at least one conductive material may be removed from above the at least one contact-level dielectric layer (71, 73) by a planarization process, which may include, for example, chemical mechanical planarization (CMP) and/or recess etching. Drain contact via structures 88 may be formed on the corresponding drain regions 63 . Word line contact via structures 84 may be formed on corresponding conductive layers 46 . Peripheral device contact via structures 8P may be formed on corresponding nodes of the peripheral device 210 . Additional metal interconnect structures (not shown) and layers of interlevel dielectric material (not shown) may be formed over the first exemplary structure to provide electrical routing between the various contact via structures.

The first exemplary structure may include a three-dimensional memory device. The three-dimensional memory device may comprise alternating stacks of insulating layers 32 and conductive layers 46 on substrate 10, and a memory stack structure 55 extending through the alternating stacks (32, 46). The three-dimensional memory device includes a source region 61 including a substrate source portion 61A in the substrate, and a substrate (for example, in the substrate semiconductor layer 10 ) above and with the source portion 61A. Epitaxially aligned epitaxial pedestal source portion 61B.

Backside trenches extend through the alternating stacks (32, 46). Insulating spacers 74 are located in the backside trenches, and contact the sidewall surfaces of the epitaxial pedestal source portion 61B. The bottom surface of insulating spacer 74 contacts the top surface of substrate source portion 61A, and portion 61A extends under spacer 74 to overlap the bottom of select gate electrode 46S. However, portion 61A does not extend to the corner of select gate electrode 46S adjacent to memory stack structure 55 such that the channel of the first conductivity type is located below the corner of select gate electrode 46S adjacent to layer 116 . Horizontal interface 59C between epitaxial pedestal source portion 61B and substrate source portion 61A may be coplanar with the bottom surface of insulating spacer 74 . In one embodiment, the horizontal interface 59C between the epitaxial pedestal source portion 61B and the substrate source portion 61A may lie in a plane at or below the topmost surface of the substrate including the substrate semiconductor layer 10 .

In one embodiment, epitaxial pedestal source portion 61B may have the same or different semiconductor composition as that of substrate source portion 61A. Backside contact via structures 76 may be laterally surrounded by insulating spacers 74 and may contact source regions 61 . In one embodiment, the backside contact via structure 76 may include a metal pad that contacts the top surface of the epitaxial pedestal source portion 61B. In one embodiment, the top surface of epitaxial pedestal source portion 61B may lie above a horizontal plane containing the bottom surface of bottommost conductive layer 46S (eg, select gate electrode) within the alternating stack ( 32 , 46 ). In another embodiment, the top surface of epitaxial pedestal source portion 61B may be positioned level with or below a horizontal plane containing the bottom surface of bottommost conductive layer 46S (eg, select gate electrode).

Epitaxial channel portion 11 may contact substrate 10 . Each epitaxial channel portion 11 may underlie a corresponding memory stack structure 55 . In one embodiment, epitaxial channel portion 11 may have the same semiconductor composition but a different conductivity type as epitaxial pedestal source portion 61B. In another embodiment, epitaxial channel portion 11 may have a different semiconductor composition than epitaxial pedestal source portion 61B. The p-n junction is located between the source region 61 and the doped semiconductor channel portion HC within the substrate (eg, in the substrate semiconductor layer 10 ). The p-n junction may be spatially (ie, vertically and/or horizontally) offset from the interface between substrate source portion 61A and epitaxial pedestal source portion 61B.

Referring to FIGS. 15A and 15B , a second exemplary structure can be derived from the in-process exemplary structure of FIGS. 6A and 6B . 15A and 15B illustrate the structure of the second embodiment after forming the insulating cap layer 70 by forming the memory opening 49 and the backside trench 79 through the alternating stack (32, 42). In the second embodiment, the epitaxial pedestal structure is formed simultaneously with the epitaxial channel structure and before forming the gate electrodes 46 , 46S and insulating spacers 74 . In the second embodiment, the memory opening 49 and the backside trench 79 can be formed simultaneously by using the same photolithographic patterning process and anisotropic etching. Both the memory opening 49 and the backside trench 79 may be recessed into the substrate semiconductor layer 10 . In this case, backside trench 79 and memory opening 49 may be formed during the same anisotropic etch process. The top surface of the monocrystalline semiconductor material portion in the substrate semiconductor layer 10 is physically exposed at the bottom of each backside trench 79 . In another embodiment, memory opening 49 and backside trench 79 may be formed in different process steps, each employing a combination of photolithographic patterning steps and anisotropic etching. In this case, the formation of the backside trench 79 may be performed before or after forming the memory opening 49 .

Referring to FIG. 16, a selective epitaxial process may be performed to form the epitaxial channel portion 11 and the epitaxial column structure 161 in the same growth step. If the memory opening has a narrower width than the backside trench 79 , the epitaxial channel portion 11 may be higher than the epitaxial pillar structure 161 . Each epitaxial channel portion 11 is formed at the bottom of the memory opening 49 . A memory cavity 49' is present above each epitaxial channel portion 11. Each epitaxial pedestal structure 161 is formed at the bottom of the backside trench 79 . A backside cavity 179 exists above each epitaxial pedestal structure 161 . Each epitaxial pedestal structure 161 has the same composition as the epitaxial channel portion 11 .

The selective epitaxial process used to form the epitaxial channel portion 11 and the epitaxial column structure 161 may be the same as the selective epitaxial process used to form the epitaxial channel portion 11 of the first embodiment. Thus, the composition of the epitaxial channel portion 11 and the epitaxial pedestal structure 161 may be the same as that of the epitaxial channel portion 11 of the first embodiment. Thus, the formed epitaxial channel portion 11 and epitaxial pedestal structure 161 may be undoped, or may have a slight doping of the first conductivity type (for example, about 1.0×10 ¹⁶ /cm ³ to 1.0×10 ¹⁷ /cm ³ dopant concentration, although higher or lower concentrations can also be used). The duration of the selective epitaxy process may be chosen such that the topmost surface of the epitaxial channel portion 11 is formed at a level of the insulating layer 32 directly at the most on the top layer of sacrificial material and below the layer of sacrificial material to be replaced with the control gate electrode. Each of the epitaxial pedestal structure 161 and the epitaxial channel portion 11 may be formed at the top surface of the single crystal semiconductor material portion that is the topmost portion of the substrate within the substrate semiconductor layer 10 in epitaxial alignment.

Referring to FIG. 17, the process steps of FIGS. 2C-2H are performed to form a memory stack structure 55 within each memory cavity 49'. Each memory stack structure 55 is formed over a corresponding epitaxial channel portion 11 . A dummy trench-fill structure 155 is formed within each backside cavity 179 concurrently with the formation of the memory stack structure 55 . Each feature within dummy trench-fill structure 155 includes the same material as a corresponding corresponding feature within one memory stack structure 55 . For example, each dummy trench filling structure 155 may include a dummy memory film 150, a first dummy semiconductor channel 611, and a second dummy semiconductor channel 612, and the dummy memory film 150 has the same structure as the memory film 50 in the memory stack structure 55 The same composition and thickness, the first dummy semiconductor channel 611 has the same composition and thickness as the first semiconductor channel 601 in the memory stack structure 55, and the second dummy semiconductor channel 612 has the same composition and thickness as the memory stack structure The second semiconductor channel 602 in 55 has the same composition and thickness. In addition, the dummy dielectric core 162 within each backside trench can have the same composition as the dielectric core 62 in the memory opening, and each dummy drain region 163 above the dummy dielectric core 162 can have the same composition as the dielectric core 62 in the memory opening. The same composition of the drain region 63.

Referring to FIG. 18 , the process steps of FIGS. 4 and 5 may be performed to form reverse step dielectric material portion 65 , at least one contact level dielectric layer ( 71 , 73 ), and dielectric support pillar 7P.

Referring to FIG. 19 , openings may be formed over each dummy trench-fill structure 155, for example, by applying a photoresist layer over the second exemplary structure, patterning the photoresist layer to form over the The opening above the dummy trench-fill structure 155, and the portion of at least one contact-level dielectric layer (71, 73) above the dummy trench-fill structure 155 is anisotropically etched. Subsequently, the dummy trench-fill structure 155 may be removed by a combination of etching processes (which may include at least one anisotropic etching process and/or at least one isotropic etching process) selective to the epitaxial pedestal structure 161 . The photoresist layer may be removed in parallel during one etch process, or may be removed after the anisotropic etch that physically exposes the top surface of the dummy trench-fill structure 155 . A backside cavity 179 is formed within each backside trench. The top surface of each epitaxial pedestal structure 161 is physically exposed at the bottom of each backside trench 179 .

Subsequently, the top surface of the epitaxial pedestal structure 161 may be recessed below a horizontal plane containing the bottom surface of the bottommost sacrificial material layer 42S. The recessing of the top surface of the epitaxial pedestal structure 161 may be performed by isotropic etching or anisotropic etching.

Referring to FIG. 20 , the process steps of FIGS. 7-10 may be performed to replace layers 42 , 42S with gate electrodes 46 , 46S and to form insulating spacers 74 within each backside trench 79 . The bottommost surface of each insulating spacer 74 is formed on the top surface of the epitaxial pedestal structure 161 within the backside trench 79 .

Referring to FIG. 21 , dopants of the second conductivity type are implanted by ion implantation into each epitaxial pedestal structure 161 , and optionally into the underlying monocrystalline semiconductor material portion of the substrate semiconductor layer 10 . Under each backside trench 79', the epitaxial pedestal structure 161 and the underlying epitaxial pedestal structure 161 (of the substrate semiconductor layer 10 ) of the surface area of the monocrystalline semiconductor material portion, thereby forming the source region 61 .

Referring to FIG. 22A and FIG. 22B, the process steps of FIG. 13, FIG. 14A, and FIG. 14B are performed to form a backside contact via structure 76, which includes a metal liner/barrier (for example, TiN or WN ) layer 76A and metal fill (eg, tungsten) layer 76B, and various additional contact via structures (88, 84, 8P).

Each source region 61 includes a substrate source portion 61A located in the substrate (eg, in the substrate semiconductor layer 10 ), and an epitaxial pedestal overlying the substrate source portion 61A and aligned with the epitaxy. source portion 61B. The substrate source portion 61A has the same structure as the rest of the substrate semiconductor layer 10 (that is, the portion of the substrate semiconductor layer 10 having doping of the first conductivity type (for example, p-type single crystal silicon doped with boron)). semiconductor composition but the opposite conductivity type (for example, n-type single crystal silicon doped with phosphorus or arsenic). In particular, substrate source portion 61A is epitaxially aligned with horizontal channel portion HC, which is part of the channel of a field effect transistor comprising drain region 63, in the drain region 63 below and in contact with the semiconductor channel (601, 602), the epitaxial channel portion 11 in contact with the semiconductor channel (601, 602), the horizontal channel portion HC in contact with the epitaxial channel portion 11, and the horizontal The channel portion HC contacts the source region 61 . The horizontal channel portion HC, the epitaxial channel portion 11, and the semiconductor channel (601, 602) collectively constitute the channel of the field effect transistor. Each source region 61 is epitaxially aligned to the single crystal structure of the adjacent horizontal channel portion HC. Furthermore, each epitaxial channel portion 11 is epitaxially aligned to the adjacent horizontal channel portion HC. The p-n junction 59E between the source region 61 and the substrate semiconductor layer 10 may be vertically offset from the interface 59C between the substrate source portion 61A and the epitaxial pedestal source portion 61B.

A second exemplary structure may include a three-dimensional memory device. A three-dimensional memory device may comprise alternating stacks of insulating layers 32 and conductive layers 46 on substrate 10, and a memory stack structure 55 extending through the alternating stacks (32, 46). The three-dimensional memory device comprises a source region 61 comprising a substrate source portion 61A in the substrate, and an epitaxial pedestal source portion 61B above the substrate source portion 61A which is epitaxially aligned.

Backside trenches extend through the alternating stacks (32, 46). Insulating spacers 74 are located in the backside trenches, and contact the sidewall surfaces of the epitaxial pedestal source portion 61B. The bottom surface of the insulating spacer 74 contacts the surface of the substrate source portion 61A. Horizontal interface 59C between epitaxial pedestal source portion 61B and substrate source portion 61A may be coplanar with the bottom surface of insulating spacer 74 . In one embodiment, the horizontal interface between the epitaxial pedestal source portion 61B and the substrate source portion 61A may lie in a plane below the topmost surface of the substrate containing the substrate semiconductor layer 10 .

In one embodiment, epitaxial pedestal source portion 61B may have the same or different semiconductor composition as that of substrate source portion 61A. Backside contact via structures 76 may be laterally surrounded by insulating spacers 74 and may contact source regions 61 . In one embodiment, the backside contact via structure 76 may include a metal pad contacting the top surface of the epitaxial pedestal source portion 61B. In one embodiment, the top surface of the epitaxial pedestal source portion 61B may be at the level of the bottom surface of the bottommost conductive layer 46S (eg, source side select gate electrode) comprising the alternating stack (32, 46). below the plane.

Epitaxial channel portion 11 may contact substrate 10 . Each epitaxial channel portion 11 may underlie a corresponding memory stack structure 55 . In one embodiment, epitaxial channel portion 11 may have the same semiconductor composition (eg, p-type or intrinsic monocrystalline silicon) as epitaxial pedestal source portion 61B (eg, n-type monocrystalline silicon) but opposite conductivity type. In one embodiment, epitaxial channel portion 11 may have a different semiconductor composition than epitaxial pedestal source portion 61B. The p-n junction is located between the source region 61 and the doped semiconductor channel portion HC within the substrate (eg, within the substrate semiconductor layer 10 ). The p-n junction may be spatially offset from the interface between substrate source portion 61A and epitaxial pedestal source portion 61B.

In one embodiment, the device in the first exemplary structure or the second exemplary structure may comprise a vertical NAND device located in the device region 100, and at least one of the conductive layers 46, 46S in the stack (32, 46) One may include or may be electrically connected to the word line and source side select gate electrodes of the NAND device, respectively. A drain side select gate electrode may be located at the top of the stack. The device region 100 may include a plurality of semiconductor channels (601, 602). At least one end portion of each of the plurality of semiconductor channels (601, 602) extends substantially perpendicular to the top surface of the semiconductor substrate. Device region 100 also includes a plurality of charge storage regions within each memory layer 50 . Each charge storage region is located adjacent a respective one of the plurality of semiconductor channels (601, 602). The device region 100 also includes a plurality of control gate electrodes having a stripe shape extending substantially parallel to the top surface of the substrate (eg, of the substrate semiconductor layer 10 ). The plurality of control gate electrodes includes at least a first control gate electrode in a first device level and a second control gate electrode in a second device level. The plurality of conductive layers 46 in the stack (32, 46) may be in electrical contact with or may include a plurality of control gate electrodes, and extend from the device region 100 to a plurality of conductive contact via structures. contact area 300 .

Where the first exemplary structure or the second exemplary structure comprises a three-dimensional NAND device, a stack (32, 46) of alternating pluralities of word lines 46 and insulating layers 32 may be located over a semiconductor substrate. Each of the word lines 46 and the insulating layer 32 are located at different levels vertically spaced by different distances from the top surface of the semiconductor substrate. An array of memory stack structures 55 is embedded within the stack (32, 46). Each memory stack structure 55 includes a semiconductor channel (601, 602) and at least one charge storage region located adjacent to the semiconductor channel (601, 602). At least one end portion of the semiconductor channel (601, 602) extends through the stack (32, 46) substantially perpendicular to the top surface of the semiconductor substrate.

While the foregoing has referred to certain preferred embodiments, it should be understood that the disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present disclosure. Where the present disclosure illustrates an embodiment employing a particular structure and/or configuration, it should be understood that the present disclosure may be practiced with any other compatible structure and/or configuration that is functionally equivalent, provided that such substitutions are not expressly prohibited or known to be impossible by a person of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims (24)

1. a kind of three dimensional memory device, including：

Insulating layer and conductive layer are alternately stacked body, and are located at substrate；

Memory stacking body structure, the memory stacking body structure, which extends through, described is alternately stacked body；And

Source area, the source area include the substrate source part being located in the substrate, and in the substrate source part Above and the extension pedestal source electrode portion that is aligned with the substrate source portion of epi.

2. three dimensional memory device according to claim 1, further includes：

Dorsal part groove, the dorsal part groove, which extends through, described is alternately stacked body；

Insulation gap body, the insulation gap body are located in the dorsal part groove and contact the extension pedestal source electrode portion Sidewall surfaces；And

Source contact through-hole structure, the source contact through-hole structure by the insulation gap body transversely about and contact institute State source area.

3. three dimensional memory device according to claim 2, wherein the basal surface of the insulation gap body contacts the lining The surface of bottom source electrode portion.

4. three dimensional memory device according to claim 2, wherein the epitaxial base seat source electrode portion and the substrate source The basal surface of horizontal interface and the insulation gap body between the part of pole is coplanar.

5. three dimensional memory device according to claim 4, wherein the epitaxial base seat source electrode portion and the substrate source The horizontal interface between the part of pole is located in the plane most below top surface of the substrate.

6. three dimensional memory device according to claim 2, wherein the epitaxial base seat source electrode portion includes monocrystalline silicon, and And the substrate includes silicon single crystal wafer or monocrystalline silicon layer containing the substrate source part.

7. three dimensional memory device according to claim 2, wherein：

The p-n junction between doped semiconductor channel portion in the source area and the substrate from the substrate source part with Interface between the extension pedestal source electrode portion is spatially offset；

The basal surface of the insulation gap body contacts the top surface of the substrate source part；

The substrate source part extends below the insulation gap body, to be selected with the source side being alternately stacked in body The bottom for selecting gate electrode is overlapping；And

The substrate source part is not extending to the source side selection gate electrode with the memory stacking body structure phase Adjacent corner.

8. three dimensional memory device according to claim 1, wherein the top surface of the epitaxial base seat source electrode portion is located at Above or below the source side selection gate electrode being alternately stacked in body.

9. three dimensional memory device according to claim 1, further includes epi channels part, the epi channels part connects The substrate is touched, and in corresponding memory stacking body structure in the following, and with identical with the extension pedestal source electrode portion Semiconductor component.

10. three dimensional memory device according to claim 1, wherein in the memory stacking body structure each from Inner side includes to outside：

Semiconductor channel；

Tunnel dielectric layer, the tunnel dielectric layer is transversely about the semiconductor channel；And

Charge storaging area, the charge storaging area is transversely about the tunnel dielectric layer.

11. three dimensional memory device according to claim 1, wherein：

The three dimensional memory device includes the vertical nand device being formed in device region；

The conductive layer includes or is electrically connected to the corresponding wordline of the NAND device；

The device region includes：

Multiple semiconductor channels, wherein at least one end sections of each in the multiple semiconductor channel substantially hang down Directly extend in the top surface of the substrate；

Multiple charge storaging areas, each charge storaging area is near one corresponding with the multiple semiconductor channel； And

There is the top surface substantially parallel to the substrate to extend for multiple control gate electrodes, the multiple control gate electrode Bar shaped；

The multiple control gate electrode is including at least the first control gate electrode being located in the first device level and positioned at second The second control gate electrode in device level；And

The conductive layer in the stacked body makes electrical contact with the multiple control gate electrode, and extends from the device region To contact zone, the contact zone is connected comprising the multiple conductive through hole；And

The substrate includes silicon substrate, and the silicon substrate contains the drive circuit of the NAND device.

12. a kind of method for manufacturing three dimensional memory device, including：

Formation is alternately stacked body, and the body that is alternately stacked includes insulating layer on the single-crystal semiconductor material part of substrate and sacrificial Domestic animal material layer；

Form memory stacking body structure, the memory stacking body structure, which extends through, described is alternately stacked body；

Dorsal part groove is formed through the body that is alternately stacked, wherein the top surface of the single-crystal semiconductor material part is in the back of the body The bottom physics exposure of side trench；

Landform is directed on the top surface of the single-crystal semiconductor material part and with the single-crystal semiconductor material portion of epi Into extension base construction；And

By adulterate the extension base construction and the single-crystal semiconductor material part below the extension base construction Surface region form source area, wherein the step of doping occurs forming step phase of the extension base construction Between, after the step of forming the extension base construction, or during the step of forming the extension base construction and in shape The step of extension base construction after.

13. according to the method for claim 12, wherein the epitaxial base holder structure includes being formed by selective epitaxial process Monocrystal silicon structure.

14. according to the method for claim 12, further include：

It is recessed by removing the sacrificial material layer to form dorsal part；

Conductive layer is formed wherein by depositing at least one conductive material in dorsal part depression；And

Insulation gap body is formed on the side wall of the dorsal part groove.

15. the method according to claim 11, wherein：

The extension base construction is formed on the side wall of the insulation gap body；

The dorsal part depression is formed before the extension base construction is formed；And

The memory stacking body structure is formed before the backside contact groove is formed.

16. the method according to claim 11, wherein：

The most basal surface of the insulation gap body is formed on the top surface of the extension base construction；

The dorsal part depression is formed after the extension base construction is formed；And

The memory stacking body structure is formed after the backside contact groove is formed.

17. according to the method for claim 14, wherein after the insulation gap body is formed, by using electrical dopant Ion implanting, to adulterate the surface portion of the extension base construction and the single-crystal semiconductor material part.

18. the method according to claim 11, wherein：

The doping surfaces region of the single-crystal semiconductor material part includes substrate source part；

The basal surface of the insulation gap body contacts the top surface of the substrate source part；

The substrate source part extends under the insulation gap body, to be selected with the source side being alternately stacked in body The bottom of gate electrode is overlapping；And

The substrate source part is not extending to the source side selection gate electrode with the memory stacking body structure phase Adjacent corner.

19. according to the method for claim 14, further include：

Memory opening is formed through the body that is alternately stacked；And

Epi channels part is formed at the bottom of each memory opening and directly on the surface of the substrate, wherein described Memory stacking body structure is formed on corresponding epi channels part.

20. according to the method for claim 19, wherein forming the notopleural suture after the epi channels part is formed Groove and the extension base construction.

21. the method according to claim 11, wherein：

The dorsal part groove and the memory opening are formed during identical anisotropic etching process；And

The epi channels part is formed during the growth step identical with the extension base construction.

22. according to the method for claim 21, further include：

While with forming the memory stacking body structure, illusory trench fill knot is formed on the extension base construction Structure, wherein each component in the illusory trench fill structure includes and a storage in the memory stacking body structure The identical material of corresponding corresponding component in device stacked body structure；And

After the memory stacking body structure is formed, the illusory trench fill structure is removed out of described dorsal part groove, The top surface physics exposure of wherein described epitaxial base holder structure.

23. according to the method for claim 12, wherein each in the memory stacking body structure is from inboard to outer Side includes：

Semiconductor channel；

Tunnel dielectric layer, the tunnel dielectric layer is transversely about the semiconductor channel；And

Charge storaging area, the charge storaging area is transversely about the tunnel dielectric layer.

24. the method according to claim 11, wherein：

The three dimensional memory device is included in the vertical nand device formed in device region；

The conductive layer includes or is electrically connected to the corresponding wordline of the NAND device；

The device region includes：

Multiple semiconductor channels, wherein at least one end sections of each in the multiple semiconductor channel substantially hang down Directly extend in the top surface of the substrate；

Multiple charge storaging areas, each charge storaging area is near one corresponding with the multiple semiconductor channel； And

There is the top surface substantially parallel to the substrate to extend for multiple control gate electrodes, the multiple control gate electrode Bar shaped；

The multiple control gate electrode is including at least the first control gate electrode being located in the first device level and positioned at second The second control gate electrode in device level；And

Conductive layer in the stacked body makes electrical contact with the multiple control gate electrode, and extends to and connect from the device region Area is touched, the contact zone is connected comprising the multiple conductive through hole；And

The substrate includes silicon substrate, and the silicon substrate contains the drive circuit of the NAND device.