CN107993952B - Alignment measuring method of gate line - Google Patents
Alignment measuring method of gate line Download PDFInfo
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- CN107993952B CN107993952B CN201711182124.6A CN201711182124A CN107993952B CN 107993952 B CN107993952 B CN 107993952B CN 201711182124 A CN201711182124 A CN 201711182124A CN 107993952 B CN107993952 B CN 107993952B
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- gate line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The invention discloses an alignment measurement method of a gate line, and belongs to the technical field of semiconductors. The method comprises the following steps: providing a three-dimensional memory sample to be formed with a gate line; grinding the three-dimensional memory sample to the polysilicon plug presenting the channel hole; etching back and removing part of the dielectric layer to leak out the corresponding part of the channel hole; forming a hard mask layer on the residual dielectric layer and the leaked channel hole, wherein the region of the hard mask layer corresponding to the channel hole is of a protruding structure; spin-coating a photoresist layer on the hard mask layer, and forming a gate line opening pattern on the photoresist layer; alignment measurements are made between the gate line opening pattern and the bump structures. According to the invention, alignment measurement between the gate line opening pattern and the protruding structure is completed, namely alignment measurement between the gate line and the channel hole is completed; alignment measurement between the gate line and the channel hole is not needed after the gate line groove is etched, so that the alignment measurement efficiency is improved, and the wafer damage probability is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an alignment measurement method of a gate line.
Background
Flash memory is a non-volatile memory, and is a special structure of electrically erasable and programmable read-only memory, and nowadays, through the development period of planar flash memory, the flash memory has entered the development trend of three-dimensional flash memory, and its main feature is to convert the planar structure into a three-dimensional structure.
Due to the complexity of the three-dimensional memory structure, in the manufacturing process of the three-dimensional memory, an alignment measurement (OVL) operation between structures is indispensable, and an alignment measurement between a Gate Line (Gate Line) and a Channel Hole (Channel Hole) is one of the essential. The conventional alignment measurement method between the gate line and the channel hole, as shown in fig. 1 to 4, generally mainly includes: 1) grinding the three-dimensional memory sample to the polysilicon plug presenting the channel hole; 2) forming a hard mask layer on the ground three-dimensional memory sample; 3) spin-coating a photoresist layer on the hard mask layer, and performing graphical processing to form a gate line opening graph; 4) and etching along the gate line opening pattern to form a gate line groove, and performing alignment measurement between the gate line groove and the channel hole. In the method, because the hard mask layer formed in the step 2) is very thick, the difficulty is increased when alignment measurement is carried out between the gate line groove and the channel hole in the step 4); in the existing processing mode, usually, in the process of etching the gate line groove in step 4), only the uppermost wafer is etched to form a part of the gate line groove, then alignment measurement between the part of the gate line groove and the channel hole is performed, when deviation occurs in the alignment measurement result, adjustment is performed until a satisfactory alignment measurement result is obtained, and then etching is performed on other wafers to obtain a complete gate line groove; during the adjustment process, other wafers can only wait for the result without any treatment; the process is complicated and inefficient, and when the alignment test is out of control, the etched wafer is damaged and cannot be used.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides an alignment measurement method of a gate line, which comprises the following steps:
providing a three-dimensional memory sample to be formed with a gate line;
grinding the three-dimensional memory sample to a polysilicon plug presenting a channel hole;
etching back and removing part of the dielectric layer to leak out the corresponding part of the channel hole;
forming a hard mask layer on the residual dielectric layer and the leaked channel hole, wherein the hard mask layer and the area corresponding to the channel hole are in a protruding structure;
spin-coating a photoresist layer on the hard mask layer, and forming a gate line opening pattern on the photoresist layer;
alignment measurements are performed between the gate line opening patterns and the protrusion structures.
Optionally, the grinding the three-dimensional memory sample to the polysilicon plug presenting the channel hole specifically includes: and grinding the silicon nitride layer on the dielectric layer and the buffer area of the channel hole in the three-dimensional memory sample by adopting a chemical mechanical grinding process until the polysilicon plug of the channel hole is formed.
Optionally, the etching back and removing a part of the dielectric layer to expose a corresponding part of the channel hole specifically includes: and etching back and removing part of the dielectric layer by adopting a dry etching process to leak out the corresponding part of the channel hole.
Optionally, the forming a hard mask layer on the remaining dielectric layer and the leaked channel hole specifically includes: and depositing an oxide on the residual dielectric layer and the leaked channel hole by adopting a chemical vapor deposition method to form an oxide layer, depositing carbon on the oxide layer to form a carbon layer, and depositing silicon oxynitride on the carbon layer to form a hard mask layer.
Optionally, the bottom end of the protruding structure is flush with the upper surface of the channel hole.
Optionally, the spin-coating a photoresist layer on the hard mask layer and forming a gate line opening pattern on the photoresist layer specifically includes: and spin-coating photoresist on the hard mask layer to form a photoresist layer, positioning and aligning a gate line opening pattern contained in the mask plate with the photoresist layer, and forming the gate line opening pattern on the photoresist layer through exposure and development processes.
Optionally, the alignment measurement is performed between the gate line opening pattern and the protrusion structure, specifically: and performing alignment measurement on one side wall of the gate opening pattern and the bottom end of the convex structure adjacent to the side, and performing alignment measurement on the other side wall of the gate opening pattern and the bottom end of the convex structure adjacent to the side.
The invention has the advantages that:
in the invention, after a polysilicon plug of a channel hole of a three-dimensional memory sample is ground, a hard mask layer with a raised structure in an area corresponding to the channel hole is formed by back-etching the dielectric layer, so that alignment measurement between an opening pattern of a gate line and the raised structure is finished, namely alignment measurement between the gate line and the channel hole is finished; alignment measurement between the gate line and the channel hole is not needed after the gate line groove is etched, so that the alignment measurement efficiency is improved, and the wafer damage probability is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 to 4 are schematic structural changes in a conventional alignment measurement method between a gate line and a trench hole;
FIG. 5 is a flow chart of a gate line alignment measurement method provided by the present invention;
fig. 6 to 9 are schematic structural changes in the gate line alignment measurement method according to the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
According to an embodiment of the present invention, there is provided a method of measuring alignment of a gate line, as shown in fig. 5 to 9, including:
providing a three-dimensional memory sample to be formed with a gate line;
grinding the three-dimensional memory sample to a polysilicon Plug (Plug Poly) exhibiting a channel hole;
etching back and removing part of the dielectric layer to leak out the corresponding part of the Channel Hole (Channel Hole);
forming a Hard Mask layer (HM) on the residual dielectric layer and the leaked channel hole, wherein the area of the Hard Mask layer corresponding to the channel hole is of a protruding structure;
spin-coating a photoresist layer on the hard mask layer, and forming a gate line opening pattern on the photoresist layer;
an alignment measurement (OVL) is performed between the gate line opening pattern and the bump structure.
According to an embodiment of the present invention, a three-dimensional memory sample to be formed with a gate line is provided, which specifically includes: the semiconductor device includes a substrate, a stacked structure formed on the substrate, a dielectric layer formed on the stacked structure, a silicon nitride layer (not shown) formed on the dielectric layer, and a channel hole formed in the dielectric layer and the stacked structure.
According to an embodiment of the present invention, grinding a three-dimensional memory sample to a polysilicon plug exhibiting a channel hole comprises: and (2) grinding a silicon nitride layer positioned on the dielectric layer and a Buffer region (CH Buffer for short) of the Channel hole in the three-dimensional memory sample by adopting a Chemical Mechanical Polishing (CMP) process to form a polysilicon plug of the Channel hole.
According to the embodiment of the invention, the etching back and the removal of part of the dielectric layer to leak out the corresponding part of the channel hole are as follows: and etching back and removing part of the dielectric layer by adopting a Dry etching (Dry Etch) process, and leaking out the corresponding part of the channel hole.
According to the embodiment of the invention, the forming of the hard mask layer on the residual dielectric layer and the leaked channel hole specifically comprises the following steps: and depositing an oxide on the residual dielectric layer and the leaked channel hole by adopting a chemical vapor deposition method to form an oxide layer, depositing carbon (C) on the oxide layer to form a carbon layer, and depositing silicon oxynitride (SiON) on the carbon layer to form a hard mask layer.
The silicon oxynitride layer is also called a dielectric antireflective coating (DARC).
According to an embodiment of the present invention, the bottom end of the bump structure is flush with the upper surface of the channel hole.
According to the embodiment of the invention, a photoresist layer is spin-coated on the hard mask layer, and a gate line opening pattern is formed on the photoresist layer, which specifically comprises: and spin-coating photoresist on the hard mask layer to form a photoresist layer, aligning the gate line opening pattern contained in the mask plate with the photoresist layer, and forming the gate line opening pattern on the photoresist layer through exposure and development processes.
According to the embodiment of the invention, alignment measurement is carried out between the gate line opening pattern and the convex structure, and the alignment measurement is specifically as follows: and performing alignment measurement on one side wall of the gate opening pattern and the bottom end of the convex structure adjacent to the side, and performing alignment measurement on the other side wall of the gate opening pattern and the bottom end of the convex structure adjacent to the side.
According to the invention, by back-etching the dielectric layer and forming the hard mask layer with the protruding structure in the area corresponding to the channel hole, alignment measurement between the gate line and the channel hole is not required to be carried out after etching the gate line groove, and the wafer is not required to be separately processed; but the alignment measurement between the gate line opening pattern and the bump structure, that is, the alignment measurement between the gate line and the channel hole is completed; not only the efficiency of alignment measurement is improved, but also the probability of wafer damage is reduced.
According to the embodiment of the present invention, after the alignment measurement between the gate line opening pattern and the protrusion structure is completed, the method further includes: and etching along the Gate Line opening pattern to form a Gate Line groove, and depositing metal in the Gate Line groove to form a Gate Line (Gate Line).
In the invention, after a polysilicon plug of a channel hole of a three-dimensional memory sample is ground, a hard mask layer with a raised structure in an area corresponding to the channel hole is formed by back-etching the dielectric layer, so that alignment measurement between an opening pattern of a gate line and the raised structure is finished, namely alignment measurement between the gate line and the channel hole is finished; alignment measurement between the gate line and the channel hole is not needed after the gate line groove is etched, so that the alignment measurement efficiency is improved, and the wafer damage probability is reduced.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A method for measuring alignment of a gate line, comprising:
providing a three-dimensional memory sample to be formed with a gate line;
grinding the three-dimensional memory sample to a polysilicon plug presenting a channel hole;
etching back and removing part of the dielectric layer to leak out the corresponding part of the channel hole;
forming a hard mask layer on the residual dielectric layer and the leaked channel hole, wherein the hard mask layer and the area corresponding to the channel hole are in a protruding structure;
spin-coating a photoresist layer on the hard mask layer, and forming a gate line opening pattern on the photoresist layer;
alignment measurements are performed between the gate line opening patterns and the protrusion structures.
2. The method of claim 1, wherein the grinding of the three-dimensional memory sample to the polysilicon plug presenting the channel hole is performed by: and grinding the silicon nitride layer on the dielectric layer and the buffer area of the channel hole in the three-dimensional memory sample by adopting a chemical mechanical grinding process until the polysilicon plug of the channel hole is formed.
3. The method according to claim 1, wherein said etching back and removing a portion of the dielectric layer to expose a corresponding portion of the trench hole comprises: and etching back and removing part of the dielectric layer by adopting a dry etching process to leak out the corresponding part of the channel hole.
4. The method of claim 1, wherein forming a hard mask layer over the remaining dielectric layer and the leaked channel hole comprises: and depositing an oxide on the residual dielectric layer and the leaked channel hole by adopting a chemical vapor deposition method to form an oxide layer, depositing carbon on the oxide layer to form a carbon layer, and depositing silicon oxynitride on the carbon layer to form a hard mask layer.
5. The method of claim 1, wherein a bottom end of the raised structure is flush with an upper surface of the channel hole.
6. The method of claim 1, wherein spin-coating a photoresist layer on the hard mask layer and forming a gate line opening pattern on the photoresist layer comprises: and spin-coating photoresist on the hard mask layer to form a photoresist layer, positioning and aligning a gate line opening pattern contained in the mask plate with the photoresist layer, and forming the gate line opening pattern on the photoresist layer through exposure and development processes.
7. The method of claim 1, wherein said performing alignment measurements between said gate line opening pattern and said raised structure comprises: and performing alignment measurement on the bottom end of the raised structure adjacent to one side wall of the gate opening pattern, and performing alignment measurement on the bottom end of the raised structure adjacent to the other side wall of the gate opening pattern.
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| CN201711182124.6A CN107993952B (en) | 2017-11-23 | 2017-11-23 | Alignment measuring method of gate line |
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| CN201711182124.6A CN107993952B (en) | 2017-11-23 | 2017-11-23 | Alignment measuring method of gate line |
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| CN107993952B true CN107993952B (en) | 2020-04-14 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101283446A (en) * | 2005-10-12 | 2008-10-08 | 英特尔公司 | Self-Aligned Gate Isolation |
| CN107369686A (en) * | 2016-05-11 | 2017-11-21 | 美光科技公司 | Semiconductor memery device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514277B2 (en) * | 2004-09-14 | 2009-04-07 | Tokyo Electron Limited | Etching method and apparatus |
| JP2015015287A (en) * | 2013-07-03 | 2015-01-22 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
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- 2017-11-23 CN CN201711182124.6A patent/CN107993952B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101283446A (en) * | 2005-10-12 | 2008-10-08 | 英特尔公司 | Self-Aligned Gate Isolation |
| CN107369686A (en) * | 2016-05-11 | 2017-11-21 | 美光科技公司 | Semiconductor memery device and preparation method thereof |
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