CN107993941A - The manufacture method and semiconductor alloy lead of semiconductor alloy lead - Google Patents
The manufacture method and semiconductor alloy lead of semiconductor alloy lead Download PDFInfo
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- CN107993941A CN107993941A CN201610955766.4A CN201610955766A CN107993941A CN 107993941 A CN107993941 A CN 107993941A CN 201610955766 A CN201610955766 A CN 201610955766A CN 107993941 A CN107993941 A CN 107993941A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 29
- 239000000956 alloy Substances 0.000 title 2
- 229910045601 alloy Inorganic materials 0.000 title 2
- 239000010410 layer Substances 0.000 claims abstract description 158
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 97
- 238000002955 isolation Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 238000000151 deposition Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000004090 dissolution Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- 230000004927 fusion Effects 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- VMPVEPPRYRXYNP-UHFFFAOYSA-I antimony(5+);pentachloride Chemical compound Cl[Sb](Cl)(Cl)(Cl)Cl VMPVEPPRYRXYNP-UHFFFAOYSA-I 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明的半导体金属引线的制造方法和半导体金属引线，其在半导体的制造方法中，通过在半导体衬底上进行绝缘介质生长，形成层间介质层；并对该层间介质层进行刻蚀，形成引线孔；在形成引线孔后的半导体衬底上沉积隔离介质，形成隔离层；在隔离层上沉积金属介质，形成金属层；对隔离层和金属层进行刻蚀，从而形成独特的由隔离层和金属层构成的两层金属引线结构，从根本上避免了金属层元素与半导体衬底层元素发生互溶的问题，提高半导体产品的生产良率和可靠性，降低生产成本，提高半导体制造的产品的市场竞争力。
The manufacturing method of the semiconductor metal lead and the semiconductor metal lead of the present invention, in the manufacturing method of the semiconductor, by growing an insulating medium on the semiconductor substrate, an interlayer dielectric layer is formed; and the interlayer dielectric layer is etched, Form a lead hole; deposit an isolation medium on the semiconductor substrate after forming the lead hole to form an isolation layer; deposit a metal medium on the isolation layer to form a metal layer; etch the isolation layer and the metal layer to form a unique isolation layer. The two-layer metal lead structure composed of the metal layer and the metal layer fundamentally avoids the problem of mutual dissolution between the elements of the metal layer and the elements of the semiconductor substrate layer, improves the production yield and reliability of semiconductor products, reduces production costs, and improves the quality of semiconductor manufacturing products. market competitiveness.
Description
技术领域technical field
本发明涉及半导体制造技术领域，尤其涉及一种半导体金属引线的制造方法和半导体金属引线。The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor metal lead and the semiconductor metal lead.
背景技术Background technique
随着半导体器件的技术发展，人们对半导体器件的性能要求越来越高。With the technological development of semiconductor devices, people have higher and higher requirements on the performance of semiconductor devices.
在半导体器件的生产过程中，无论是集成电路产品还是分立器件产品，必然会用到金属引线的生产工艺。目前在半导体制造过程中通常使用的金属引线都是金属铝，然而金属引线的铝衬底与半导体的硅衬底之间易发生铝硅互溶的问题，造成半导体器件的良率降低。In the production process of semiconductor devices, whether it is integrated circuit products or discrete device products, the production process of metal leads is bound to be used. At present, the metal leads commonly used in the semiconductor manufacturing process are all metal aluminum. However, the problem of mutual dissolution of aluminum and silicon between the aluminum substrate of the metal lead and the silicon substrate of the semiconductor is prone to occur, resulting in a decrease in the yield of semiconductor devices.
发明内容Contents of the invention
本发明提供一种半导体金属引线的制造方法和半导体金属引线，通过在半导体的金属层下方增加一层隔离层，形成独特的两层金属引线结构，以从根本上避免例如铝硅互溶问题，从而提高产品的生产良率和可靠性，降低生产成本，提高半导体制造的产品的市场竞争力。The present invention provides a method for manufacturing semiconductor metal leads and semiconductor metal leads. By adding an isolation layer under the metal layer of the semiconductor, a unique two-layer metal lead structure is formed to fundamentally avoid the problem of mutual solubility of aluminum and silicon, thereby Improve the production yield and reliability of products, reduce production costs, and improve the market competitiveness of semiconductor-manufactured products.
本发明提供一种半导体金属引线的制造方法，包括：The invention provides a method for manufacturing a semiconductor metal lead, comprising:
在半导体衬底上进行绝缘介质生长，形成层间介质层；Insulating dielectric growth is carried out on the semiconductor substrate to form an interlayer dielectric layer;
对所述层间介质层进行刻蚀，形成引线孔；Etching the interlayer dielectric layer to form lead holes;
在形成所述引线孔后的半导体衬底上沉积隔离介质，形成隔离层；Depositing an isolation medium on the semiconductor substrate after forming the lead hole to form an isolation layer;
在所述隔离层上沉积金属介质，形成金属层；Depositing a metal medium on the isolation layer to form a metal layer;
对所述隔离层和所述金属层进行刻蚀，形成金属引线。Etching the isolation layer and the metal layer to form metal leads.
可选的，所述在形成所述引线孔后的半导体衬底上沉积隔离介质，形成隔离层，包括：Optionally, depositing an isolation medium on the semiconductor substrate after forming the lead hole to form an isolation layer includes:
采用化学气相沉积工艺在形成所述引线孔后的半导体衬底上沉积高掺杂多晶硅，形成高掺杂低电阻的多晶硅层。A chemical vapor deposition process is used to deposit highly doped polysilicon on the semiconductor substrate after the lead holes are formed to form a highly doped and low-resistance polysilicon layer.
可选的，所述在形成所述引线孔后的半导体衬底上沉积隔离介质，形成隔离层，包括：Optionally, depositing an isolation medium on the semiconductor substrate after forming the lead hole to form an isolation layer includes:
在形成所述引线孔后的半导体衬底上沉积多晶硅，在所沉积的多晶硅内注入或扩散掺杂介质，形成高掺杂低电阻的多晶硅层。Polysilicon is deposited on the semiconductor substrate after the lead hole is formed, and a doping medium is implanted or diffused into the deposited polysilicon to form a highly doped and low-resistance polysilicon layer.
可选的，所述高掺杂低电阻的多晶硅层中所包含的掺杂介质包括以下介质中的至少一种：硼、磷、砷、锑。Optionally, the doping medium contained in the highly doped low-resistance polysilicon layer includes at least one of the following mediums: boron, phosphorus, arsenic, and antimony.
可选的，所述对所述隔离层和所述金属层进行刻蚀，包括：Optionally, the etching the isolation layer and the metal layer includes:
采用干法刻蚀对所述隔离层和所述金属层进行刻蚀，形成金属引线。The isolation layer and the metal layer are etched by dry etching to form metal leads.
可选的，所述半导体衬底包括以下衬底中的任意一种：硅衬底、氮化镓衬底、碳化硅衬底。Optionally, the semiconductor substrate includes any one of the following substrates: a silicon substrate, a gallium nitride substrate, and a silicon carbide substrate.
可选的，所述金属介质为铝。Optionally, the metal medium is aluminum.
可选的，所述绝缘介质为氧化硅或氮化硅。Optionally, the insulating medium is silicon oxide or silicon nitride.
本发明还提供一种半导体金属引线，包括：半导体衬底上形成的层间介质层；所述层间介质层为绝缘层；The present invention also provides a semiconductor metal lead, comprising: an interlayer dielectric layer formed on a semiconductor substrate; the interlayer dielectric layer is an insulating layer;
所述层间介质层上形成有引线孔；Lead holes are formed on the interlayer dielectric layer;
所述引线孔内形成有隔离层和金属层；An isolation layer and a metal layer are formed in the lead hole;
其中，所述引线孔内的所述隔离层与所述半导体衬底相接触，所述金属层位于所述隔离层上方。Wherein, the isolation layer in the lead hole is in contact with the semiconductor substrate, and the metal layer is located above the isolation layer.
可选的，所述隔离层为高掺杂低电阻的多晶硅层。Optionally, the isolation layer is a polysilicon layer with high doping and low resistance.
本发明的半导体金属引线的制造方法和半导体金属引线，其在半导体的制造方法中，通过在半导体衬底上进行绝缘介质生长，形成层间介质层；并对该层间介质层进行刻蚀，形成引线孔；在形成引线孔后的半导体衬底上沉积隔离介质，形成隔离层；在隔离层上沉积金属介质，形成金属层；对隔离层和金属层进行刻蚀，从而形成独特的由隔离层和金属层构成的两层金属引线结构，从根本上避免了金属层元素与半导体衬底层元素发生互溶的问题，提高半导体产品的生产良率和可靠性，降低生产成本，提高半导体制造的产品的市场竞争力。The manufacturing method of the semiconductor metal lead and the semiconductor metal lead of the present invention, in the manufacturing method of the semiconductor, by growing an insulating medium on the semiconductor substrate, an interlayer dielectric layer is formed; and the interlayer dielectric layer is etched, Form a lead hole; deposit an isolation medium on the semiconductor substrate after forming the lead hole to form an isolation layer; deposit a metal medium on the isolation layer to form a metal layer; etch the isolation layer and the metal layer to form a unique isolation layer. The two-layer metal lead structure composed of the metal layer and the metal layer fundamentally avoids the problem of mutual dissolution between the elements of the metal layer and the elements of the semiconductor substrate layer, improves the production yield and reliability of semiconductor products, reduces production costs, and improves the quality of semiconductor manufacturing products. market competitiveness.
附图说明Description of drawings
图1为一示例性实施例示出的半导体金属引线的制造方法的流程图；Fig. 1 is a flow chart of a method for manufacturing a semiconductor metal lead shown in an exemplary embodiment;
图2～图5为图1所示实施例的各个步骤中所形成的半导体的剖面结构示意图；2 to 5 are schematic cross-sectional structure diagrams of semiconductors formed in various steps of the embodiment shown in FIG. 1;
图6为另一示例性实施例示出的半导体金属引线的制造方法的流程图。FIG. 6 is a flowchart of a method for manufacturing a semiconductor metal lead shown in another exemplary embodiment.
附图说明：Description of drawings:
半导体衬底1、层间介质层2、引线孔3、隔离层4、金属层5。A semiconductor substrate 1 , an interlayer dielectric layer 2 , a lead hole 3 , an isolation layer 4 , and a metal layer 5 .
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
图1为一示例性实施例示出的半导体金属引线的制造方法的流程图，图2～图5为图1所示实施例的各个步骤中所形成的半导体的剖面结构示意图，如图1～5所示，本实施例的方法包括：Fig. 1 is a flowchart of a method for manufacturing semiconductor metal leads shown in an exemplary embodiment, and Fig. 2 to Fig. 5 are schematic cross-sectional structure diagrams of semiconductors formed in various steps of the embodiment shown in Fig. 1 , as Fig. 1 to 5 As shown, the method of the present embodiment includes:
步骤101、在半导体衬底1上进行绝缘介质生长，形成层间介质层2。Step 101 , performing insulating dielectric growth on the semiconductor substrate 1 to form an interlayer dielectric layer 2 .
步骤102、对层间介质层2进行刻蚀，形成引线孔3(如图2所示)。Step 102 , etching the interlayer dielectric layer 2 to form lead holes 3 (as shown in FIG. 2 ).
步骤103、在形成引线孔3后的半导体衬底上沉积隔离介质，形成隔离层4(如图3所示)。Step 103 , depositing an isolation medium on the semiconductor substrate after the lead hole 3 is formed to form an isolation layer 4 (as shown in FIG. 3 ).
步骤104、在隔离层4上沉积金属介质，形成金属层5(如图4所示)。Step 104 , depositing a metal medium on the isolation layer 4 to form a metal layer 5 (as shown in FIG. 4 ).
步骤105、对隔离层4和金属层5进行刻蚀，形成金属引线(如图5所示)。Step 105 , etching the isolation layer 4 and the metal layer 5 to form metal leads (as shown in FIG. 5 ).
在半导体器件的生产过程中，需要制作金属引线，然而构成金属引线的金属层中的金属介质易发生与其下的下层介质，如硅介质发生融合，从而影响了金属引线的导电性能，使得半导体器件的良品率降低。本发明在进行金属层沉积工艺前，先沉积一层隔离介质，该隔离介质具有低电阻，不会对金属层的导电性能构成影响，同时还能对金属层与其下层介质间的融合起到隔离作用。具体实现为，首先在半导体衬底1上进行绝缘介质生长，该绝缘介质可以采用任意类型的绝缘介质，例如，氧化硅SiO2、氮化硅Si3N4等形成该层间介质层2。对层间介质层2采用光刻和刻蚀，形成引线孔3。再在形成了引线孔3后的整个半导体衬底的上表面分别沉积隔离介质和金属介质，形成隔离层4和金属层5。其中，隔离介质可以采用经过掺杂处理的多晶硅，从而获得高掺杂低电阻的多晶硅隔离层4，用于沉积的金属介质可以采用铝或其他金属材料，以构成金属层5。再对隔离层4和金属层5一起采用光刻和刻蚀工艺，保留引线孔3内以及孔外预设范围内的隔离层4和金属层5，形成半导体的金属引线结构。其中，刻蚀方式可以采用利用反应气体与等离子体进行刻蚀的干法刻蚀技术，也可以采用利用化学试剂与被刻蚀材料发生化学反应进行刻蚀的湿法刻蚀技术。本实施例对刻蚀方法不作具体限制，本领域技术人员可以根据半导体器件的个体特性进行选择。In the production process of semiconductor devices, it is necessary to make metal leads. However, the metal medium in the metal layer that constitutes the metal leads is prone to fusion with the underlying medium, such as the silicon medium, which affects the electrical conductivity of the metal leads and makes semiconductor devices The yield rate is reduced. In the present invention, before the metal layer deposition process, a layer of isolation medium is deposited first. The isolation medium has low resistance, does not affect the conductivity of the metal layer, and can also isolate the fusion between the metal layer and the underlying medium. effect. Specifically, the interlayer dielectric layer 2 is formed by first growing an insulating dielectric on the semiconductor substrate 1 . The insulating dielectric can be any type of insulating dielectric, for example, silicon oxide SiO 2 , silicon nitride Si 3 N 4 , etc. Photolithography and etching are used for the interlayer dielectric layer 2 to form lead holes 3 . Then, an isolation medium and a metal medium are respectively deposited on the upper surface of the entire semiconductor substrate after the lead hole 3 is formed to form an isolation layer 4 and a metal layer 5 . Wherein, the isolation medium can be doped polysilicon, so as to obtain a polysilicon isolation layer 4 with high doping and low resistance, and the metal medium used for deposition can be aluminum or other metal materials to form the metal layer 5 . The isolation layer 4 and the metal layer 5 are then photolithographically and etched together to retain the isolation layer 4 and the metal layer 5 within the lead hole 3 and outside the hole in a predetermined range, forming a semiconductor metal lead structure. The etching method may be a dry etching technique using reactive gas and plasma, or a wet etching technique using a chemical reaction between a chemical reagent and the material to be etched. This embodiment does not specifically limit the etching method, which can be selected by those skilled in the art according to the individual characteristics of the semiconductor device.
本实施例的半导体金属引线的制造方法，通过在半导体衬底上进行绝缘介质生长，形成层间介质层；并对该层间介质层进行刻蚀，形成引线孔；在形成引线孔后的半导体衬底上沉积隔离介质，形成隔离层；在隔离层上沉积金属介质，形成金属层；对隔离层和金属层进行刻蚀，从而形成独特的由隔离层和金属层构成的两层金属引线结构，从根本上避免了金属层元素与半导体衬底层元素发生互溶的问题，提高半导体产品的生产良率和可靠性，降低生产成本，提高半导体制造的产品的市场竞争力。The manufacturing method of the semiconductor metal lead of the present embodiment is to form an interlayer dielectric layer by growing an insulating dielectric on the semiconductor substrate; and etch the interlayer dielectric layer to form a lead hole; after forming the lead hole, the semiconductor Deposit the isolation medium on the substrate to form an isolation layer; deposit a metal medium on the isolation layer to form a metal layer; etch the isolation layer and the metal layer to form a unique two-layer metal lead structure composed of the isolation layer and the metal layer , It fundamentally avoids the problem of miscibility between metal layer elements and semiconductor substrate layer elements, improves the production yield and reliability of semiconductor products, reduces production costs, and improves the market competitiveness of semiconductor manufacturing products.
图6为另一示例性实施例示出的半导体金属引线的制造方法的流程图，在上一实施例的基础上，进一步地，本实施例包括以下具体的步骤：FIG. 6 is a flow chart of a method for manufacturing semiconductor metal leads shown in another exemplary embodiment. On the basis of the previous embodiment, further, this embodiment includes the following specific steps:
步骤201、在半导体衬底1上进行绝缘介质生长，形成层间介质层2。Step 201 , perform insulating dielectric growth on the semiconductor substrate 1 to form an interlayer dielectric layer 2 .
步骤202、对层间介质层2进行刻蚀，形成引线孔3。Step 202 , etching the interlayer dielectric layer 2 to form a lead hole 3 .
步骤203、在形成引线孔3后的半导体衬底上沉积多晶硅。Step 203 , depositing polysilicon on the semiconductor substrate after the lead hole 3 is formed.
步骤204、在所沉积的多晶硅内注入或扩散掺杂介质，形成高掺杂低电阻的多晶硅层4(也就是隔离层4)。Step 204 , implanting or diffusing a doping medium into the deposited polysilicon to form a highly doped and low-resistance polysilicon layer 4 (that is, an isolation layer 4 ).
步骤205、在高掺杂低电阻的多晶硅层4上沉积金属介质，形成金属层5。Step 205 , depositing a metal medium on the highly doped and low-resistance polysilicon layer 4 to form a metal layer 5 .
步骤206、对隔离层和金属层进行刻蚀，形成金属引线。Step 206 , etching the isolation layer and the metal layer to form metal leads.
具体的，在形成引线孔后的半导体衬底上沉积多晶硅，以使多晶硅对金属介质(例如铝)和半导体衬底(例如硅)的硅铝融合问题起到隔离作用。但是由于沉积了多晶硅后的多晶硅层与金属层一起形成金属引线，为了尽可能减少半导体器件的阻值，对多晶硅层可以采用离子注入工艺或扩散工艺，进行掺杂处理，形成高掺杂低电阻的多晶硅层。其中，所谓扩散就是将一定数量和一定种类的杂质掺入到多晶硅中，以改变多晶硅的电学性质，形成低电阻的多晶硅层。根据所掺杂的杂质源的不同，可以进行固态源扩散、液态源扩散、气态源扩散。本实施例中高掺杂低电阻的多晶硅层中所包含的掺杂介质包括以下介质中的至少一种：硼、磷、砷、锑；其中，硼(B)以乙硼烷(气体)进行气态源扩散，还可以以三氟化硼(气体)进行气态源扩散，还可以以三溴化硼(液体)进行液态源扩散；磷(P)以磷烷(气体)进行气态源扩散，还可以以三氯氧磷(液体)进行液态源扩散；砷(As)以砷烷(气体)进行气态源扩散；锑(Sb)以五氯化锑(固体)进行固态源扩散。所谓离子注入是在高真空的复杂系统中，通过离子注入的浓度产生电离杂质并形成高能量的离子束，再将其打到硅片靶中进行多晶硅层的掺杂处理。离子注入层的深度依赖于离子能量，杂质浓度依赖于离子剂量，因此通过精确控制掺杂层的深度和浓度可以获得所需的尽可能小的电阻阻值的高掺杂多晶硅层。注入掺杂和扩散掺杂对比来说，离子注入掺杂的加工温度低、容易制作浅结、均匀的大面积注入杂质、易于自动化，但成本较高。本申请对于掺杂的具体工艺没有限定，但掺杂后的多晶硅层需要具备预设的低电阻阻值。Specifically, polysilicon is deposited on the semiconductor substrate after the lead hole is formed, so that the polysilicon can isolate the silicon-aluminum fusion problem of the metal medium (such as aluminum) and the semiconductor substrate (such as silicon). However, since the polysilicon layer after polysilicon deposition and the metal layer form metal leads together, in order to reduce the resistance of the semiconductor device as much as possible, the polysilicon layer can be doped by ion implantation or diffusion process to form a high-doped low-resistance polysilicon layer. Among them, the so-called diffusion is to dope a certain amount and a certain type of impurities into the polysilicon to change the electrical properties of the polysilicon and form a low-resistance polysilicon layer. Depending on the impurity sources to be doped, solid-state source diffusion, liquid-state source diffusion, and gas-state source diffusion can be performed. In this embodiment, the doping medium contained in the highly doped and low-resistance polysilicon layer includes at least one of the following mediums: boron, phosphorus, arsenic, and antimony; wherein, boron (B) is carried out in a gaseous state with diborane (gas) Source diffusion can also be performed with boron trifluoride (gas) for gaseous source diffusion, and boron tribromide (liquid) for liquid source diffusion; phosphorus (P) can be used for gaseous source diffusion with phosphine (gas), and can also be Phosphorus oxychloride (liquid) is used for liquid source diffusion; arsenic (As) is used for arsine (gas) for gaseous source diffusion; antimony (Sb) is used for antimony pentachloride (solid) for solid source diffusion. The so-called ion implantation is to generate ionized impurities through the concentration of ion implantation in a complex system of high vacuum and form a high-energy ion beam, which is then injected into the silicon wafer target for doping treatment of the polysilicon layer. The depth of the ion-implanted layer depends on the ion energy, and the impurity concentration depends on the ion dose. Therefore, by accurately controlling the depth and concentration of the doped layer, the required highly doped polysilicon layer with the smallest possible resistance value can be obtained. Compared with implantation doping and diffusion doping, the processing temperature of ion implantation doping is low, it is easy to make shallow junctions, uniform large-area implantation of impurities, and easy to automate, but the cost is relatively high. The present application does not limit the specific process of doping, but the doped polysilicon layer needs to have a preset low resistance value.
进一步地，对于隔离层的形成，除了采用先沉积多晶硅层，再在多晶硅层内采用离子注入或扩散工艺进行掺杂处理外，还可以预先形成高掺杂多晶硅，再利用化学气相沉积工艺将预先形成的高掺杂多晶硅沉积在半导体衬底上，形成高掺杂低电阻的多晶硅层。相较于步骤203和步骤204，直接在待加工的半导体上进行离子注入，易造成晶格损伤，所以可以采用预先加工好高掺杂低电阻的多晶硅，再将掺杂后的多晶硅沉积在半导体衬底上。Further, for the formation of the isolation layer, in addition to depositing the polysilicon layer first, and then performing doping treatment in the polysilicon layer by ion implantation or diffusion process, it is also possible to pre-form highly doped polysilicon, and then use chemical vapor deposition process to preform the polysilicon layer. The formed highly doped polysilicon is deposited on the semiconductor substrate to form a highly doped and low resistance polysilicon layer. Compared with step 203 and step 204, ion implantation directly on the semiconductor to be processed is easy to cause lattice damage, so pre-processed polysilicon with high doping and low resistance can be used, and then the doped polysilicon is deposited on the semiconductor on the substrate.
在上述实施例的基础上，On the basis of the above examples,
可选的，步骤206中对隔离层和金属层的刻蚀，可以采用干法刻蚀工艺。Optionally, a dry etching process may be used to etch the isolation layer and the metal layer in step 206 .
可选的，半导体衬底可以包括以下衬底中的任意一种：硅衬底、氮化镓衬底、碳化硅衬底。Optionally, the semiconductor substrate may include any one of the following substrates: a silicon substrate, a gallium nitride substrate, and a silicon carbide substrate.
可选的，构成金属层的金属介质可以为铝介质。Optionally, the metal medium constituting the metal layer may be an aluminum medium.
可选的，步骤201中在半导体衬底上进行绝缘介质生长，该绝缘介质可以为氧化硅或氮化硅。Optionally, in step 201, an insulating medium is grown on the semiconductor substrate, and the insulating medium may be silicon oxide or silicon nitride.
参照图5，本发明还提供一种半导体金属引线，包括：半导体衬底1上形成的层间介质层2；层间介质层2为绝缘层；层间介质层2上形成有引线孔3；引线孔3内形成有隔离层4和金属层5；其中，引线孔3内的隔离层4与半导体衬底1相接触，金属层5位于隔离层4上方。其中，该隔离层4为高掺杂低电阻的多晶硅层。Referring to FIG. 5 , the present invention also provides a semiconductor metal lead, comprising: an interlayer dielectric layer 2 formed on a semiconductor substrate 1; the interlayer dielectric layer 2 is an insulating layer; a lead hole 3 is formed on the interlayer dielectric layer 2; An isolation layer 4 and a metal layer 5 are formed in the lead hole 3 ; wherein, the isolation layer 4 in the lead hole 3 is in contact with the semiconductor substrate 1 , and the metal layer 5 is located above the isolation layer 4 . Wherein, the isolation layer 4 is a polysilicon layer with high doping and low resistance.
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.
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