CN107979264B - Line voltage detection circuit and related detection method - Google Patents

Abstract

Line voltage detection circuit and related detection method. An embodiment of the present invention provides a line voltage detection circuit, which is applicable to a power controller, which has a high voltage end connected to the line voltage through a high voltage resistor. The line voltage is associated with an AC input voltage. The line voltage detection circuit includes a high voltage start-up transistor, a switchable current source, a voltage divider circuit, and a management circuit. The high voltage start-up transistor is connected to the high voltage end. The switchable current source is connected between the high voltage start-up transistor and a ground line. The voltage divider circuit includes two voltage divider resistors, which are connected in series between the high voltage end and the ground line, and can provide a voltage divider result. According to the voltage divider result, the management circuit switches the switchable current source to selectively provide an offset current flowing through the high voltage start-up transistor and the high voltage resistor.

Description

Line voltage detection circuit and related detection method

technical field

The invention relates to a detection circuit for alternating current, in particular to a detection circuit and a detection method for line voltage generated by rectification of alternating current.

Background technique

For an AC-to-DC power supply, the voltage value of the line voltage is often very important information. For example, the power supply may need to stop power conversion when the line voltage is too low to prevent operational errors, which is called brown-out protection. When the line voltage is high enough, the power supply is allowed to operate normally to provide power conversion, which is called brown-in. Moreover, knowing the voltage value of the line voltage can also provide line voltage compensation for the operation of the power supply.

FIG. 1 illustrates an AC-to-DC power supply 100 with a flyback architecture. The bridge rectifier 12 provides full-wave rectification for the commercial power V _AC-MAIN , and generates an input voltage V _IN at the input terminal IN, and the commercial power V _AC-MAIN can be regarded as an AC input voltage. A power controller (power controller) 18 is generally an integrated circuit, which provides a pulse-width modulation (PWM) signal S _PWM to control the power switch 26 and also controls the current flowing through the transformer 16 . When the power switch 26 is turned on (ON), the transformer 16 stores energy; when the power switch 26 is turned off (OFF), the transformer 16 releases energy, and the output voltage V _OUT is established in the output capacitor 30 through the diode 32 to supply power to the load 19 .

Diode 14 provides half-wave rectification, producing line voltage V _LINE . The power controller 18 has a high-voltage terminal HV connected to the line voltage V _LINE through a high-voltage resistor 20 , wherein the high-voltage resistor is not a necessary component, and in another embodiment of the present invention, the high-voltage resistor 20 can be omitted. The power controller 18 may provide a high-voltage startup function. When the mains V _AC-MAIN starts supplying power, the power controller 18 can draw a charging current from the high voltage terminal HV, and charge the operating power capacitor 28 by operating the power terminal VCC to establish the operating power voltage V _CC . Once the operating power voltage V _CC is high enough, the charging current is turned off, and the power controller 18 can start to provide the PWM signal S _PWM .

FIG. 2A exemplifies a power controller 18a and illustrates a method for detecting the line voltage V _LINE . There is a high-voltage start-up transistor 46 in the power controller 18a, which is turned on during high-voltage start-up, and can provide charging current to charge the operating power supply capacitor 28 . Outside the power controller 18a, a voltage dividing circuit 40a is connected between the high voltage terminal HV and the ground line GND. The voltage-dividing circuit 40a includes voltage-dividing resistors 42a and 44a, the connection point of which can provide the voltage-dividing result to the detection terminal SENS of the power controller 18a, so that it can know the voltage value of the line voltage V _LINE . For system designers, this is very convenient, because different combinations of voltage dividing resistors 42 and 44 can select the trigger point of undervoltage protection or full pressure braking. However, in terms of architecture, FIG. 2A is expensive because there are two more external voltage dividing resistors 42a and 44a, and the power controller 18a also needs one more pin as the detection terminal SENS.

Another method for detecting the line voltage V _LINE is to build the voltage divider circuit 40 a in FIG. 2A into a power controller, such as the power controller 18 b shown in FIG. 2B . Compared with the power controller 18a in FIG. 2A , the power controller 18b in FIG. 2B has a built-in voltage dividing circuit 40b and does not have a detection terminal SENS. The power controller 18b may result in a less expensive power supply, but may sacrifice the system designer's ability to adjust or change the trigger point of the brownout protection, for example.

Contents of the invention

An embodiment of the present invention provides a detection method for a line voltage, which is suitable for a power supply controller, which has a high-voltage terminal connected to the line voltage through a high-voltage resistor. The line voltage is associated with an AC input voltage. The power controller includes a high voltage enable transistor. The detection method includes: providing a voltage divider circuit, which at least includes two voltage divider resistors, connected in series between the high voltage end and a ground wire, and the high voltage end has a first input voltage; using the voltage divider circuit to detect The first input voltage, and provide a voltage division result; and, according to the voltage division result, switch an offset current, which flows through the high voltage enabling transistor and the high voltage resistor.

The embodiment of the present invention also provides a line voltage detection circuit suitable for a power controller, which has a high voltage terminal connected to the line voltage through a high voltage resistor. The line voltage is associated with an AC input voltage. The line voltage detection circuit includes a high-voltage start transistor, a switchable current source, a voltage divider circuit, and a management circuit. The high voltage enable transistor is connected to the high voltage terminal. The switchable current source is connected between the high voltage enable transistor and a ground line. The voltage dividing circuit includes two voltage dividing resistors, which are connected in series between the high voltage end and the grounding line, and can provide a voltage dividing result. According to the divided voltage result, the management circuit switches the switchable current source to selectively provide an offset current to flow through the high voltage enable transistor and the high voltage resistor.

Description of drawings

FIG. 1 is an example of an AC-to-DC power supply with a flyback architecture.

2A and 2B illustrate two kinds of power controllers.

FIG. 3 shows a power controller implemented according to the present invention.

FIG. 4 shows signal waveforms of some of the signals in FIG. 3 .

FIG. 5 shows another AC-to-DC power supply with a flyback architecture implemented according to the present invention.

【Symbol Description】

12 bridge rectifier

14 diodes

16 Transformers

18, 18a, 18b, 18c Power Controller

19 load

20 high voltage resistor

26 power switch

28 Power Capacitor

30 Output capacitor

32 diodes

40a, 40b, 40c voltage divider circuit

42a, 42b, 42c, 44a, 44b, 44c Divider resistors

46 High voltage start transistor

100, 600 AC to DC power supply

202 diodes

204 management circuit

206 Switchable Current Source

208 Undervoltage protection circuit

209 defibrillation circuit

210 foot brake circuit

211 NOT gate

212 signal generator

213 SR flip-flop

220 Comparators

222 Single Pulse Generator

224 control circuit

230 defibrillation circuit

232 AND gate

234 NOT gate

240D flip-flop

242 AND gate

CLK clock signal

GND ground wire

HV high voltage side

IN input terminal

I _OS offset current

IOS fixed value

RG preset range

S _BI confirmation signal

S _CHK Comparison Results

SENS detection terminal

S _PWM PWM signal

S _RES pulse

t1, t2, t3 time points

T _DEB1 , T _DEB2 defibrillation time

V _AC-MAIN

V _BNO partial voltage result

V _BTM lower limit voltage

V _CC power supply voltage

VCC operation power terminal

V _HV input voltage

V _IN input voltage

V _LINE line voltage

V _OUT output voltage

V _REF reference voltage

V _TOP upper limit voltage

Detailed ways

In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and can be deduced by those skilled in the art based on the teaching of this specification. For the sake of brevity in the description, elements with the same symbols will not be repeated.

FIG. 3 shows a power controller 18c implemented according to the present invention, and some peripheral circuits. In one embodiment, the power controller 18 c is an integrated circuit, which can replace the power controller 18 in FIG. 1 , and can provide a PWM signal S _PWM to control the power switch 26 .

The power controller 18c has a high voltage enable transistor 46 connected to the high voltage terminal HV. For example, it is a depletion mode metal-oxide-semiconductor (MOS) transistor. It is turned on when the high voltage is started, and can provide charging current to charge the operating power supply capacitor 28 through the diode 202 . When the operating power supply voltage V _CC is higher than a certain level, such as exceeding 20V, the high-voltage start-up transistor 46 can be automatically turned off because its source voltage is pulled high, and stop supplying the charging current. As shown for example in FIG. 3 , the high voltage enable transistor 46 can be electrically connected to the line voltage V _LINE through the high voltage terminal HV and the high voltage resistor 20 .

The power controller 18c includes a switchable current source 206 , a voltage dividing circuit 40c , a management circuit 204 , an undervoltage protection circuit 208 , a foot voltage brake circuit 210 , and a signal generator 212 .

The voltage dividing circuit 40c has two voltage dividing resistors 42c and 44c, which are connected in series between the high voltage terminal HV and the ground line GND. The connection point between the voltage dividing resistors 42 c and 44 c can provide a voltage dividing result V _BNO to the management circuit 204 , which controls the switchable current source 206 accordingly. The voltage dividing circuit 40c detects the input voltage V _HV at the high voltage terminal HV, and generates a voltage dividing result V _BNO that is approximately proportional.

When the switchable current source 206 is turned on, it can provide an offset current I _OS . The offset current I _OS is approximately a certain value IOS that is not zero, and it starts from the line voltage V _LINE and flows through the high voltage resistor 20 , the high voltage enable transistor 46 and the switchable current source 206 . When the switchable current source 206 is turned off, the offset current I _OS disappears. The switchable current source 206 can be designed to be turned on after the high-voltage start-up is completed, or when the operating power supply voltage V _CC is high enough.

As shown in FIG. 3 , the management circuit 204 includes a comparator 220 , a single pulse generator 222 , and a control circuit 224 . The comparator 220 compares the divided voltage result V _BNO with a reference voltage V _REF to generate a comparison result S _CHK . It will be explained later that when the comparison result S _CHK changes from logic 0 to logic 1, the single pulse generator 222 can provide a pulse S _RES . When the pulse S _RES does not exist (logic value 0), the control circuit 224 keeps turning off the switchable current source 206 . When the pulse S _RES appears, the control circuit 224 allows the clock signal CLK to trigger to turn on the switchable current source 206 .

The single pulse generator 222 includes a debounce circuit 230 , a NOT gate 234 , and an AND gate 232 . In this embodiment, as long as the comparison result S _CHK is logic 0, the confirmation signal S _BI will be logic 0. Only when the comparison result S _CHK changes from logic 0 to logic 1 and stays at logic 1 for more than a preset defibrillation time T _DEB1 , the logic value of confirmation signal S _BI will change from 0 1. In this embodiment, the defibrillation time T _DEB1 is about 300us. The NOT gate 234 and the AND gate 232 together serve as a logic circuit to generate the pulse S _RES according to the comparison result S _CHK and the confirmation signal S _BI .

The control circuit 224 receives the clock signal CLK and the pulse S _RES . When the pulse S _RES is not present (logic 0), the D flip-flop 240 is always reset, maintaining its output at a logic 0, turning off the switchable current source 206 . When the pulse S _RES appears, which is logic 1, the D flip-flop 240 can turn on the switchable current source 206 through the AND gate 242 when the next rising edge of the clock signal CLK occurs. In this embodiment, the period of the clock signal CLK is 100us.

The foot brake circuit 210 receives the confirmation signal S _BI . When the confirmation signal S _BI is logic 1, the SR flip-flop 213 is set (set), enabling the signal generator 212 . Therefore, the signal generator 212 can provide the PWM signal S _PWM to switch the power switch 26 , so that the power supply in FIG. 1 starts power conversion.

The undervoltage protection circuit 208 receives the confirmation signal S _BI . The undervoltage protection circuit 208 has an inverter gate 211 and a defibrillation circuit 209 . Functionally, the defibrillation circuit 209 is the same as the defibrillation circuit 230 , except that the defibrillation time T _DEB2 of the defibrillation circuit 209 is different from the defibrillation time T _DEB1 of the defibrillation circuit 230 . In this embodiment, the defibrillation time T _DEB2 is approximately 180 ms. In other words, when the confirmation signal S _BI does not become logic 1 for 180 ms, the undervoltage protection circuit 208 will reset the SR flip-flop 213 and disable the signal generator 212 . At this time, the signal generator 212 is prohibited from providing the PWM signal S _PWM , the power switch 26 remains in the off state, and the power supply in FIG. 1 stops power conversion.

In this embodiment, the resistance of the high voltage resistor 20 is approximately tens of kiloohms, and the sum of the resistances of the voltage dividing resistors 42c and 44c is approximately tens of million ohms.

FIG. 4 shows signal waveforms of some of the signals in FIG. 3 . From top to bottom, they are line voltage V _LINE , voltage division result V _BNO , clock signal CLK, comparison result S _CHK , offset current I _OS , and confirmation signal S _BI .

In the first half of FIG. 4 , the line voltage V _LINE gradually increases; in the second half, the line voltage V _LINE gradually decreases.

Before time point t1, the offset current I _OS is 0A, the line voltage V _LINE is lower than the lower limit voltage V _BTM , and does not fall into the preset range RG, which is between the upper limit voltage V _TOP and the lower limit voltage V _BTM . The voltage division result V _BNO is approximately equal to K*V _LINE , which is less than the reference voltage V _REF , where K is a proportional constant determined by the voltage division circuit 40c. The comparison result S _CHK is fixed at logic 0, the confirmation signal S _BI is 0, and the pulse S _RES is maintained at 0. Therefore, the control circuit 224 keeps turning off the switchable current source 206 .

At time point t1, the line voltage V _LINE rises above the lower limit voltage V _BTM and falls into the preset range RG. At this time, the voltage division result V _BNO (equal to K*V _LINE ) relatively exceeds the reference voltage V _REF . Therefore, the comparison result S _CHK transitions to a logical 1, and the pulse S _RES then transitions to a logical 1. The control circuit 224 turns on the switchable current source 206 when the next rising edge of the clock signal CLK occurs, so that the offset current I _OS appears, which is a fixed value IOS exceeding 0A.

The appearance of the offset current I _OS will quickly pull down the input voltage V _HV and the voltage division result V _BNO . At this time, the voltage division result V _BNO is approximately equal to K*(V _LINE −IOS*RHV), where RHV is the resistance value of the high voltage resistor 20 . Therefore, the voltage division result V _BNO is quickly lower than the reference voltage V _REF . The comparison result S _CHK turns to logic 0, the pulse S _RES ends, the control circuit 224 immediately turns off the switchable current source 206 and turns off the offset current I _OS . This means that the turn-on of the offset current I _OS , after feedback, will cause it to turn off. In other words, the offset current I _OS is only turned on for a very short time, as shown in FIG. 4 .

Turning off the offset current I _OS will cause the voltage division result V _BNO to rise, making the logic value of the comparison result S _CHK change from 0 to 1. As previously described, when the next rising edge of the clock signal CLK occurs, the offset current I _OS is turned on for a very short time. In other words, the offset current I _OS is periodically turned on for a very short time every time a rising edge of the clock signal CLK occurs.

At time t2, the line voltage V _LINE has exceeded the upper limit voltage V _TOP . As shown in FIG. 4 , during the period from time point t1 to t2, the line voltage V _LINE is between the upper limit voltage V _TOP and the lower limit voltage V _BTM , and the offset current I _OS is periodically turned on and off according to the clock signal CLK .

During the rising process of the line voltage V _LINE , starting from the time point t2, the line voltage V _LINE has exceeded the upper limit voltage V _TOP , and does not fall into the preset range RG. At this time, no matter whether the offset current I _OS is turned on or not, the voltage division result V _BNO is greater than the reference voltage V _REF , and the comparison result S _CHK is logic 1. At this time, after the offset current I _OS is turned on, it will not be turned off early, and a duty cycle will be completely performed according to the clock signal CLK. When the comparison result S _CHK remains at a logic value of 1 and exceeds the defibrillation time T _DEB1 (300us), that is, the time point t3, the defibrillation circuit 230 allows the comparison result S _CHK to pass through and become the confirmation signal S _BI , which logically The 0's become 1's. Then the offset current I _OS is turned off stably.

As shown in Figure 4. During the period between time points t2 and t3, the offset current I _OS is turned on and off as the logic value of the clock signal CLK changes. In order to save energy consumed by turning on the offset current I _OS , the duty cycle (Duty Cycle) of the clock signal CLK can be designed to be 10% or less.

The acknowledgment signal S _BI will always maintain logic 1. Until the voltage division result V _BNO drops to the reference voltage V _REF , or the line voltage V _LINE drops to the lower limit voltage V _BTM , as happened at time point t4 in FIG. 4 , the confirmation signal S _BI and the comparison result S _CHK become Logical 0.

It can be seen from the analysis of FIG. 3 and FIG. 4 that the comparator 220 compares the voltage division result V _BNO and the reference voltage V _REF to detect whether the line voltage V _LINE falls within the preset range RG. Moreover, if the line voltage V _LINE does not fall within the preset range RG, the offset current I _OS will be continuously turned off. When the line voltage V _LINE falls within the preset range RG, the offset current I _OS is only turned on periodically and briefly. This means that most of the time, the offset current I _OS is turned off to save power.

From the above explanation, it can be known that the upper limit voltage V _TOP and the lower limit voltage V _BTM comply with the following formulas (1) and (2), respectively.

K*(V _TOP –RHV*IOS)＝V _REF ......(1)

K*V _BTM ＝V _REF ......(2)

Formula (1) clearly shows that the upper limit voltage V _TOP is related to the resistance value RHV of the high voltage resistor 20 . When the offset current I _OS appears, it is approximately a fixed value IOS preset by the integrated circuit. Therefore, the system designer can determine the upper limit voltage V _TOP by selecting the resistance value RHV of the high voltage resistor 20 .

Only when the line voltage V _LINE stably exceeds the upper limit voltage V _TOP , the confirmation signal S _BI will be logic 1. Therefore, the confirmation signal S _BI can be used as a judgment for undervoltage protection or full pressure braking.

As shown in FIG. 3 , when the confirmation signal S _BI is logic 1, the foot brake circuit 210 enables the signal generator 212 . Therefore, the signal generator 212 can provide the PWM signal S _PWM to switch the power switch 26 , so that the power supply in FIG. 1 starts power conversion. After more than 180 ms, the confirmation signal S _BI has always been logic 0 and has not become logic 1, which means that the peak value of the line voltage V _LINE is determined to be too low, so the undervoltage protection circuit 208 resets the foot pressure The SR flip-flop 213 in the driving circuit 210, the disable signal generator 212, and the power switch 26 remain in the off state, and the power supply in FIG. 1 stops power conversion.

In FIG. 3 , the criterion for the line voltage V _LINE to trigger the under-voltage protection or the full-voltage brake is the upper limit voltage V _TOP , which can be determined by selecting the resistance value RHV of the high-voltage resistor 20 .

FIG. 5 shows another AC-to-DC power supply 600 with a flyback structure implemented according to the present invention, which can also have a high-voltage start-up function, and uses the power controller 18c of FIG. 3 . FIG. 5 does not have the diode 14 in FIG. 1 , and the line voltage V _LINE of FIG. 5 is directly provided by the bridge rectifier 12 .

Although the present invention is described above with an AC-to-DC power supply with a flyback structure as an embodiment, the present invention is not limited thereto. The present invention can also be applied to a booster converter (booster), a buck converter (buck converter) and the like.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A detection method of a line voltage, which is applicable to a power controller, which has a high-voltage terminal connected to the line voltage through a high-voltage resistor, the line voltage is associated with an AC input voltage, and the power controller includes a high-voltage start-up transistor, The detection method includes: A voltage dividing circuit is provided, which includes at least two voltage dividing resistors connected in series between the high voltage end and the ground line, and the high voltage end has a first input voltage; detecting the first input voltage with the voltage dividing circuit, and providing a voltage dividing result; and According to the divided voltage result, switch an offset current, which flows through the high voltage enable transistor and the high voltage resistor; Wherein, the detection method also includes: Comparing the divided voltage result with the reference voltage to detect whether the line voltage exceeds the upper limit voltage, wherein the upper limit voltage is related to the resistance value of the high voltage resistor. 2. detection method as claimed in claim 1, also comprises: Comparing the divided voltage result with the reference voltage to detect whether the line voltage is lower than a lower limit voltage. 3. The detection method according to claim 2, wherein a preset range is defined between the upper limit voltage and the lower limit voltage, and the detection method further comprises: When the line voltage does not fall into the preset range, the offset current is continuously turned off. 4. detection method as claimed in claim 3, also comprises: When the line voltage falls within the preset range, the offset current is switched on and off periodically. 5. detection method as claimed in claim 4, also comprises: providing a clock signal; and When the line voltage falls into the preset range, the offset current is periodically turned on according to the clock signal. 6. detection method as claimed in claim 1, also comprises: Turn on the high-voltage startup transistor to provide charging current to charge the operating power supply. 7. A line voltage detection circuit suitable for a power controller, which has a high voltage terminal connected to the line voltage through a high voltage resistor, the line voltage is associated with an AC input voltage, comprising: A high-voltage startup transistor connected to the high-voltage terminal; A switchable current source is connected between the high-voltage startup transistor and the ground line; a voltage dividing circuit, which includes at least two voltage dividing resistors, which are connected in series between the high voltage end and the ground wire, and can provide a voltage dividing result; and The management circuit switches the switchable current source according to the voltage division result to selectively provide an offset current to flow through the high-voltage start-up transistor and the high-voltage resistor; Among them, the management circuit includes: a comparator for comparing the divided voltage result with a reference voltage to generate a comparison result; a single pulse generator, which can provide a pulse according to the comparison result; and The control circuit can turn on the switchable current source when the pulse occurs. 8. The line voltage detection circuit as claimed in claim 7, wherein the control circuit receives a clock signal, and the control circuit can turn on the switchable current source when an edge of the clock signal occurs. 9. The line voltage detection circuit as claimed in claim 7, wherein the single pulse generator comprises: A defibrillation circuit (debounce circuit), when the comparison result is stable beyond a preset defibrillation time, the defibrillation circuit can pass the comparison result as a confirmation signal; and The logic circuit generates the pulse according to the comparison result and the confirmation signal. 10. The line voltage detection circuit as claimed in claim 9, further comprising: The brown-out protection circuit causes the power controller to stop the power conversion of the power supply when the confirmation signal is a first logic value exceeding a first preset time. 11. The line voltage detection circuit as claimed in claim 10, further comprising: A brown-in brake circuit is used to enable the power supply to start power conversion when the confirmation signal is a second logic value.