CN107978628A - A kind of GaN transistor for covering nano-pillar potential barrier and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN transistor covered with a nanocolumn barrier and a preparation method thereof. _{AlxGa1 -xN} alloy nanocolumns are distributed on the surface of the barrier layer of the transistor, and the nanocolumn and the screw in the barrier layer One-to-one correspondence between dislocations. The present _invention can not _only avoid the formation of V-type defects at the termination of screw dislocations but also form 1-3nm Al _x Ga _1‑x N alloy nanopillars. Since the alloy nanopillars fill the V-shaped defects at the termination of the screw dislocation on the barrier surface, the effective barrier thickness at the termination of the screw dislocation is increased, thereby effectively suppressing the gate leakage current and improving the withstand voltage characteristics of the transistor.

Description

A GaN transistor covered with nanocolumn barrier and its preparation method

technical field

The invention relates to the growth of semiconductor materials and the manufacture of semiconductor devices, in particular to a GaN-based transistor covered with nanocolumns and a barrier growth method thereof.

Background technique

Gallium nitride-based high electron mobility transistor (HEMT) is a heterojunction formed by Al _x Ga _1-x N and GaN, and the interface spontaneous polarization and piezoelectric polarization of Al _x Ga _1-x N/GaN heterojunction The discontinuity forms remnant polarization charges and thus a high concentration of two-dimensional electron gas at the interface. The growth technology of high-quality Al _x Ga _1-x N barrier layer is one of the key epitaxial technologies for GaN-based transistors. GaN-based HEMTs have the advantages of high two-dimensional electron gas (2DEG) concentration, high mobility, and strong breakdown electric field, and are widely used in high-frequency and high-voltage microwave devices.

At present, it is very difficult to obtain high-quality and large-size GaN substrates and the price is very expensive. Therefore, the growth of GaN epitaxial materials is generally achieved by heterogeneous epitaxy on silicon carbide, sapphire and silicon substrates. Due to the existence of lattice mismatch, there are a large number of threading dislocations (10 ⁶ -10 ⁹ /cm ² ) in GaN heteroepitaxial materials, and these dislocation defects also affect the electrical characteristics and device reliability of GaN transistors. Threading dislocations in heteroepitaxially grown GaN materials include edge dislocations, partial dislocations and screw dislocations, among which screw dislocations have the greatest influence on the electrical characteristics of devices. Screw dislocations usually form V-shaped defects on the surface of the barrier to reduce the effective thickness of the barrier. At the same time, there are usually a large number of defect vacancies in the center of the screw dislocation, which will form leakage channels and electrical breakdown channels under high voltage under the gate electrode.

In order to reduce the impact of screw dislocation defects on device performance, it is generally grown on a SiC substrate with a small lattice mismatch, using a complex buffer layer structure, and using a lateral epitaxial growth method to filter threading dislocations to reduce the potential barrier. Layer screw dislocation density and other methods, the above method is high cost, complex process and poor controllability.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, and provide a transistor and its preparation method in which the potential barrier covers the nano-column by optimizing the growth conditions of the potential barrier.

The technical solution adopted by the present invention to solve its technical problems is:

A GaN transistor covering a nanocolumn barrier, the transistor includes a substrate, a buffer layer, a channel layer and a barrier layer covering a nanocolumn from bottom to top, and the barrier layer is provided with a source, a drain and a gate , and the gate is located between the source and the drain; the channel layer is formed by GaN heteroepitaxial growth, the barrier layer is formed by Al _x Ga _1-x N heteroepitaxial growth, and the surface of the barrier layer Al _x Ga _1-x N alloy nanocolumns are distributed, where 0<x<1; the nanocolumns correspond to the screw dislocations in the barrier layer one by one.

Optionally, the height of the nanocolumns is 1-3 nm.

Optionally, the density of the nanocolumns is 10 ^{6 -10 9} /cm ² .

Optionally, the Al composition of the _{AlxGa1 -xN} barrier layer is 15%-22%.

Optionally, the source, drain and gate are made of metal, and the source and drain form an ohmic contact with the barrier layer, and the gate forms a Schottky contact with the barrier layer.

A preparation method of the above-mentioned GaN transistor covered with a nanocolumn barrier comprises the following steps:

(1) forming a buffer layer on a substrate;

(2) growing a GaN channel layer heteroepitaxially on the buffer layer;

(3) Heteroepitaxially growing an _{AlxGa1 -xN} barrier layer covering the nanocolumns on the channel layer by MOCVD, the growth conditions are: TMGa is 180-300sccm, TMAl is 350-800sccm, _NH3 The flow rate is 8000-12000sccm, and the surface temperature of epitaxial growth is 1000-1150°C, so that nano-pillars are formed one-to-one at the termination of screw dislocations on the surface of the barrier layer;

(4) forming a source electrode and a drain electrode on the surface covering the nanocolumn barrier layer;

(5) A gate region is defined between the source and the drain to form a gate.

Optionally, in step (3), the growth conditions of the barrier layer are: the surface temperature is 1070° C., the flow rate of TMAl is 400 sccm, the flow rate of TMGa is 230 sccm, and the flow rate of NH3 is 9000 sccm.

Optionally, the growth rate of the barrier layer is 1.8 μm/h-3 μm/h.

Optionally, step (2) specifically includes the following sub-steps: Ti/Al/Ni/Au multi-metal layers are respectively evaporated on the two regions of the surface of the barrier layer by electron beam evaporation, wherein the The thicknesses of Ti/Al/Ni/Au are 20/150/70/100nm respectively; annealing at 850-950° C. for 25-50 seconds forms ohmic contact and forms the source and drain.

Optionally, in step (4), the gate is metal, which is deposited on the surface of the barrier layer covering the nanocolumns by magnetron sputtering, ion evaporation or electron beam evaporation and formed with the barrier layer Schottky contacts.

The beneficial effects of the present invention are:

1. The present invention forms an alloy nanocolumn structure at the termination of the screw dislocation on the surface of the barrier by controlling the growth conditions of the _{AlxGa1 -xN} barrier layer, because the alloy nanocolumn fills the vacancy heterogeneous gate of the screw dislocation center During the electrode annealing process, the electrode material diffuses in the dislocation center to reduce the gate leakage channel.

2. The alloy nanocolumn structure is formed by the termination of the screw dislocation on the barrier surface, which effectively increases the effective barrier thickness at the termination of the screw dislocation to avoid the breakdown of the device through the screw dislocation under high voltage, thereby improving the high-voltage working characteristics of the device.

3. The manufacturing method is simple, there is no special process requirement, and the controllability is strong, which can effectively reduce the cost of epitaxy and improve the high-voltage characteristics of the device, and is suitable for actual production and application.

Description of drawings

Fig. 1 is the schematic cross-sectional structure diagram of the embodiment of the present invention;

Fig. 2 is the top view structure diagram of the embodiment of the present invention;

Fig. 3 is a schematic cross-sectional view of a covered nanocolumn barrier according to an embodiment of the present invention;

Fig. 4 is a schematic cross-sectional view of an uncovered nanocolumn barrier according to an embodiment of the present invention;

Fig. 5 is the AFM figure that has covered nanocolumn barrier surface of the embodiment of the present invention;

Fig. 6 is an AFM image of the surface of the barrier-free nano-column according to the embodiment of the present invention.

Detailed ways

Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. All the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and their specific proportions can be adjusted according to design requirements. The growth conditions of the barriers covering the nanopillars described herein are only examples, and it is still possible to form a barrier structure covering the nanopillars by changing a single condition, which is within the disclosure scope of this specification. The size and number of components in the device manufacturing process described in this article are only examples, and can be adjusted according to actual design requirements.

With reference to Fig. 1 and Fig. 2, a kind of GaN transistor that covers the barrier of nanocolumn, comprises the barrier layer 4 that comprises substrate 1, buffer layer 2, channel layer 3 and covers nanocolumn 5 from bottom to top, barrier layer 4 A source 6, a drain 7 and a gate 8 are arranged on it, and the gate 8 is located between the source 6 and the drain 7; the channel layer 3 is formed by GaN heteroepitaxial growth, and the barrier layer 4 It is formed by Al _x Ga _1-x N heteroepitaxial growth, and Al _x Ga _1-x N alloy nanocolumns 5 are distributed on the surface of the barrier layer 4, wherein 0<x<1; the nanocolumns 5 and the barrier layer The screw dislocations in 4 correspond one-to-one. Its preparation method comprises the following steps:

1) Growth of GaN channel layer and buffer layer: use metal organic chemical vapor deposition (MOCVD) to grow buffer layer 2 (nucleation layer and transition layer ), growing a 200nm GaN channel layer 3 at a high temperature (surface temperature 1040°C) on the buffer layer 2, as shown in Figure 1;

2) Continue the epitaxial growth of the Al _x Ga _1-x N barrier layer 4 on 1). In order to form the alloy nanocolumn 5 at the termination of the screw dislocation on the surface of the barrier layer 4, a higher MO flow rate is used, wherein TMGa (Ttrimethylgalli μm ) is 180-300sccm (standard cubic meter per minute), TMAl (Trimethylalμminiμm) is 350-800sccm, while the flow rate of NH ₃ is 8000-12000sccm, and the surface temperature of epitaxial growth is 1000-1150°C; at high MO flow rate and low V/ Under the condition of III ratio, the barrier growth rate is about 1.8μm/h-3μm/h, and the Al composition of the Al _x Ga _1-x N barrier layer is about 15%-22%. 1-3nm nanocolumns 5 are formed at the terminating position, as shown in Figure 1 and Figure 2, wherein the density of the nanocolumns is 10 ^{6 -10 9} /cm ² ;

3) Preparation of source and drain electrodes 6 and 7: Prepare the photoresist pattern required for the source and drain electrodes on the surface of the barrier layer by photolithography (electron beam exposure (EBL), ultraviolet exposure (UVL)), and cover the photoresist epitaxy Evaporate source and drain electrode metal (Ti/Al/Ni/Au, thickness 20nm/150nm/70nm/100nm) on the surface of the sheet, peel off the metal in the stripping solution to obtain the source and drain electrodes, and use the rapid annealing furnace to anneal the source and drain electrodes (annealing temperature 850-950°C, annealing time 35-60s, annealing is nitrogen (nitrogen flow rate 6L/min)); as shown in Figures 1 and 2, source electrode 6, drain electrode 7;

4) Prepare the gate metal: prepare the photoresist pattern required for the gate electrode on the surface of the barrier layer by photolithography (electron beam exposure (EBL), ultraviolet exposure (UVL)), and cover the photoresist with magnetron sputtering equipment Evaporate the gate electrode (TiN, thickness 150-200nm) on the surface of the epitaxial wafer, peel off the metal in the stripping solution to obtain the gate electrode, and anneal the gate electrode in an annealing furnace (annealing temperature 600-800°C, annealing time 20-60min, annealing atmosphere is Nitrogen (nitrogen flow rate 20L/min)); as shown in Figures 1 and 2, the gate electrode 8.

The implementation of the present invention will be further described by way of example with specific application examples below:

example

(1) A channel layer and a buffer layer are grown on a 1mm 6-inch silicon substrate by MOCVD. The buffer layer includes a 200nm high-temperature (surface temperature 1100°C) AlN nucleation layer, a 1.5μm composition-graded Al _x Ga _1-x N transition layer (Al _0.75 Ga _0.25 N-200nm, Al _0.55 Ga _0.45 N-400nm , Al _0.25 Ga _0.75 N-900nm, surface temperature 1060°C) and then grow a 2.0μm GaN high resistance layer (surface temperature 980°C). The channel layer is a 200nm high-temperature (surface temperature of 1060°C) GaN layer;

(2) Continue to epitaxially grow an AlxGa1-xN barrier layer on the surface of the GaN channel layer in (1) by MOCVD. Using a higher MO flow rate, TMGa is 220 sccm, TMAl is 400 sccm and NH ₃ flow rate is 9000 sccm; under the condition of high MO flow rate, V/III ratio is 270, the barrier growth rate is about 2.2 μm/h, Al _x Ga ₁ The Al component of the _-x N barrier layer is about 20%, and a 1-2nm nanocolumn with a diameter of 120-200nm is formed at the termination of the screw dislocation under high growth rate conditions, as shown in Figure 5;

(3) The photoresist pattern required for the source and drain electrodes on the surface of the epitaxial wafer covering the nanocolumn barrier is indicated by ultraviolet lithography (the distance between the source and drain electrodes is 25 μm, the electrode length is 20 μm, and the electrode width is 100 μm). Evaporation equipment evaporates Ti/Al/Ni/Au (20nm/150nm/70nm/100nm) on the surface of the photoresist; strips the metal in the stripping solution to obtain the source and drain electrodes, and uses the rapid annealing furnace to heat the source and drain electrodes at 900°C Annealing for 50s (nitrogen flow rate 6L/min)) to form ohmic contact between the source and drain electrodes and the barrier;

(4) Prepare the photoresist pattern required for the gate electrode between the source and drain electrodes on the surface of the barrier layer by ultraviolet exposure (the gate length is 2 μm, the distance from the source is 3 μm, the distance from the drain is 15 μm, and the gate width is 100 μm). The sputtering equipment evaporates the gate electrode (TiN, thickness 180nm) on the surface of the epitaxial wafer covered with photoresist, peels off the metal in the stripping solution to obtain the gate electrode, and uses a tubular annealing furnace to anneal the gate electrode under a nitrogen atmosphere at 650°C for 40min. The gate electrode and the barrier form a Schottky contact;

Under the conditions of the usual low growth rate and high V/III ratio, V-type defects 5' will be formed at the termination of the screw dislocation on the surface of the barrier layer 4', as shown in Figure 4 and Figure 6 (wherein Figure 4 is a schematic diagram of the structure , Figure 6 is an atomic force micrograph of the epitaxial wafer surface). By adopting a low V/III ratio and a high-speed barrier growth method, alloy nanocolumns can be formed at the termination of screw dislocations on the barrier surface, as shown in Figure 3 and Figure 5 (wherein Figure 3 is a schematic diagram of the structure, and Figure 5 is the epitaxial wafer surface atomic force micrograph). Since the nanocolumn structure formed at the termination of the screw dislocation on the surface of the barrier can effectively inhibit the formation of the leakage channel under the gate electrode, and at the same time, the nanocolumn increases the effective barrier thickness of the screw dislocation attachment, and the barrier breakdown characteristics between the drain and the gate will also be improved.

The method disclosed in the present invention can also be used for self-organized growth of _{AlxGa1 -xN} alloy nanocolumns and for inhibiting GaN epitaxial thread dislocation propagation and improving epitaxial quality.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., such as simple changes to the process parameters in the examples, shall be included within the protection scope of the present invention.

Claims (10)

1. A GaN transistor covering a nanocolumn barrier, characterized in that: the transistor comprises a substrate, a buffer layer, a channel layer and a barrier layer covering a nanocolumn from bottom to top, and the barrier layer is provided with a source , the drain and the gate, and the gate is located between the source and the drain; the channel layer is formed by GaN heteroepitaxial growth, and the barrier layer is formed by _{AlxGa1 -xN} heteroepitaxial growth , and Al _x Ga _1-x N alloy nanocolumns are distributed on the surface of the barrier layer, where 0<x<1; the nanocolumns correspond to the screw dislocations in the barrier layer one by one. 2 . The GaN transistor covering the nanocolumn barrier according to claim 1 , wherein the height of the nanocolumn is 1-3 nm. 3 . The GaN transistor covered with nanocolumn barriers according to claim 1 , wherein the density of the nanocolumns is 10 ⁶ /cm ² -10 ⁹ /cm ² . 4 . The GaN transistor covering the nanocolumn barrier according to claim 1 , wherein the Al composition of the Al _x Ga _1-x N barrier layer is 15%-22%. 5. The GaN transistor covering the nanocolumn barrier according to claim 1, characterized in that: the source, the drain and the gate are made of metal and the source and the drain form an ohmic contact with the barrier layer, The gate forms a Schottky contact with the barrier layer. 6. A method for preparing a GaN transistor covering a nanocolumn barrier as claimed in any one of claims 1 to 5, characterized in that it comprises the following steps: (1) forming a buffer layer on a substrate; (2) growing a GaN channel layer heteroepitaxially on the buffer layer; (3) Heteroepitaxially growing an _{AlxGa1 -xN} barrier layer covering the nanocolumns on the channel layer by MOCVD, the growth conditions are: TMGa is 180-300sccm, TMAl is 350-800sccm, _NH3 The flow rate is 8000-12000sccm, and the surface temperature of epitaxial growth is 1000-1150°C, so that nano-pillars are formed one-to-one at the termination of screw dislocations on the surface of the barrier layer; (4) forming a source electrode and a drain electrode on the surface covering the nanocolumn barrier layer; (5) A gate region is defined between the source and the drain to form a gate. 7. The preparation method according to claim 6, characterized in that: in step (3), the growth conditions of the barrier layer are: the surface temperature is 1070° C., the flow rate of TMAl is 400 sccm, the flow rate of TMGa is 230 sccm, and the flow rate of _NH is 9000 sccm. 8. The preparation method according to claim 6, characterized in that: the growth rate of the barrier layer is 1.8 μm/h-3 μm/h. 9. The preparation method according to claim 6, characterized in that: step (2) specifically comprises the following sub-steps: The Ti/Al/Ni/Au multi-metal layer is evaporated on the two regions of the surface of the barrier layer by electron beam evaporation, wherein the thicknesses of the Ti/Al/Ni/Au are 20/150 /70/100nm; Annealing at 850-950° C. for 25-50 seconds to form ohmic contacts and form the source and drain. 10. The preparation method according to claim 6, characterized in that: in step (4), the grid is metal, which is deposited on the covered nanometer by magnetron sputtering, ion evaporation or electron beam evaporation. The surface of the barrier layer of the pillar and forms a Schottky contact with the barrier layer.