CN107968092B

CN107968092B - Intermetallic compound protective layer in 3D NAND and forming method thereof

Info

Publication number: CN107968092B
Application number: CN201711139432.0A
Authority: CN
Inventors: 刘力恒; 高晶; 杨川; 严萍; 丁蕾; 喻兰芳; 张森; 许波
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2018-12-14
Anticipated expiration: 2037-11-16
Also published as: CN107968092A

Abstract

Provided are an intermetallic compound (IMC) protective layer in 3D NAND and a method for forming the same. The IMC protection layer is formed in the source selection cell trench, between the TiN adhesion layer and the tungsten (W) gate, which is composed of hafnium Hf and tungsten W prepared by HfF ₄ , WF ₆ and other auxiliary gases. The deposited metal layer is an IMC HfW ₂ layer formed by high temperature heat treatment above 1000°C. The IMC HfW ₂ layer can prevent the tungsten diffusion of the tungsten gate from entering the silicon substrate, thereby avoiding the breakdown voltage failure problem and improving the electrical performance of 3D NAND.

Description

Intermetallic compound protective layer in 3D NAND and forming method thereof

Technical field

This application involves three-dimensional (3D) memory technology fields, more specifically, the metal being related in a kind of 3D NAND Between compound protective layer and forming method thereof.

Background technique

With the fast development of flash memory, 3D flash memory structure is rapidly developed, and NAND-type flash memory is a kind of to compare hard disk Driver preferably stores equipment, as people pursue the non-volatile memory product of low in energy consumption, light weight and excellent performance, 3D Nand flash memory is even more to be widely used in electronic product.

In existing 3D NAND preparation process, the preparation for being related to bottom selection gate (BTM) generallys use following technique: As shown in Fig. 1 (a), the bottom gate oxide layers of steam in situ growth (ISSG) technique preparation bottom selection gate (BSG) are utilized； After forming storage unit, source electrode groove is formed via etching, and the side gate oxide of BSG is formed as shown in Fig. 1 (b) Layer；The last depositing tungsten metal that formed in the trench after barrier layer as shown in Fig. 1 (c) is using as tungsten grid 103.And ISSG technique The major defect of the BSG oxide skin(coating) of formation is that the BSG oxide skin(coating) in the drain selection area after the gate oxidation of the side BSG is blocked up. In order to solve the defect, NH is generallyd use₃Processing+high temperature oxidation process processing mode is to improve the BSG oxygen in drain selection area Compound layer thickness, but this will lead to BSG oxide quality it is bad and have an adverse effect to chip Acceptance Test performance, simultaneously It is found by the applicant that NH₃Although BSG oxide skin(coating) that processing+high temperature oxidation process processing mode overcomes drain selection area is blocked up The problem of, but will lead to BSG and generate connecting lead wire (CW) breakdown voltage Problem of Failure, this diffusion for being likely due to tungsten causes 's.

Summary of the invention

To solve the above-mentioned problems, the present invention provides the intermetallic compound protective layers and its shape in a kind of 3D NAND At method, spread and forming a kind of intermetallic compound protective layer to prevent tungsten from passing through the BSG oxide in drain selection area Into silicon substrate.

The purpose of the present invention is what is be achieved through the following technical solutions:

Intermetallic compound (IMC) protective layer forming method in a kind of 3D NAND is provided, following step is specifically included It is rapid:

S1: the oxide structure of the bottom selection gate of drain selection unit is prepared on a semiconductor substrate, is then made Standby Al₂O₃The laminated construction of gate blocks layer and TiN adhesion layer；

S2: IMC protective layer is formed on above-mentioned laminated construction；

S3: the deposits tungsten grid on the IMC protective layer；

Wherein the IMC layers is IMC HfW₂Layer.

Further, above-mentioned IMC protective layer forming method forms above-mentioned IMC protective layer in step S2 and specifically includes: first The co-deposited layer of hafnium Hf and tungsten W are formed, is then heated at high temperature above-mentioned co-deposited layer to form IMC layers.

Further, in above-mentioned IMC protective layer forming method, formed above-mentioned co-deposited layer chemical formula such as following formula (1) and (2):

HfF₄→Hf+F₂ (1)

WF₆→W+F₂ (2)。

Further, in above-mentioned IMC protective layer forming method, the implementation temperature of above-mentioned high-temperature heating is greater than 1000 DEG C.

Further, in above-mentioned IMC protective layer forming method, the oxide of the bottom selection gate is prepared in step S1 Structure specifically includes: the bottom gate oxide of above-mentioned bottom selection gate is prepared using steam growth (ISSG) technique in situ； The side gate oxide of above-mentioned bottom selection gate is prepared in the source electrode groove etched.

Further, in above-mentioned IMC protective layer forming method, above-mentioned Al is prepared using atomic layer deposition (ALD) technique₂O₃ Gate blocks layer.

Further, in above-mentioned IMC protective layer forming method, step S1 further comprises: selecting forming above-mentioned bottom After the oxide structure of grid, using NH₃Processing is handled with high temperature oxidation process.

Also provided is intermetallic compound (IMC) protective layer in a kind of 3D NAND, which includes being formed Storage unit and drain selection unit on a semiconductor substrate, the IMC protective layer are formed in above-mentioned drain selection unit, should Drain selection unit further comprises the bottom selection grid being made of bottom gate oxide and side gate oxide, in above-mentioned source electrode It also successively include Al in the groove of selecting unit₂O₃Gate blocks layer, TiN adhesion layer and tungsten grid, in which: above-mentioned IMC layers of setting Between above-mentioned TiN layer and tungsten grid, and this IMC layers is IMC HfW₂Layer.

Further, in above-mentioned IMC protective layer, the IMC layers by including HfF₄And WF₆Gas preparation.

Further, in above-mentioned IMC protective layer, above-mentioned bottom gate oxide is that steam in situ grows (ISSG) oxidation Object.

Further, in above-mentioned IMC protective layer, the oxide structure of bottom selection gate is via NH₃Processing and high temperature Oxidation technology processing.

The present invention has the advantages that by providing a kind of intermetallic compound in the bottom gate configuration in 3D NAND Protective layer can prevent tungsten from passing through the BSG oxide in drain selection area and diffuse into silicon substrate, so that drain selection area BSG oxide will not be blocked up, and can prevent tungsten spread and cause BSG structure generate connecting lead wire breakdown voltage failure ask Topic.

Detailed description of the invention

By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:

Fig. 1 (a)~1 (c) shows the preparation work of bottom selection gate involved in 3D NAND technique in the prior art Skill；

Fig. 2 (a)~2 (c) is the shape of the intermetallic compound protective layer in a kind of 3D NAND provided by present embodiment At method；

Fig. 3 is HfW₂Lattice structure；

Fig. 4 is IMC HfW₂Layer diffuses to the barrier effect schematic diagram of silicon substrate to the tungsten in tungsten metal layer；

Fig. 5 is hafnium tungsten binary phase diagraml.

Specific embodiment

The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs The range opened is fully disclosed to those skilled in the art.

Fig. 2 (a) -2 (c) shows the intermetallic compound in a kind of 3D NAND provided by the application embodiment and protects The forming method of sheath, wherein the forming method includes:

S1: preparing the storage unit and BSG gate oxidation structure of 3D NAND on a semiconductor substrate, wherein utilizing original The bottom gate oxide layers of position steam growth (ISSG) technique preparation bottom selection gate (BSG), and the source electrode formed in etching The side gate oxide layers of BSG are prepared in groove；Then as shown in Fig. 2 (a), atomic layer deposition is utilized in source electrode groove (ALD) technique forms high dielectric oxidation aluminium Al₂O₃Layer and be subsequently formed TiN sedimentary, so as to form Al₂O₃Gate blocks The laminated construction 101 of layer and TiN adhesion layer.

Wherein due to there is a problem of that the BSG oxide skin(coating) in drain selection area is blocked up, in order to improve the thickness of BSG oxide skin(coating) Degree, needs to implement NH after forming side gate oxide layers₃Processing+high temperature oxidation process processing.

S2: in Al as shown in Fig. 2 (b)₂O₃With formation IMC layer 102 on TiN laminated construction 101.The IMC layer 102 utilizes two Step process preparation, is initially formed metal co-deposition layer, then forms IMC structure through Overheating Treatment.

The lattice structure of IMC structure is tightly packed and has specific chemical bond, and the chemical bond is between metallic bond and covalently Between key.Exactly because its specific lattice structure, therefore this compact continuous IMC layers can be effectively prevented metal diffusion, Such as the diffusion of tungsten.It is not that any metal mixture can form IMC structure, the preparation of IMC structure must be according to heating power Theory is realized.And in the 3D NAND structure, IMC layers of preparation are between TiN layer and tungsten layer, therefore IMC layers of the characteristic must It must match with above-mentioned adjacent TiN layer, tungsten layer.By selection, since metal hafnium Hf and tungsten W has close atomicity, The two has similar characteristic.In addition, being capable of forming HfW via processing between hafnium Hf and tungsten W₂Intermetallic compound, HfW₂Metal Between compound lattice structure as shown in figure 3, its with compound cubic lattice structure so that the HfW₂Intermetallic compound It is capable of the diffusion of effectively barrier metal tungsten, it is shown in Figure 4.Therefore before tungsten gate deposition, hafnium Hf and tungsten W is selected to prepare Form HfW₂Intermetallic compounds layer.

S3: finally, the shown deposits tungsten grid 103 on the IMC layer of such as Fig. 2 (c).

In above-mentioned steps S2, in order to form IMC HfW₂It may first have to form the co-deposited layer of hafnium Hf Yu tungsten W.Tool For body, before forming tungsten sedimentary, HfF is utilized₄、WF₆The metal of hafnium Hf Yu tungsten W are formd with other auxiliary gas preparations Co-deposited layer.Shown in the chemical formula wherein reacted such as following formula (1) and (2):

HfF₄→Hf+F₂ (1)

WF₆→W+F₂ (2)。

Then it needing to carry out high-temperature heat treatment to above-mentioned metal co-deposition layer, Fig. 5 shows the binary phase diagraml of Hf and W, Abscissa is the component of Hf and W, and ordinate is the temperature value as unit of Kelvin.According to diagram, the Hf and W of different component Metal is capable of forming body-centered cubic lattic (bcc) and close-packed hexagonal structure (hcp) under high-temperature process, and in specific components and At a temperature of, it will be able to IMC HfW needed for forming the application₂Structure.And as shown in the figure in order to form compact continuous IMC HfW₂ Structure, the heat treatment must be implemented at 1000 DEG C or more.Shown in such as following formula of chemical formula at this time (3):

Hf+W→HfW₂(3)。

3D NAND structure shown in Fig. 2 (c) is obtained using above-mentioned preparation method comprising: storage unit and source electrode select Unit is selected, further includes side including the bottom gate oxide that ISSG technique is formed in the bottom selection grid of drain selection unit Gate oxide also successively includes Al in the groove of drain selection unit₂O₃Gate blocks layer, TiN adhesion layer and tungsten grid, and An IMC layers is provided between the TiN layer and tungsten grid, the IMC layers is HfW₂Layer utilizes HfF₄、WF₆Gas is assisted with other Body is formed.Due to being prepared for the IMC HfW in the 3D NAND structure₂Layer, therefore in order to improve the thickness of BSG oxide skin(coating) And implement NH₃After processing+high temperature oxidation process processing, it still is able to utilize the IMC HfW₂Layer effectively stops tungsten grid In tungsten diffuse into silicon substrate so that the 3D NAND structure avoid generate connecting line Problem of Failure.

The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim Subject to enclosing.

Claims

1. a method for forming an intermetallic compound (IMC) protective layer in 3D NAND, is characterized in that, comprises the steps:

S1: Prepare the oxide structure of the bottom selection gate of the source selection unit on the semiconductor substrate, and then prepare the laminated structure of the Al ₂ O ₃ gate barrier layer and the TiN adhesion layer (101);

S2: forming an intermetallic compound protective layer (102) on the above laminated structure (101);

S3: Depositing a tungsten gate (103) on the intermetallic compound protective layer (102);

Wherein the intermetallic compound protective layer (102) is an intermetallic compound HfW ₂ layer.

2. IMC protective layer forming method according to claim 1, is characterized in that, in step S2, forms above-mentioned IMC protective layer (102) specifically comprises: at first forming the codeposition layer of hafnium (Hf) and tungsten (W), then The above co-deposited layer is heated at high temperature to form an IMC layer.

3. IMC protective layer forming method according to claim 2, is characterized in that, the chemical formula that forms above-mentioned co-deposition layer is as follows formula (1) and (2):

HfF ₄ →Hf+F ₂ (1)

WF ₆ →W+F ₂ (2).

4. The method for forming the IMC protective layer according to claim 2, characterized in that, the implementation temperature of the above-mentioned high-temperature heating is greater than 1000°C.

5. The method for forming an IMC protective layer according to any one of claims 1 to 3, wherein preparing the oxide structure of the bottom selection gate in step S1 specifically comprises: using an in-situ water vapor growth (ISSG) process to prepare The bottom gate oxide of the bottom selection gate is prepared; the side gate oxide of the bottom selection gate is prepared in the etched source trench.

6 . The method for forming the IMC protection layer according to any one of claims 1 to 3 , characterized in that the Al ₂ O ₃ gate barrier layer is prepared by using an atomic layer deposition (ALD) process.

7. The method for forming an IMC protective layer according to any one of claims 1 to 3, characterized in that step S1 further comprises: after forming the oxide structure of the bottom selection gate, _NH3 treatment and high temperature oxidation process are used to carry out deal with.

8. An intermetallic compound (IMC) protection layer in a 3D NAND, the 3D NAND includes a memory cell and a source selection unit formed on a semiconductor substrate, the intermetallic compound protection layer is formed in the above-mentioned source selection unit , the source selection unit further includes a bottom selection gate composed of a bottom gate oxide and a side gate oxide, and the trench of the above source selection unit further includes an Al ₂ O ₃ gate barrier layer, a TiN adhesion layer and tungsten gate, characterized in that: the intermetallic compound protection layer is arranged between the above TiN layer and the tungsten gate, and the intermetallic compound protection layer is an intermetallic compound HfW ₂ layer.

9. The IMC protective layer according to claim 8, characterized in that, the IMC layer is prepared from a gas comprising _HfF4 and _WF6 .

10. The IMC protective layer according to claim 8 or 9, wherein the bottom gate oxide is an in-situ water vapor grown (ISSG) oxide.