CN107967928A - A kind of flash chip life-span prediction method based on mathematical model - Google Patents
A kind of flash chip life-span prediction method based on mathematical model Download PDFInfo
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Abstract
The invention belongs to flash chip forecasting technique in life span, more particularly, to a kind of flash chip life-span prediction method based on mathematical model.The present invention tests the physical message and life information of systematic collection sample flash chip by flash chip first, then the data message obtained with intelligent algorithm to test carries out calculation process and obtains flash chip Life Prediction Model, the physical message of flash chip to be predicted is obtained finally by a small amount of test, physical message input prediction model is obtained into the bimetry value of flash chip.The flash memory test sample method proposed in the present invention is tested using the random data of belt restraining as test data set, can the data manipulation of more efficient simulation flash chip in actual use, obtained flash memory physical message and life information be more valuable.
Description
Technical field
The invention belongs to flash chip forecasting technique in life span, more particularly, to a kind of flash chip longevity based on mathematical model
Order Forecasting Methodology.
Background technology
In hyundai electronics information industry, memory has very heavy always as the carrier that data are stored in electronic equipment
The status wanted.At present, the memory of in the market is broadly divided into：Volatile memory and nonvolatile memory.Flash chip is
A kind of nonvolatile memory, it can preserve data for a long time after a power failure, and have that data transmission bauds is fast, is produced into
The advantages that this is low, memory capacity is big, so being widely used among electronic equipment.
At present, due to continuous progressive, the reduction of distance and the oxidated layer thickness between storage unit of semiconductor fabrication process
Reduction make in flash chip intrinsic wrong increasingly severe, what traditional error correction code approach can not meet flash chip can
By property demand, the integrity problem of flash memory has become the important topic of current storage research field.The service life of flash memory
The number of operations being able to carry out of flash memory before failure is represented, is the most important parameter index of flash chip.Predict the surplus of flash memory
Remaining service life, can allow flash memory device user using the loss state that memory is understood during equipment, avoid because
Memory cell fail and caused by data be lost in.Meanwhile the flash memory remaining life that memory user can also obtain according to prediction
Information, changes storage data policy and efficiently uses flash chip preservation data.
The content of the invention
The above-mentioned technical problem of the present invention is mainly what is be addressed by following technical proposals：
A kind of flash chip life-span prediction method based on mathematical model, it is characterised in that according to one kind of flash chip
The life prediction value of the combined prediction flash chip of physical quantity or several physical quantitys.The flash chip physical quantity includes：Flash memory
The programming time of storage chip, read access time, erasing time, program current, reading electric current, erasing electric current, threshold voltage distribution
And error rate.The specific steps of the method include：
Step 1, sample drawn is as sample flash memory from flash memory products set, in flash memory products set in addition to sample flash memory
For flash memory to be tested, and sample flash chip be connected with flash memory test system and starts test collection to establish the flash chip service life pre-
Survey the flash chip physical message and flash chip life information needed for model；Flash chip to be tested and flash memory are tested at the same time
System connection starts the flash chip physical message and flash chip life information needed for test collection prediction model；
Step 2, the combination of a kind of physical message or several physical messages that are obtained testing is as mathe-matical map in algorithm
The input variable of relation, output variable of the flash chip life prediction value as mathe-matical map relation, is handled by intelligent algorithm
Data founding mathematical models；
Step 3, test flash memory Life Prediction Model, using the flash chip physical quantity needed for prediction model as life prediction
The input of model, the remaining lifetime value of the output valve prediction target flash product of mathematic(al) expectation prediction model.
Preferably, in the step 1, sample flash memory is necessary for the flash chip of same type under same manufacturing process；
The chip sample of identical quantity is randomly selected from the chip of different batches, to ensure the diversity of sample.Wherein, batch of sampling
Secondary is to randomly select, and sample size can be sampled batch flash chip total amount 1 percent, also, flash memory tests system
Including host computer test control system and flash memory control module.Wherein, host computer test system writes journey by computer language
Sequence system is realized；Flash memory control module is realized by FPGA.
Preferably, in the step 1, flash chip physical message includes：Flash chip is from beginning to use to can not be just
The programming time of block, read access time, erasing time, program current, reading electric current, wiping in normal flash memory storage chip interior during use
Except electric current, threshold voltage distribution and error rate information.In the step 2, service life of flash memory predicts the defeated of mathe-matical map relation
Enter one or more of combinations that variable is above-mentioned physical message.In the step 1, flash chip life information is flash chip
From begin to use to can not during normal use interior experience program/erase operation cycle number.
It is preferably, described
The acquisition modes of flash chip memory block programming time are：Programming time is set to record mould in flash memory test system
Block；The programming time logging modle clock cycle that record passes through while flash memory starts to write data manipulation is receiving flash memory core
Stop recording clock periodicity after piece returned data programming complement mark；Programming time value is multiplied by volume for clock cycle duration
Journey clock periodicity.
The acquisition modes of flash chip memory block erasing time are with programming time acquisition modes：By the wiping in test system
Except the lasting clock periodicity of time recording module record erasing operation, erasing time value is multiplied by wiping for clock cycle duration
Except clock periodicity.Flash memory chip storage unit threshold voltage distribution acquisition modes be：Test system is sent to flash chip
The reading reference voltage that flash memory is altered in steps in READ-RETRY command sets reads simultaneously data according to reading data Data-Statistics threshold voltage
Distribution.
Flash chip storage block error rate acquisition modes be：Test system, which performs flash chip, reads data manipulation from sudden strain of a muscle
Middle reading data are deposited, the test data of the data of reading and write-in is carried out contrast mistake of statistics data amount check by test system, wrong
Rate is number of errors divided by total data amount check by mistake.
Preferably, in the step 1, test collection flash chip physical message is specific with flash chip life information
Step includes：
Step 5.1, the randomly drawing sample chip from flash chip set, sample flash chip and test system are connected
Connect.
Step 5.2, randomly choose memory block from each sample flash chip, is sent out by the system of testing to flash memory storage block
Test data set is sent, write-in data manipulation is performed to flash memory storage block.
Step 5.3, after having sent test data vector, keep the data stored in flash memory storage block for a period of time, protects
Time length is deposited to be determined according to the type of flash chip；Flash chip is performed by the system of testing and reads data manipulation, test system
System will read data compared with the test data sent, records and preserves error data information, is not preserved if not malfunctioning；
After having preserved error message, erasing data manipulation performs flash chip by the system of testing.
Time that step 5.4, the operation for repeating step 5.2 and step 5.3, recording step 5.2 and step 5.3 operate
Number；When number of operations reaches setting value, each memory block of sample flash memory in the last step 5.2 operation of test system record
Write the duration of data manipulation and preserve recorded Duration Information；Meanwhile test the last step of system record
The duration of each memory block erasing data manipulation of sample flash memory and recorded duration letter is preserved in rapid 5.3 operation
Breath.
Step 5.5, the threshold voltage distribution by testing systematic survey flash chip unit, record the threshold of simultaneously storage unit
Threshold voltage distributed intelligence；The step is optional step, if prediction object does not have READ-RETRY functions in testing procedure not
Including the step.
Step 5.6, the data error rate information tested system statistics and preserve each memory block of flash chip.
Step 5.7, repeat step step 5.4 arrive step 5.6, until flash chip reaches lifetime limitation；Test system is united
Count the program/erase operation cycle number of flash chip.
In the present invention, step 2 is the intelligent algorithm using genetic programming algorithm as founding mathematical models, institute in the present invention
The intelligent algorithm stated is not limited to the algorithm.Service life of flash memory value refers to programming/wiping that flash memory products can perform before disabling
Except periodicity, specific steps include：
Step 6.1, computer program initialization life prediction function set；Life prediction function screening equation is set.
Step 6.2, by test data substitute into life prediction function set in each function；Function result is calculated, that is, is dodged
Deposit chip life prediction value；The flash chip life prediction value being calculated actual life value corresponding with test data is substituted into
Fitness equation, life prediction function is screened according to fitness equation calculation result.
Step 6.3, on the basis of the life prediction function set by screening, it is new using the generation of gene programmed method
Function set.
Step 6.4, the operation that step 6.2 and step 6.3 are repeated to new function set, number of operations reach setting
Upper limit value when terminate operation；Upper limitation is set according to forecast demand.
Step 6.5, select the predicted value function optimal with actual life value matching degree from set, obtains life prediction number
Learn model.
Life prediction function described in step 6.1 includes operator, coefficient and input variable；Wherein coefficient is calculating
The constant that machine program randomly generates, input variable are programming time, erasing time, threshold voltage distribution and several tests of error rate
Data acquisition system, wherein, threshold voltage is distributed as optional input variable；A kind of test data set represents an input and becomes
Amount, the input variable number that function is included can be set according to forecast demand.Life prediction function is realized by the form of matrix
Set.
Wherein, fitness equation refers to that the absolute value of service life of flash memory predicted value and the difference of test value weights in step 6.2
With.Fitness equation is embodied as：F=ω1|A1-B1|+ω2|A2-B2|+…+ωn|An-Bn|；Wherein, Ai represents prediction
Value；Bi is actual value；ω i are weights, and the value of ω i is more than 0 and is less than or equal to 1；N is total sample number.
The operation of new function set described in step 6.3 includes：Intersection, mutation and the breeding operation of function.The letter
Several crossover operations be specially exchange tree function node, using the function obtained after exchange as new function set into
Member.Mutation operation randomly generates function by computer program, and the function randomly generated is replaced to the expression formula point of former generation's function
Branch obtains new offspring's function.Gene programming breeding operation be the function that will be met the requirements after selection operation by certain probability into
Row replicates, and the function after duplication is as new offspring.
Therefore, the invention has the advantages that：1. the flash memory test sample method proposed in the present invention is using belt restraining
Random data is tested as test data set, being capable of the number of more efficient simulation flash chip in actual use
According to operation, obtained flash memory physical message and life information is more valuable.2. the present invention is using a variety of dependability parameters as the longevity
Order prediction model input, with only using a kind of accuracy of parameter bimetry value compared with the Life Prediction Model of foundation more
It is high.3. the present invention proposes a kind of service life of flash memory prediction side based on the intelligent algorithm modeling technique in current computer realm forward position
Method；Compared with current technology, the advance of this method is based on experimental data to establish flash memory core by intelligent algorithm
Piece life prediction mathematical model prediction service life of flash memory value.
Brief description of the drawings
Fig. 1 is a kind of flow diagram of the flash chip life-span prediction method based on mathematical model of the embodiment of the present invention.
Fig. 2 is a kind of flow chart of reliability of flash memory test method of the embodiment of the present invention.
Fig. 3 is the structure chart that a kind of flash memory of the embodiment of the present invention tests system.
Fig. 4 is a kind of service life of flash memory prediction model modeling procedure based on gene programming of the embodiment of the present invention.
Fig. 5 is the life prediction function structure exemplary plot used in the embodiment of the present invention.
Fig. 6 is the matrix form exemplary plot of life prediction function in the embodiment of the present invention.
Fig. 7 is that gene programs crossover operation exemplary plot in the embodiment of the present invention.
Fig. 8 is that gene programs mutation operation exemplary plot in the embodiment of the present invention.
Fig. 9 is gene programming breeding operation example figure in the embodiment of the present invention.
Embodiment
Below with reference to the embodiments and with reference to the accompanying drawing the technical solutions of the present invention will be further described.
Embodiment：
It is below in conjunction with attached drawing and specifically real in order to enable the above objects, features and advantages of the present invention to become apparent from
Example is applied to be described in detail.
Fig. 1 predicts the flow diagram in flash chip service life, the flow of flash chip life prediction shown in figure for the present invention
Suitable for all flash chip types, detailed explain is carried out to Fig. 1 by embodiment of a kind of flash chip product below
It is bright.
In the present embodiment, using more pole unit nand flash memories (MLC NAND flash) product under certain manufacturing process as survey
Try object and life prediction object.Step S01 as shown in Figure 1, according to following rule extraction sample from the flash memory products set
This：Sample flash memory is necessary for the flash chip of same type under same manufacturing process；Randomly selected from the chip of different batches
The chip sample of identical quantity, to ensure the diversity of sample.Wherein, the batch of sampling is randomly selects, and sample size can be with
To be sampled 1 the percent of batch flash chip total amount.
Step S02, sample flash chip and flash memory test system be connecteds and starts test collection and establishes the flash chip service life
Flash chip physical message and flash chip life information needed for prediction model.The flash chip physical message includes：Dodge
Chip is deposited from beginning to use to can not the programming time of block, erasing time, threshold value in interior flash memory storage chip during normal use
(threshold voltage is distributed as optional thing to the data message that voltage's distribiuting and error rate change under the conditions of increasing in the program/erase cycle
Manage information).
The acquisition modes of flash chip memory block programming time are：Programming time is set to record mould in flash memory test system
Block；The programming time logging modle clock cycle that record passes through while flash memory starts to write data manipulation is receiving flash memory core
Stop recording clock periodicity after piece returned data programming complement mark；Programming time value is multiplied by volume for clock cycle duration
Journey clock periodicity.
The acquisition modes of flash chip memory block erasing time with programming time acquisition modes similarly, by test system
The lasting clock periodicity of erasing time logging modle record erasing operation, erasing time value are multiplied by for clock cycle duration
Wipe clock periodicity.Flash memory chip storage unit threshold voltage distribution acquisition modes be：Test system is sent out to flash chip
The reading reference voltage that flash memory is altered in steps in READ-RETRY command sets is sent to read simultaneously data electric according to data Data-Statistics threshold value is read
Pressure distribution.
Flash chip storage block error rate acquisition modes be：Test system, which performs flash chip, reads data manipulation from sudden strain of a muscle
Middle reading data are deposited, the test data of the data of reading and write-in is carried out contrast mistake of statistics data amount check by test system, wrong
Rate is number of errors divided by total data amount check by mistake.
The flash memory test method used in step S02, its flow are as shown in Figure 2.According to Fig. 2, the specific step of flash memory test
Suddenly it is：
(1) the randomly drawing sample chip from flash chip set, sample flash chip is connected with test system.
(2) memory block is randomly choosed from each sample flash chip, is sent and surveyed to flash memory storage block by the system of testing
Data acquisition system is tried, write-in data manipulation is performed to flash memory storage block.
(3) after having sent test data vector, the data stored in flash memory storage block are kept for a period of time, the holding time
Length is determined according to the type of flash chip；Flash chip is performed by the system of testing and reads data manipulation, test system will be read
Go out data compared with the test data sent, record and preserve error data information, do not preserved if not malfunctioning；Preserve
After error message, erasing data manipulation performs flash chip by the system of testing.
(4) number of the operation of step (2) and step (3), recording step (2) and step (3) operation is repeated；Work as behaviour
When reaching setting value as number, each memory block write-in number of sample flash memory in the last step (2) operation of test system record
According to operation duration and preserve recorded Duration Information；Meanwhile test the last step (3) behaviour of system record
The duration of each memory block erasing data manipulation of sample flash memory and recorded Duration Information is preserved in work.
(5) it is distributed by testing the threshold voltage of systematic survey flash chip unit, records and the threshold value of storage unit is electric
Press distributed intelligence；The step is optional step, and do not have if prediction object does not include if READ-RETRY functions in testing procedure
The step.
(6) test system statistics and preserve the data error rate information of each memory block of flash chip.
(7) repeat step (4) arrives step (6), until flash chip reaches lifetime limitation；Test system statistics flash chip
Program/erase operation cycle number.
The flash memory test system used in step S02, its structure is as shown in figure 3, mainly include host computer testing and control system
System and flash memory control module.Wherein, host computer test system is write programming system by computer language and is realized；Flash memory controls mould
Block is realized by FPGA.
Step S03, data founding mathematical models are handled by intelligent algorithm, will test obtained physical message as algorithm
The input variable of middle mathe-matical map relation, output variable of the flash chip life prediction value as mathe-matical map relation；This implementation
In example the calculation is not limited to using genetic programming algorithm as the intelligent algorithm of founding mathematical models, heretofore described intelligent algorithm
Method.Service life of flash memory value refers to the program/erase periodicity that flash memory products can perform before disabling.
In the present embodiment step S03, flow such as Fig. 4 institutes of service life of flash memory prediction model are established using genetic programming algorithm
Show.According to Fig. 4, concretely comprising the following steps for service life of flash memory prediction model is established：
(1) computer program initialization life prediction function set；Life prediction function screening equation is set.
(2) test data is substituted into each function in life prediction function set；Calculate function result, i.e. flash chip
Life prediction value；The flash chip life prediction value being calculated actual life value corresponding with test data is substituted into fitness
Equation, life prediction function is screened according to fitness equation calculation result.
(3) on the basis of the life prediction function set by screening, new function is generated using gene programmed method
Set.
(4) operation of step (2) and step (3) is repeated to new function set, number of operations reaches the upper of setting
Operation is terminated during limit value；Upper limitation is set according to forecast demand.
(5) the predicted value function optimal with actual life value matching degree is selected from set, obtains life prediction mathematical modulo
Type.
Establish the required data processing operation of flash chip Life Prediction Model to realize by computer program, made
Computer language is not limited to a certain computer language.
It is as shown in Figure 5 according to the definition of gene programming, the expression way of the life prediction function described in step (1).It is described
Function includes operator, coefficient and input variable；Wherein coefficient is the constant that computer program randomly generates, and input variable is volume
(threshold voltage is distributed as optional input and becomes for journey time, erasing time, threshold voltage distribution and several test data set of error rate
Amount)；A kind of test data set represents an input variable, and the input variable number that function is included can be according to prediction need
Ask setting.Computer program can realize life prediction function set by the form of matrix, specific as shown in Figure 6.
Step (2) the fitness equation refers to the absolute value weighted sum of service life of flash memory predicted value and the difference of test value.
Fitness equation is embodied as：F=ω1|A1-B1|+ω2|A2-B2|+…+ωn|An-Bn|；Wherein, fitness equation represents
Symbol is F；Ai represents predicted value；Bi is actual value；ω i are weights, and the value of ω i is more than 0 and is less than or equal to 1；N is total for sample
Number.
The definition programmed according to gene, the operation of the new function set described in step (3) include：The intersection of function, dash forward
Become and breeding operates.The crossover operation of the function is as shown in fig. 7, concrete operations are incited somebody to action to exchange the node of tree function
The function obtained after exchange is as new function set member.The schematic diagram of mutation operation is as shown in figure 8, mutation operation passes through meter
Calculation machine program randomly generates function, and the expression formula branch that the function randomly generated is replaced to former generation's function obtains new offspring's letter
Number.The schematic diagram of gene programming breeding operation is as shown in figure 9, breeding operates the function that will be met the requirements after selection operation by one
Determine probability to be replicated, the function after duplication is as new offspring.
In the present invention, experimental data is divided into two groups：Training data set and validation data set are closed.The present invention is using friendship
The method training mathematical model of fork verification, is divided into 5 groups by experimental data.Wherein 4 groups are used to train, and 1 group is used to verify.Per height
Experimental data set will be all verified once.
Step S04, test Life Prediction Model is closed using validation data set.In the present invention, by calculating root-mean-square error
Test flash memory Life Prediction Model：Wherein, RMSE represents for root-mean-square error
Symbol；N is total sample number；Xobs,iFor i-th of flash chip lifetime measurement value；Xmodel,iI-th of flash chip life prediction mould
Type predicted value.
Step S05, programming time and the erasing time of flash memory to be predicted are measured using the flash memory test platform in step S02
Etc. physical message, the input variable using the physical message that measurement obtains as Life Prediction Model, mathematic(al) expectation prediction model
Output valve predicts the remaining lifetime value of target flash product.
Specific embodiment described herein is only to spirit explanation for example of the invention.Technology belonging to the present invention is led
The technical staff in domain can do various modifications or additions to described specific embodiment or replace in a similar way
Generation, but without departing from spirit of the invention or beyond the scope of the appended claims.
Claims (5)
1. a kind of flash chip life-span prediction method based on mathematical model, it is characterised in that according to a kind of thing of flash chip
The life prediction value of the combined prediction flash chip of reason amount or several physical quantitys；The flash chip physical quantity includes：Flash memory is deposited
Store up the programming time of chip, read access time, the erasing time, program current, read electric current, erasing electric current, threshold voltage distribution and
Error rate；The specific steps of the method include：
Step 1, sample drawn is as sample flash memory from flash memory products set, to treat in addition to sample flash memory in flash memory products set
Test flash memory, and sample flash chip and flash memory test system be connected and starts test collection and establishes flash chip life prediction mould
Flash chip physical message and flash chip life information needed for type；Flash chip to be tested and flash memory are tested into system at the same time
Connection starts the flash chip physical message and flash chip life information needed for test collection prediction model；
Step 2, the combination of a kind of physical message or several physical messages that are obtained testing is as mathe-matical map relation in algorithm
Input variable, output variable of the flash chip life prediction value as mathe-matical map relation, data are handled by intelligent algorithm
Founding mathematical models；
Step 3, test flash memory Life Prediction Model, using the flash chip physical quantity needed for prediction model as Life Prediction Model
Input, mathematic(al) expectation prediction model output valve prediction target flash product remaining lifetime value.
A kind of 2. flash chip life-span prediction method based on mathematical model according to claim 1, it is characterised in that institute
State in step 1, sample flash memory is necessary for the flash chip of same type under same manufacturing process；From the chip of different batches with
Machine extracts the chip sample of identical quantity, to ensure the diversity of sample；Wherein, the batch of sampling is randomly selects, sample number
Amount can be sampled batch flash chip total amount 1 percent, also, flash memory test system includes host computer testing and control
System and flash memory control module；Wherein, host computer test system is write programming system by computer language and is realized；Flash memory controls
Module is realized by FPGA.
A kind of 3. flash chip life-span prediction method based on mathematical model according to claim 1, it is characterised in that institute
State in step 1, flash chip physical message includes：Flash chip is from beginning to use to can not interior flash memory storage during normal use
Programming time, read access time, erasing time, program current, reading electric current, erasing electric current, threshold voltage distribution and the mistake of chip
Rate data message by mistake；In the step 2, the input variable of service life of flash memory prediction mathe-matical map relation is the one of above-mentioned physical message
Kind or several combinations；In the step 1, flash chip life information is flash chip from beginning to use to can not normal use
The program/erase operation cycle number of experience in period.
A kind of 4. flash chip life-span prediction method based on mathematical model according to claim 3, it is characterised in that institute
State
The acquisition modes of flash chip memory block programming time are：Programming time logging modle is set in flash memory test system；
The programming time logging modle clock cycle that record passes through while flash memory starts to write data manipulation is receiving flash chip
Stop recording clock periodicity after returned data programming complement mark；Programming time value is multiplied by programming for clock cycle duration
Clock periodicity；
The acquisition modes of flash chip memory block erasing time are with programming time acquisition modes：During by erasing in test system
Between the lasting clock periodicity of logging modle record erasing operation, when erasing time value is that clock cycle duration is multiplied by erasing
Clock periodicity；Flash memory chip storage unit threshold voltage distribution acquisition modes be：Test system sends READ- to flash chip
The reading reference voltage that flash memory is altered in steps in RETRY command sets reads simultaneously data according to reading data Data-Statistics threshold voltage distribution；
Flash chip storage block error rate acquisition modes be：Test system, which performs flash chip, reads data manipulation from flash memory
Data are read, the test data of the data of reading and write-in is carried out contrast mistake of statistics data amount check, error rate by test system
For number of errors divided by total data amount check.
A kind of 5. flash chip life-span prediction method based on mathematical model according to claim 1, it is characterised in that institute
State in step 1, flash chip physical message and the specific steps of flash chip life information are collected in test to be included：
Step 5.1, the randomly drawing sample chip from flash chip set, sample flash chip is connected with test system；
Step 5.2, randomly choose memory block from each sample flash chip, is sent and surveyed to flash memory storage block by the system of testing
Data acquisition system is tried, write-in data manipulation is performed to flash memory storage block；
Step 5.3, after having sent test data vector, keep in flash memory storage block the data that store for a period of time, during preservation
Between length determined according to the type of flash chip；Flash chip is performed by the system of testing and reads data manipulation, test system will
Data are read compared with the test data sent, records and preserves error data information, do not preserved if not malfunctioning；Preserve
After complete error message, erasing data manipulation performs flash chip by the system of testing；
The number that step 5.4, the operation for repeating step 5.2 and step 5.3, recording step 5.2 and step 5.3 operate；When
When number of operations reaches setting value, each memory block write-in of sample flash memory in the last step 5.2 operation of test system record
The duration of data manipulation simultaneously preserves recorded Duration Information；Meanwhile test the last step 5.3 of system record
The duration of each memory block erasing data manipulation of sample flash memory and recorded Duration Information is preserved in operation；
Step 5.5, the threshold voltage distribution by testing systematic survey flash chip unit, record and the threshold value of storage unit are electric
Press distributed intelligence；The step is optional step, and do not have if prediction object does not include if READ-RETRY functions in testing procedure
The step；
Step 5.6, the data error rate information tested system statistics and preserve each memory block of flash chip；
Step 5.7, repeat step step 5.4 arrive step 5.6, until flash chip reaches lifetime limitation；System statistics is tested to dodge
Deposit the program/erase operation cycle number of chip.
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